CN101657901B - Geometry of MOS device with low on-resistance - Google Patents
Geometry of MOS device with low on-resistance Download PDFInfo
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- CN101657901B CN101657901B CN2007800519011A CN200780051901A CN101657901B CN 101657901 B CN101657901 B CN 101657901B CN 2007800519011 A CN2007800519011 A CN 2007800519011A CN 200780051901 A CN200780051901 A CN 200780051901A CN 101657901 B CN101657901 B CN 101657901B
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Abstract
A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around thedrain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
Description
The cross reference of related application
The application requires the U.S. Provisional Patent Application No.60/882 that submits on December 28th, 2006,250 priority, and the content of this application is incorporated into this by reference, just looks like the same by full disclosure.
Technical field
The present invention relates to the geometric figure of metal-oxide semiconductor (MOS) (MOS) device, have the device of low on-resistance (on-resistance), and relate to particularly and have so geometric square DMOS (SQDMOS) device so that produce.
Background technology
From purpose relatively, Fig. 1 show have grid, the vertical view of the geometric figure (geometry) of traditional metal oxide semiconductor (MOS) structure in drain electrode, source electrode and body (body) district.The width of MOS raceway groove (gate regions) is B, and the length of MOS raceway groove is G.The length S of source and drain region and D respectively based on the design rule of concrete treatment technology to realize a certain reliability and voltage capability.The gross area of MOS is A * B.
The conducting resistance of MOS (Ron) depends on the width B and the length G of MOS raceway groove.Bigger width B causes littler Ron, and littler length G causes littler Ron.Through reducing Ron, can be increased in the number of times of MOS switch in section preset time, and therefore can obtain higher processing speed and the lower energy consumption of each switch events.
Yet when reducing Ron, if the width B of MOS raceway groove increases, the area of MOS possibly increase.The chip that the MOS area that increases can cause in equal area, having less computing capability, the bigger chip that perhaps has the manufacturing cost that is increased.Therefore, the area that reduces Ron and also do not increase simultaneously MOS is only favourable.
The technology of a kind of Ron of reducing comprises two basic MOS structures of ghosted, so that the drain region of each structure is overlapping, shown in the geometric figure of Fig. 2.According to this technology, effective width B is doubled (promptly existing each to have two MOS raceway grooves of width B), thereby has reduced Ron, simultaneously the gross area of this structure less than the twice area of single MOS structure (promptly less than the A of twice * B).Can repeat this structure as illustrated in fig. 3 to obtain even littler Ron.
The invention provides the geometric figure that is used for the MOS device, this geometric figure obtained device Ron's in addition further reduce, also do not increase the area of device simultaneously.
Summary of the invention
The present invention has made full use of the such understanding of inventor: if the form that (on channel region, forming) gate regions is formed with ring centers on the drain region, then increased channel width with respect to given MOS area.In this way, because increased the effective width of raceway groove, thus reduced the Ron of MOS, and do not increase the area of MOS.
Therefore, in one aspect, the invention provides a kind of metal-oxide semiconductor (MOS) (MOS) device and a kind of method that on substrate, forms this MOS device.MOS comprises: the drain region; Center on the gate regions of drain region with the form of ring; Plurality of source regions, these source areas are disposed in around the gate regions and are relative with the drain region; And a plurality of tagmas (bulk region), these tagmas are disposed in around the gate regions and separate source area.
Utilize above-mentioned configuration, reduced the Ron of MOS.The gate regions of Cheng Huan provides the grid width that increases, and does not increase the area of MOS.Through reducing Ron, can increase MOS switch number of times, and therefore can obtain higher processing speed and the lower energy consumption of each switch events.
Compare with traditional structure, the tagma is arranged in around the gate regions and separates source area can provide further reducing of MOS area.Because the tagma is disposed in around the gate regions, so can not need the extra tagma around the source area.In the normal running of MOS, any electric current is not carried in body contact included in the tagma.The body contact provides voltage bias to the tagma of MOS.Therefore, can reduce the number of body contact, and not influence the performance of MOS.Because the tagma can be excluded outside source area, so can reduce the size of source area.Through reducing the area of MOS, in area identical, more computing capability can be provided, perhaps can produce littler chip, thereby reduce manufacturing cost.
Gate regions can be formed closed loop, and gate regions can have and the corresponding shape of the shape of drain region.The drain region can have round-shaped or polygon polygonal shape, and that this polygon polygonal shape comprises is square, one of rectangle, hexagon and octagon.
Channel region can be formed under the gate regions, and channel region can be configured to make electric current to flow to the drain region from each source area.Substrate can have and the corresponding shape of the shape of drain region, and the tagma can be disposed in the corner of substrate.The corner that the tagma is arranged in substrate can make effective channel width maximization.
The MOS device can be a transistor, and substrate can be a silicon substrate.Gate regions can comprise polysilicon, and the MOS device can be square DMOS (SQDMOS).Drain region and at least one source area can have contact separately, and the contact of drain region and the distance between the gate regions can be greater than the contact of source area and the distances between the gate regions, to reach the bigger puncture voltage from the drain region to the source area.
On the other hand, the invention provides a kind of metal-oxide semiconductor (MOS) (MOS) device and a kind of method that is used to form this MOS device, this MOS device has a plurality of MOS transistors unit that on substrate, forms with array format.Each MOS transistor unit comprises: the drain region; Gate regions around the drain region; Plurality of source regions, these source areas are disposed in around the gate regions and on the opposite, drain region; And a plurality of tagmas, these tagmas are disposed in around the gate regions and separate source area.The form that gate regions is formed with ring centers on the drain region.The respective sources polar region of source area and adjacent mos transistors unit is overlapping.
Providing of this simplified summary is in order to understand essence of the present invention rapidly.Through the following detailed description of the reference preferred embodiment of the present invention relevant, can obtain to understand more completely to of the present invention with accompanying drawing.
Description of drawings
Fig. 1, Fig. 2 and Fig. 3 are the diagrammatic sketch of the vertical view of metal-oxide semiconductor (MOS) (MOS) structure of having described to be used for comparison or MOS cellular array.
Fig. 4 is the diagrammatic sketch of having described according to the vertical view of the MOS structure of first embodiment of the invention.
Fig. 5 A and Fig. 5 B are the diagrammatic sketch of having described according to the vertical view of the MOS cellular array of second embodiment of the invention.
Fig. 6 A is the block diagram of the present invention in the hard disk drive.
Fig. 6 B is the block diagram of the present invention in the DVD driver.
Fig. 6 C is the block diagram of the present invention in the high definition TV (HDTV).
Fig. 6 D is the block diagram of the present invention in the vehicle control system.
Fig. 6 E is the block diagram of the present invention in honeycomb or the mobile phone.
Fig. 6 F is the block diagram of the present invention in the STB (STB).
Fig. 6 G is the block diagram of the present invention in the media player.
Fig. 6 H is the block diagram of the present invention in the VoIP player.
Embodiment
Fig. 4 is the diagrammatic sketch of vertical view of having described metal-oxide semiconductor (MOS) (MOS) structure of single MOS according to an embodiment of the invention unit (cell) 400.As shown in Figure 4, unit 400 is formed square shape, but in other embodiments, unit 400 can have round-shaped or any polygon polygonal shape, for example rectangle, hexagon or octagon.Unit 400 can be a MOS transistor for example, comprises NMOS and PMOS transistor, and unit 400 can be square DMOS (Square DMOS) (SQDMOS).Unit 400 comprises drain region 401, gate regions 402, source area 404 and 405 and the tagma 406 that on substrate, forms at least, and substrate for example is the substrate of silicon substrate or any other suitable type.
As shown in Figure 4, drain region 401 is formed square shape, but in other embodiments, drain region 401 can have round-shaped or any polygon polygonal shape, for example rectangle, hexagon or octagon.Drain region 401 comprises drain contact (contact) 409.As shown in the figure, show two drain contacts 409, but other embodiment can use the drain contact of different numbers, this part ground depends on action need, for example electric current needs.Drain contact 409 is spliced (butt) is used for given current capacity with optimization area.In an illustrated embodiment, the distance B 1 to D4 between drain contact 409 and the gate regions 402 is similar basically, but in other embodiments, distance B 1 to D4 can be different, and this part ground depends on the shape of drain region 401.
Because tagma 406 is not arranged in source area 404 and 405 as in conventional MOS unit (Fig. 1), so the size of source area 404 and 405 can be less than the size of source area in the conventional MOS unit.
As shown in the figure, source area 404 and 405 is formed the shape of rectangle, and tagma 406 is formed square shape with zone 407.Yet; In other embodiments; Source area 404 and 405, tagma 406 and zone 407 can have round-shaped or any polygon polygonal shape; For example triangle, square, rectangle, hexagon or octagon, this part ground depend on shape and source area 404 and 405, the tagma 406 of unit 400 and regional 407 layout and/or shape.
As stated, zone 407 can comprise the gate contacts (not shown) that is electrically coupled to gate regions 402.Tagma 406 comprises body contact 411, and source area 404 and 405 comprises source contact 410.Can use in other embodiments with shown in the source contact 410 and body contact 411 of the different numbers in contact of number, this part ground depends on action need, for example electric current needs.
As shown in the figure; Shorter than the distance B between drain contact 409 and the gate regions 402 1 between source contact 410 and the gate regions 402 to D4 apart from S1; But in other embodiments, can be different apart from S1 and D1 to the relation between the D4, this part ground depends on puncture voltage.
Fig. 5 A is the diagrammatic sketch of vertical view of having described the array of four MOS unit 500 according to one example embodiment.Each unit all has the structure of the MOS unit 400 of Fig. 4.Unit 501 to 504 is arranged such that their source area 404 and 405 is overlapping.In this way, the gross area of cell array 500 can be less than four times of the area of individual cell 400.
Through arranging that thereby gate regions 402 makes it be looped around around the drain region 401, channel width can increase the gate regions part 510,511,520,521,530,531,540 and 541 shown in Fig. 5 B.Though some channel widths possibly lost, because under zone 407, possibly there not be effective raceway groove (promptly source area and drain region possibly not separated in zone 407), this loss can be less than the gain on the channel width.
In this way, the structure of MOS unit 400 (with MOS cell array 500) can have the littler Ron of Ron than conventional MOS unit (or cell array).Through gate regions 402 is looped around around the drain region 401, can increase clean channel width, and not increase the area of MOS structure.Through reducing Ron, can increase MOS switch number of times, and therefore can obtain higher processing speed and the lower energy consumption of each switch events.
Because the tagma is disposed in around the gate regions, so can not need the extra tagma around the source area.Because the tagma can not be included in the source area, so the size of source area can reduce.Through reducing the area of MOS, in area identical, more computing capability can be provided, perhaps can produce littler chip, thereby reduce manufacturing cost.
With reference now to Fig. 6 A-Fig. 6 H,, shows various exemplary implementation of the present invention.With reference to figure 6A, the present invention can be embodied as the MOS device in the hard disk drive 1500.The present invention can realize any or both in signal processing and/or the control circuit, and these circuit usually are designated 1502 in Fig. 6 A.In some implementations, but other circuit (not shown) deal with data among signal processing and/or control circuit 1502 and/or the HDD 1500, carry out coding and/or encrypt, carry out and calculate and/or format exports the data of magnetic storage medium 1506 and/or the data that receive from magnetic storage medium 1506 to.
With reference now to Fig. 6 B,, the present invention can be embodied as the MOS device in digital versatile disc (DVD) driver 1510.The present invention can realize the signal processing of DVD driver 1510 and/or any or both (these circuit usually are designated 1512 in Fig. 6 B) and/or the bulk data storage device 1518 in the control circuit.But other circuit (not shown) deal with data among signal processing and/or control circuit 1512 and/or the DVD 1510, carry out coding and/or encrypt, carry out and calculate and/or the format data of reading from optical storage media 1516 and/or the data that write optical storage media 1516.In some implementations, other circuit (not shown) among signal processing and/or control circuit 1512 and/or the DVD 1510 also can be carried out other functions, such as coding and/or decoding and/or any other signal processing function of being associated with the DVD driver.
With reference now to Fig. 6 C,, the present invention can be embodied as the MOS device in the high definition TV (HDTV) 1520.The present invention can realize any or both (these circuit usually are designated 1522 in Fig. 6 C), WLAN interface and/or the bulk data storage device in signal processing and/or the control circuit of HDTV 1520.HDTV 1520 receives the HDTV input signal of wired or wireless form, and generates the HDTV output signal that is used for display 1526.In some implementations, but other circuit (not shown) deal with data of signal processing circuit and/or control circuit 1522 and/or HDTV 1520, carry out coding and/or encrypt, carry out calculating, formatted data and/or carry out any other type that possibly need HDTV handle.
With reference now to Fig. 6 D,, the present invention can be embodied as the MOS device in the control system of vehicle 1530, the WLAN interface and/or the bulk data storage device of vehicle control system.In some implementations; The present invention realizes power assembly (powertrain) control system 1532; The input that power assembly control system 1532 receives from the one or more transducers such as temperature sensor, pressure sensor, rotation sensor, pneumatic sensor and/or any other right sensors; And/or generate one or more output control signals, such as engine operation parameters, transmission operating parameter and/or other control signals.
The present invention also may be implemented in the other control system 1540 of vehicle 1530.Control system 1540 can receive similarly from the signal of input pickup 1542 and/or export control signal to one or more output equipments 1544.In some implementations, control system 1540 can be the part of anti-lock braking system (ABS), navigation system, teleprocessing (telematics) system, vehicle remote information processing system, deviation system, adaptive cruise control system, the vehicle entertainment system such as stereo, DVD, CD etc.Also can expect other implementations.
Power assembly control system 1532 can be communicated by letter with the bulk data storage device 1546 with the non-volatile storage data.Bulk data storage device 1546 can comprise light and/or magnetic storage apparatus, for example hard disk drive HDD and/or DVD.At least one HDD can have the configuration shown in Fig. 6 A and/or at least one DVD can have the configuration shown in Fig. 6 B.HDD comprises that one or more diameters are less than about 1.8 " the small-sized HDD of dish.Power assembly control system 1532 can be connected to memory 1547, for example the nonvolatile memory of RAM, ROM, the low latency such as flash memory and/or other suitable electronic data storage device structures.Power assembly control system 1532 also can be supported to be connected with WLAN via wlan network interface 1548.Control system 1540 also can comprise bulk data storage device, memory and/or WLAN interface (all not shown).
With reference now to Fig. 6 E,, the present invention can be embodied as the MOS device in the cell phone 1550, and cell phone 1550 can comprise cellular antenna 1551.The present invention can realize any or both (these circuit usually are designated 1552 in Fig. 6 E), WLAN interface and/or the bulk data storage device in signal processing and/or the control circuit of cell phone 1550.In some implementations, cell phone 1550 comprises microphone 1556, the audio frequency such as loud speaker and/or audio frequency output socket output 1558, display 1560 and/or input equipment 1562 such as keyboard, some optional equipment, voice activity and/or other input equipments.But other circuit (not shown) deal with data in signal processing and/or control circuit 1552 and/or the cell phone 1550, carry out coding and/or encrypt, carry out calculating, formatted data and/or carry out other cellular telephone functions.
Cell phone 1550 can be communicated by letter with the bulk data storage device 1564 with the non-volatile storage data such as light and/or magnetic storage apparatus, wherein for example hard disk drive HDD and/or DVD of light and/or magnetic storage apparatus.At least one HDD can have the configuration shown in Fig. 6 A and/or at least one DVD can have the configuration shown in Fig. 6 B.HDD comprises that one or more diameters are less than about 1.8 " the small-sized HDD of dish.Cell phone 1550 can be connected to memory 1566, for example the nonvolatile memory of RAM, ROM, the low latency such as flash memory and/or other suitable electronic data storage device structures.Cell phone 1550 also can be supported to be connected with WLAN via wlan network interface 1568.
With reference now to Fig. 6 F,, the present invention can be embodied as the MOS device in the STB 1580.The present invention can realize any or both (these circuit usually are designated 1584 in Fig. 6 F), WLAN interface and/or the bulk data storage device in signal processing and/or the control circuit of STB 1580.The signal that STB 1580 receives from the source such as broad band source, and output is applicable to the standard and/or the high definition audio/vision signal of the display 1588 such as TV and/or monitor and/or other video and/or audio output equipments.But other circuit (not shown) deal with data of signal processing and/or control circuit 1584 and/or STB 1580, carry out coding and/or encrypt, carry out calculating, formatted data and/or carry out any other set-top box functionality.
With reference now to Fig. 6 G,, the present invention can be embodied as the MOS device in the media player 600.The present invention can realize any or both (these circuit usually are designated 604 in Fig. 6 G), WLAN interface and/or the bulk data storage device in signal processing and/or the control circuit of media player 600.In some implementations, media player 600 comprises that display 607 and/or user such as keyboard, touch pad etc. import 608.In some implementations, media player 600 can use graphic user interface (GUI), and graphic user interface (GUI) is generally imported 608 via display 607 and/or user and used menu, drop down menu, icon and/or click the interface.Media player 600 also comprises the audio frequency output 609 such as loud speaker and/or audio frequency output socket.But other circuit (not shown) deal with data of signal processing and/or control circuit 604 and/or media player 600, carry out coding and/or encrypt, carry out calculating, formatted data and/or carry out any other functions.
Media player 600 can with communicate by letter such as audio frequency and/or the bulk data storage device 610 of the data the video content of compression with non-volatile storage.In some implementations, the audio file of compression comprises the file that meets MP3 format or other proper compression audio frequency and/or video format.Bulk data storage device can comprise light and/or magnetic storage apparatus, for example hard disk drive HDD and/or DVD.At least one HDD can have the configuration shown in Fig. 6 A and/or at least one DVD can have the configuration shown in Fig. 6 B.HDD comprises that one or more diameters are less than about 1.8 " the small-sized HDD of dish.Media player 600 can be connected to memory 614, for example the nonvolatile memory of RAM, ROM, the low latency such as flash memory and/or other suitable electronic data storage device structures.Media player 600 also can be supported to be connected with WLAN via wlan network interface 616.Also can expect except that above-mentioned those other implementations implementation.
With reference to figure 6H, the present invention can be embodied as the MOS device in IP phone (VoIP) phone 620, and voip phone 620 can comprise antenna 621.The present invention can realize any or both (these circuit usually are designated 622 in Fig. 6 H), wave point and/or the bulk data storage device in signal processing and/or the control circuit of voip phone 623.In some implementations, voip phone 620 partly comprises microphone 624, the output of the audio frequency such as loud speaker and/or audio frequency output socket 625, display monitor 626, input equipment 627 and Wireless Fidelity (Wi-Fi) communication module 628 such as keyboard, some optional equipment, voice activity and/or other input equipments.But other circuit (not shown) deal with data in signal processing and/or control circuit 622 and/or the voip phone 620, carry out coding and/or encrypt, carry out calculating, formatted data and/or carry out other voip phone functions.
Voip phone 620 can be communicated by letter with the bulk data storage device 623 with the non-volatile storage data such as light and/or magnetic storage apparatus, wherein for example hard disk drive HDD and/or DVD of light and/or magnetic storage apparatus.At least one HDD can have the configuration shown in Fig. 6 A and/or at least one DVD can have the configuration shown in Fig. 6 B.HDD comprises that one or more diameters are less than about 1.8 " the small-sized HDD of dish.Voip phone 620 can be connected to memory 629, and memory 629 can be nonvolatile memory and/or other suitable electronic data storage device structure of RAM, ROM, the low latency such as flash memory.Voip phone 620 is configured to via the communication link of Wi-Fi communication module 628 foundation with the voip network (not shown).
More than with regard to concrete exemplary embodiment the present invention has been described.Should be appreciated that to the invention is not restricted to the foregoing description, and under the situation that does not break away from the spirit and scope of the present invention, can carry out various changes and modification by those skilled in the relevant art.
Claims (25)
1. a metal-oxide semiconductor (MOS) that on substrate, forms (MOS) device comprises:
The drain region;
Gate regions, said gate regions be around said drain region, and be formed and be looped around around the said drain region;
Plurality of source regions, said plurality of source regions are disposed in around the said gate regions and are relative with said drain region; And
A plurality of tagmas, said a plurality of tagmas are disposed in around the said gate regions and separate said source area,
Wherein said plurality of source regions is disposed on each side of said gate regions, and arrangement makes each side of said drain region equate or the source area of bigger width is aimed at having.
2. MOS device according to claim 1, wherein said gate regions is formed closed loop.
3. MOS device according to claim 2, wherein said gate regions have and the corresponding shape of the shape of said drain region.
4. MOS device according to claim 3, wherein said drain region has polygon polygonal shape, and that said polygon polygonal shape comprises is square, one of rectangle, hexagon and octagon.
5. MOS device according to claim 4, wherein said substrate have and the corresponding shape of the shape of said drain region, and said tagma is disposed in the corner of said substrate.
6. MOS device according to claim 3, wherein said drain region has round-shaped.
7. MOS device according to claim 1, wherein channel region is formed under the said gate regions.
8. MOS device according to claim 7, wherein said channel region are configured to make electric current to flow to said drain region from each source area.
9. MOS device according to claim 1, wherein said MOS device is a transistor.
10. MOS device according to claim 1, wherein said substrate is a silicon substrate, and said gate regions comprises polysilicon.
11. MOS device according to claim 10, wherein said MOS device are square DMOS (SQDMOS).
12. MOS device according to claim 1; Wherein said drain region has contact separately with at least one said source area, and the distance between the contact of said drain region and the said gate regions is greater than the contact of said source area and the distance between the said gate regions.
13. a metal-oxide semiconductor (MOS) (MOS) device, said MOS device have a plurality of MOS transistors unit that on substrate, forms with array format, each MOS transistor unit comprises:
The drain region;
Gate regions, said gate regions centers on said drain region, and is formed the form of ring; And
Plurality of source regions, said plurality of source regions are disposed in around the said gate regions and are relative with said drain region; And
A plurality of tagmas, said a plurality of tagmas are disposed in around the said gate regions and separate said source area;
The respective sources polar region of wherein said source area and adjacent mos transistors unit is overlapping,
Wherein said plurality of source regions is disposed on each side of said gate regions, and arrangement makes each side of said drain region equate or the source area of bigger width is aimed at having.
14. a method that is used on substrate, forming metal-oxide semiconductor (MOS) (MOS) device comprises:
Form the drain region;
Form gate regions, said gate regions centers on said drain region with the form of ring;
Form plurality of source regions, said plurality of source regions is disposed in around the said gate regions and is relative with said drain region; And
Form a plurality of tagmas, said a plurality of tagmas are arranged in around the said gate regions and separate said source area,
Wherein said plurality of source regions is disposed on each side of said gate regions, and arrangement makes each side of said drain region equate or the source area of bigger width is aimed at having.
15. method according to claim 14, wherein said gate regions forms with closed loop.
16. method according to claim 15, wherein said gate regions have and the corresponding shape of the shape of said drain region.
17. method according to claim 16, wherein said drain region has polygon polygonal shape, and that said polygon polygonal shape comprises is square, one of rectangle, hexagon and octagon.
18. method according to claim 17, wherein said substrate have and the corresponding shape of the shape of said drain region, and said tagma is disposed in the corner of said substrate.
19. method according to claim 16, wherein said drain region has round-shaped.
20. method according to claim 14 also is included under the said gate regions and forms channel region.
21. method according to claim 20, wherein said channel region are configured to make electric current to flow to said drain region from each source area.
22. method according to claim 14, wherein said substrate is a silicon substrate, and said gate regions comprises polysilicon.
23. method according to claim 22, wherein said MOS device are square DMOS (SQDMOS).
24. method according to claim 14; Also be included in the contact that forms in said drain region and the said source area separately, the distance between the contact of wherein said drain region and the said gate regions is greater than the contact of said source area and the distance between the said gate regions.
25. a method that is used on substrate, forming metal-oxide semiconductor (MOS) (MOS) transistor unit comprises:
On said substrate, form a plurality of MOS transistors unit, wherein each MOS transistor unit forms through following steps:
Form the drain region;
Form gate regions, said gate regions centers on said drain region with the form of ring;
Form plurality of source regions, said plurality of source regions is disposed in around the said gate regions and is relative with said drain region; And
Form a plurality of tagmas, said a plurality of tagmas are disposed in around the said gate regions and separate said source area;
Wherein the source area separately of adjacent mos transistors unit is overlapping,
Wherein said plurality of source regions is disposed on each side of said gate regions, and arrangement makes each side of said drain region equate or the source area of bigger width is aimed at having.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210147239.2A CN102709285B (en) | 2006-12-28 | 2007-12-26 | There is the geometric figure of the MOS device of low on-resistance |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88225006P | 2006-12-28 | 2006-12-28 | |
| US60/882,250 | 2006-12-28 | ||
| PCT/US2007/088866 WO2008083180A2 (en) | 2006-12-28 | 2007-12-26 | Geometry of mos device with low on-resistance |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210147239.2A Division CN102709285B (en) | 2006-12-28 | 2007-12-26 | There is the geometric figure of the MOS device of low on-resistance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101657901A CN101657901A (en) | 2010-02-24 |
| CN101657901B true CN101657901B (en) | 2012-07-04 |
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| CN201210147239.2A Expired - Fee Related CN102709285B (en) | 2006-12-28 | 2007-12-26 | There is the geometric figure of the MOS device of low on-resistance |
| CN2007800519011A Expired - Fee Related CN101657901B (en) | 2006-12-28 | 2007-12-26 | Geometry of MOS device with low on-resistance |
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| CN201210147239.2A Expired - Fee Related CN102709285B (en) | 2006-12-28 | 2007-12-26 | There is the geometric figure of the MOS device of low on-resistance |
Country Status (6)
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| US (1) | US9466596B2 (en) |
| EP (1) | EP2100334B1 (en) |
| JP (2) | JP5360829B2 (en) |
| CN (2) | CN102709285B (en) |
| TW (1) | TWI456758B (en) |
| WO (1) | WO2008083180A2 (en) |
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| CN102403310A (en) | 2010-09-13 | 2012-04-04 | 登丰微电子股份有限公司 | Metal oxide semiconductor field-effect transistor layout and structure |
| CN102142462B (en) * | 2011-02-25 | 2012-08-29 | 北京大学 | Power MOS transistor of asymmetric structure and array thereof |
| WO2012158174A1 (en) * | 2011-05-19 | 2012-11-22 | Hewlett-Packard Development Company, L.P. | Device active channel length/width greater than channel length/width |
| KR20150092828A (en) * | 2014-02-06 | 2015-08-17 | 정덕영 | 4-terminal FET for Battery Charging and discharging control circuit |
| CN105097916A (en) | 2014-05-05 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor device and manufacturing method thereof |
| CN104409503B (en) * | 2014-11-21 | 2017-05-17 | 中国科学院上海微系统与信息技术研究所 | Layout design of MOSFET with multiple interdigital grid electrode structures |
| US9356105B1 (en) * | 2014-12-29 | 2016-05-31 | Macronix International Co., Ltd. | Ring gate transistor design for flash memory |
| EP3062349B1 (en) | 2015-02-25 | 2019-10-09 | Nxp B.V. | Semiconductor device comprising a switch |
| CN106328508B (en) * | 2016-08-22 | 2019-02-01 | 上海华力微电子有限公司 | Improve the method for the gate corners of active area boundary |
| EP3352224B1 (en) * | 2017-01-24 | 2020-03-11 | Nxp B.V. | Semiconductor device comprising a switch |
| US10811497B2 (en) | 2018-04-17 | 2020-10-20 | Silanna Asia Pte Ltd | Tiled lateral BJT |
| US11309353B2 (en) * | 2020-04-30 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer-defined back-end transistor as memory selector |
| CN111599807B (en) * | 2020-05-22 | 2023-09-01 | 赛卓电子科技(上海)股份有限公司 | Differential input pair tube for improving performance under standard MOS process and improving method |
| CN116344530A (en) * | 2021-12-24 | 2023-06-27 | 长鑫存储技术有限公司 | Transistor unit, array thereof and integrated circuit |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI456758B (en) | 2014-10-11 |
| JP2010515274A (en) | 2010-05-06 |
| CN102709285A (en) | 2012-10-03 |
| EP2100334A2 (en) | 2009-09-16 |
| EP2100334A4 (en) | 2011-03-23 |
| WO2008083180A3 (en) | 2008-08-28 |
| CN101657901A (en) | 2010-02-24 |
| WO2008083180A2 (en) | 2008-07-10 |
| EP2100334B1 (en) | 2016-04-13 |
| CN102709285B (en) | 2015-09-16 |
| JP2013179336A (en) | 2013-09-09 |
| JP5360829B2 (en) | 2013-12-04 |
| JP5726230B2 (en) | 2015-05-27 |
| US9466596B2 (en) | 2016-10-11 |
| TW200849591A (en) | 2008-12-16 |
| US20080157195A1 (en) | 2008-07-03 |
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