JPS61290767A - Mos field-effect transistor - Google Patents

Abstract

PURPOSE:To form a MOS field-effect transistor having large W/L in a comparatively small-sized layout space having a fine shape by shaping a gate electrode in the two-dimensional directions to a source region. CONSTITUTION:A MOS field-effect transistor takes an N-channel type, and is formed to a P<-> type semiconductor base body 1. The N-channel MOS field- effect transistor has a drain region 2 and a source region 3 by N<+> type diffusion layers and a gate electrode 4 shaped extending over both regions 2 and 3. With the MOS field-effect transistor M1, the drain region 2 is arranged so as to surround the periphery of the source region 3 from all directions while the gate electrode 4 is shaped annularly along a section between both regions 2 and 3. That is, the source region 3 and the drain region 2 are disposed so as to be adjoined mutually from the plural directions while the gate electrode 4 is formed in the plural directions to the source region 3.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor device technology and MOS field effect transistors. The present invention relates to a technique that is effective when applied to effect transistors.

[Background technology]

In general, MOS field effect transistors are frequently used not only as single active elements but also as active elements in semiconductor integrated circuit devices. For example, in the field of digital semiconductor integrated circuit devices such as micro processors, many devices employ MOS field effect transistors as active elements.

By the way, in a conventional MO5 field effect transistor, as shown in the layout state in FIG. Electrode 4 was formed. In this case, as shown in the figure, the regions 2.3 are arranged so as to be adjacent to each other only from a single direction, and the gate electrode 4 is formed to straddle the regions. Note that D represents a source, G represents a gate, and S represents a source.

Here, the characteristics of this type of MOS field effect transistor,
%, important characteristics such as input threshold and drain current largely depend on the length L of the channel formed between the drain region 2 and the source region 30 and the width W of the gate electrode 40.

In order to obtain a large drain current without increasing the input threshold, the ratio of the channel length to the gate width W, so-called W/L, must be made as large as possible.

In this case, the lower limit of the channel length is determined by the minimum processing dimension. Therefore, in order to increase W/L, the gate width W must be made thicker.

However, when the gate width W is increased in order to increase W/L with a MOS field effect transistor having a conventional layout shape as shown in FIG. 7, the layout shape of the MOS field effect transistor becomes vertical. Alternatively, such irregularly shaped elements, which are extremely long on one side only, make it difficult to rationally design the layout and make effective use of the limited element formation area of the semiconductor chip. The inventors of the present invention have clarified that there is a problem in that it causes various adverse effects such as interference.

Regarding MOS field effect transistors.

For example, "Integrated Circuit Engineering (1)" published by Corona Publishing Co., Ltd., co-authored by Hisayoshi Yanai and Minoru Nagata, published April 5, 1970, 138-14.
[Object of the Invention] The object of the invention is to form a MOS field effect transistor with a large W/L in a relatively small size and a well-shaped layout space. It is an object of the present invention to provide a technology that facilitates rational layout design and makes effective use of the limited element formation area of a semiconductor chip.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

That is, by forming the gate electrode in two dimensions with respect to the source region, it is possible to form a MOS field effect transistor with a large W/L in a relatively small size and well-shaped layout space. To facilitate rational layout design and to effectively utilize the limited element formation area of a semiconductor chip.

This goal is achieved.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

Note that in one drawing, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a MOS field effect transistor according to the invention.

In the figure, (a) shows the planar layout shape.

(b) shows the cross-sectional state of the B-8 portion, and (C) shows its equivalent circuit.

The MOSO8 field effect transistor shown in FIG. 1 is a one-channel type, and is formed on a p-type semiconductor substrate 1. This n-channel +MOSt field effect transistor is
It has a drain region 2 and a source region made of an n+ type scattering layer, and a gate electrode 4 formed across both regions 2 and 3. Reference numeral 5 indicates a lead-out portion of an electrode for wiring made of K such as aluminum. Also, D is the drain, S is the source, and G
indicate the respective gates.

Here, MOSO8 field effect transistor case 1 of the example
As shown in FIG. 2(a), the drain region 2 is arranged to surround the source region 30 from all sides, and
A gate electrode 4 is formed in an annular shape along between both regions 2 and 3. That is, the source region 3 and the drain ramp 2 are arranged adjacent to each other in multiple directions, and the gate electrode 4 is formed in multiple directions with respect to the source region 3.

With the above configuration, as is clear from FIG. 1(a), M with a long gate width (W) can be arranged in a well-shaped layout shape where neither K in the vertical or horizontal directions is extremely long.
An OSO8 field effect transistor can be constructed. From this, a MOS field effect transistor with good characteristics such as threshold voltage and drain current can be formed in a relatively small size and well-shaped layout space. Also.

As well as facilitating the rational design of the layout.

It becomes possible to effectively utilize the limited element formation area of a semiconductor chip.

FIG. 2 shows another embodiment of the invention.

In the figure, (a) shows the planar layout shape.

(b) shows the equivalent circuit, and (C) shows the equivalent circuit symbolized.

This embodiment is basically similar to the embodiment described above. Therefore, the following explanation will focus on the differences from the above-described embodiment, and the other parts will be indicated using the same reference numerals in the drawings.

In the MOS field effect transistor shown in the figure, the drain region 2 is divided into a plurality (four) as shown in (a). From this k, one MOS field effect transistor has four drains DI, D2°D3 . A MOS field effect transistor with a multi-electrode structure having D4 is constructed. In this case, the plurality of drains DI, D2,
D3 and D4 are electrically independent. Therefore, functionally, it has the same function as a circuit unit formed by commonly connecting the gates G and sources S of a plurality of MO5 field effect transistors M1, M2, M3, and M4, respectively, as shown in FIG. . If the symbol of this circuit unit were to be expressed, it would look like (C).

Furthermore, if the drains DI, D2, D3, and D4 are commonly connected to each other, it can be used as a MOS field effect transistor with a large W/L.

FIG. 3 shows yet another embodiment of the invention.

In the same figure, (a) shows the planar layout shape of Φ
) indicate their equivalent circuits.

In the MOS field effect transistor of the embodiment shown in the figure,
(a) K shows 5K, multiple drain regions 2 (four)
In addition to being divided, the gate electrode 4 is also divided into a plurality of parts (four parts). From this K, there are four drains DI, D2 . D3. D4
and a plurality of gates Gl, G2 . G3. A MOS field effect transistor with a multi-electrode structure having G4 is constructed. In this case, the plurality of drains D1. D2. D3°D4 and a plurality of gates G1. G2. G3. G4 are electrically independent, and only the source S is common to them.

Therefore, functionally, as shown in (b)K, there are a plurality of (four) independent MOS field effect transistors Ml.
, M2, M3, and M4. Note that a channel stopper is formed in the portion indicated by reference numeral 6.

Also, each drain DI, D2, D3, D4 and each gate G1. G2. G3. If G4 are commonly connected to each other, it can be used as an MO5 field effect transistor with a large W/L.

FIG. 4 shows an example of application of the MOS field effect transistor shown in FIG.

As shown in the figure, for example, switches S1, S2, 5K, etc. are connected by using the aforementioned MOS field effect transistors. S
3. A circuit that performs logical processing (logical product or logical sum) on each operating state of S4 can be easily configured. In the figure, Vdd represents a power source, Vcs represents a constant power source, Ro represents a load resistance, and out represents an output.

FIG. 5 shows another example of application of the MOS field effect transistor shown in FIG.

As shown in the figure, the above-described MOS field effect transistor can be used to constitute the main part of an A/D converter, for example. In the same figure, IR, 2R, 4R,
8R indicates each weighted resistance.

Ro indicates load resistance.

This A/D converter converts a digital signal consisting of multiple bits (4 bits) into multiple (4) gates (G1).

By applying it to G2, G3, and G4 in parallel, an analog signal of a level corresponding to the value of the digital signal can be extracted from the output out.

FIG. 6 shows yet another embodiment of the invention.

As shown in the figure, by arranging a large number of source/drain regions 23 regularly in advance and making it possible to arbitrarily design only the formation location of the gate electrode 4 and the pattern of the multilayer wiring (not shown), it is possible to Like a gate array, a two-dimensional circuit network can be arbitrarily configured according to customer orders and other FCs.It is 5Vc.

〔effect〕

(11) By forming the gate electrode in two dimensions for the source region, it has become possible to form a MOS field effect transistor with a large W/L using a relatively small size and well-shaped layout base. This makes it easy to rationally design the layout, and makes effective use of the limited element formation area of the semiconductor chip.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the MOS field effect transistor may be of a p-channel type. Alternatively, the source region 3 may be formed around the drain region 2, and the source region may be further divided.

[Application field]

Although the invention made by the present inventor is applied to digital MOS technology, which is the background field of application, the present invention is not limited thereto, and can be applied to, for example, analog MOS technology.

[Brief explanation of the drawing]

FIGS. 1(a) = (b) and (c) are diagrams showing an embodiment of a MOS field effect transistor according to the present invention. FIGS. 2(a), (b), and (c) are views showing another embodiment of the MOS field effect transistor according to the present invention, and FIGS. 3(a) and (b) are views showing another embodiment of the MOS field effect transistor according to the present invention. The figure which shows another Example. FIG. 4 is a circuit diagram showing an application example of the MOS field effect transistor shown in FIG. 2. FIG. 5 is a circuit diagram showing an application example of the MOS field effect transistor shown in FIG. 3. FIG. 6 is a layout state diagram showing still another embodiment of the present invention. FIG. 7 is a layout state diagram showing the configuration of a conventional MOS field effect transistor. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Drain region, 3...
Source region, 4... Gate electrode, 23... Source
Drain region, 25... Isolation region. Pa.) Figure 1 (C) Figure 2 (Yun (tears)
(Cn Fig. 3 (Etsumi n r > 7 Fig. 4 Fig. 5 Fig. 6 Fig. 7

Claims (1)

[Claims] 1. A MOS field effect transistor having a drain region, a source region, and a gate electrode formed across both regions, the source region and the drain region being adjacent to each other from multiple directions. A MOS field effect transistor characterized in that a gate electrode is formed in a plurality of directions with respect to a source region or a drain region. 2. The MOS field effect transistor according to claim 1, wherein the drain region is divided into a plurality of parts.