JP2002110970A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can realize high breakdown voltage by suppressing generation of electric field concentrated spots by effectively increasing the expansion widths of depletion layers. SOLUTION: Although the depleted layers 26 are formed in an n-type silicon layer 11 and off-set regions 13 by forming p-n junction with body regions 15, the body regions 15 are provided to surround the off-set regions 13. Consequently, the depleted layers 26, which expand toward the off-set regions 13 from the body regions 15, expand toward the insides of the regions surrounded by the body regions 15. Therefore, the widths of the depleted layers 26 can be increased effectively, and the concentration of electric fields can be suppressed, because the depleted layers 26 expanding in two directions are combined at the corner sections of the body regions 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure for improving a breakdown voltage of a high breakdown voltage type semiconductor device by reducing electric field concentration at a pn junction. .

[0002]

2. Description of the Related Art Conventionally, there has been known a power IC in which a high breakdown voltage type semiconductor device used for a high breakdown voltage driving circuit and the like and a low breakdown voltage type semiconductor device used for a low breakdown voltage driving circuit and the like are provided on the same substrate. And various uses have been devised. The above-mentioned semiconductor device is mainly a MOS transistor, and a high breakdown voltage type MOS transistor arranged at the output stage of this type of power IC is required to have two contradictory characteristics of a high breakdown voltage and a low on-resistance. I have.

A conventional high breakdown voltage MOS transistor will be described with reference to FIGS. FIG.
(A) is LDMOS (Lateral Double-Diffused MOS)
3A and 3B illustrate a structure of a transistor, in which FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along line AA ′ in FIG.

As shown in the figure, a p ⁺ type silicon substrate 10
An n ⁻ -type epitaxial silicon layer 110 is provided on 0, and an n ⁺ -type buried layer 120 is provided at the junction between the two. In the surface region of n ⁻ type silicon layer 110, p type impurity diffusion layer 150 serving as a body region is provided so as to have a stripe shape.
Inside, an n ⁺ -type impurity diffusion layer 160 serving as a source region and ap ⁺ -type impurity diffusion layer 17 serving as a contact region with an electrode
0 is provided. Further, an n ⁺ -type impurity diffusion layer 140 serving as a drain region is provided in the surface region of the n ⁻ -type silicon layer 110 so as to surround the body region 150. The n ⁻ -type impurity diffusion layer 130 serving as an offset region
Is provided.

The gate electrode 210 extends from the source region 160 to the drain region 140 with the gate insulating film 190 and the thick insulating film 200 interposed therebetween.
0 is provided. A drain electrode 220 is formed on the drain region 140, and a source electrode 230 is formed on the source region 160 and the contact region 170.
Are provided to form an LDMOS transistor.

As described above, in particular, a high breakdown voltage type LDMOS
In the transistor, the source and drain regions 160 and 14
By making the shape of 0 a stripe, the channel width is designed to be large, and it corresponds to a large current operation. In this configuration, an offset gate structure is adopted, the distance between the drain region 140 and the gate electrode 210 is increased, and the electric field concentration is relaxed by the n ⁻ -type offset region 130 to maintain a high voltage, thereby improving the drain breakdown voltage. Let me. However, since it is necessary to provide the body region 150 having the p-type conductivity, a decrease in the breakdown voltage due to the pn junction with the body region 150 arises as a new problem.

FIGS. 16A and 16B respectively show FIGS.
FIG. 3B is an enlarged view of a region 250 in FIG.
FIGS. 3A and 3B show a state in which a depletion layer generated around the body region of the transistor expands. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line BB ′ in FIG.

As shown, an n ^- type silicon layer 110 is formed.
A depletion layer 260 is formed in offset region 130 by a pn junction with body region 150. Since the impurity concentration of body region 150 is set higher than n ⁻ -type silicon layer 110 and offset region 130, most of depletion layer 260 forms the other region that forms a pn junction with body region 150, that is, n ^- -type silicon layer 110
And in the offset region 130. As aforementioned,
The body region 150 is provided in the n ⁻ type silicon layer 110 in a stripe shape. Therefore, depletion layer 260 is formed so as to extend outward from the body region as a center.

Here, at a certain applied voltage, the width of the depletion layer formed at the pn junction with body region 150 is set to d.
Assume 1. The depletion layer 260 generated in the portion where the body region is formed in a straight line can extend in the horizontal direction by the width of d1. However, the depletion layer cannot be sufficiently expanded at the corner of the body region 150, and the width of the depletion layer is d.
It becomes d2 smaller than 1.

As described above, depletion layer 260 is formed in body region 1.
The width of the depletion layer is reduced at the corners of body region 150 because it is formed so as to extend outside of 50. As a result,
The corner of the body region 150 becomes the electric field concentration point, and the LDM
This may cause a decrease in withstand voltage of the OS transistor.

[0011]

As described above, the conventional L
In a DMOS transistor, a depletion layer is formed around a body region surrounding a source region. Usually LDMOS
In the transistor, the depletion layer is formed so as to extend outward from the body region. At the corners of the body region, the depletion layer does not easily spread, and the width of the depletion layer is reduced. For this reason, there is a problem that electric field concentration is likely to occur at the corners of the body region, which causes a reduction in the breakdown voltage of the LDMOS transistor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to suppress a generation of an electric field concentration portion by effectively increasing a width of a depletion layer, thereby realizing a high withstand voltage. Is to provide.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention comprises: a first conductivity type offset region provided in a surface region of a first conductivity type semiconductor region; A second conductivity type body region provided in the surface region of the semiconductor region so as to surround the offset region; a first conductivity type drain region provided in a stripe shape in the surface region of the offset region; A gate insulating film is interposed between the first conductivity type source region provided in the surface region of the body region so as to surround the offset region and at least the body region between the drain region and the source region. And a gate electrode that is provided.

Further, the corner of the outer periphery in the planar shape of the body region is an arc having a predetermined radius.

Further, the semiconductor region is an epitaxial growth layer provided on a semiconductor substrate of the second conductivity type. The semiconductor device may further include a first conductivity type buried layer provided in a junction region between the semiconductor substrate and the semiconductor region, and an extraction electrode provided in the semiconductor region and connected to the buried layer. .

According to the above configuration, for example, the MOS
In the transistor, a depletion layer is formed in the semiconductor region and the offset region by a pn junction with the body region. The body region is provided so as to surround the offset region. Therefore, the depletion layer extending from the body region toward the offset region extends from the offset region as a center toward the region surrounded by the body region. Therefore, a depletion layer extending from two directions is synthesized at the corner of the body region, and the width of the depletion layer is increased. Thus, by expanding the depletion layer in the region surrounded by the body region,
The extension width of the depletion layer generated at the corner of the junction with the body region is set to be larger than that at the portion other than the corner. As a result, the corner portion, which is the place where the electric field concentration occurs in the conventional structure, can be made the portion where the electric field is most unlikely to concentrate, so that the withstand voltage of the MOS transistor can be improved.

Further, the outer peripheral corner in the planar shape of the body region is formed in an arc shape. The radius of this arc shape can be designed to a predetermined value, and by increasing the value of this radius, the width of the depletion layer formed at the corner can be increased. Can be avoided, and the breakdown voltage of the MOS transistor can be improved.

Further, a buried layer is provided at an interface between the epitaxial growth layer and the semiconductor substrate as an epitaxial growth layer in which a semiconductor region is formed on a semiconductor substrate, and a predetermined potential is applied to the buried layer, whereby the MOS transistor is turned on. It can correspond to both the side switch and the low side switch.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

The semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) and (b). FIG. 1A shows an LDM.
A plan view of the OS transistor, and FIG. 2B is a cross-sectional view taken along a line CC ′ in FIG.

As shown, a p ⁺ type silicon substrate 10
An n ⁻ type epitaxial silicon layer 11 is provided thereon,
An n ⁺ type buried layer 12 is provided at the junction between the two. An n ⁻ -type impurity diffusion layer 13 serving as an offset region is provided in the surface region of the n ⁻ -type silicon layer 11 so as to have a stripe shape, and an n ⁺ -type impurity diffusion serving as a drain region is provided in the offset region 13. The layer 14 is provided in a stripe shape. Further, n ^- type silicon layer 11
In the surface region, a p-type impurity diffusion layer 15 serving as a body region is provided so as to surround the offset region 13. In the body region 15, a source region and a p-type impurity region are similarly surrounded so as to surround the offset region 13. N ⁺ -type impurity diffusion layer 16 is provided. This body area 1
The outer periphery of 5 has an arc shape with a corner at a predetermined radius. In the body region 15, ap ⁺ -type impurity diffusion layer 17 serving as a contact region with an electrode is provided.
^{In the −} type silicon layer 11, an n ⁺ type impurity diffusion layer 18 serving as an extraction electrode that contacts the n ⁺ type buried layer 12
Is provided. Further, a gate electrode 21 is provided from the source region 16 to the drain region 14 so as to surround the drain region 14 with a gate insulating film 19 and a thick insulating film 20 interposed therebetween. An LDMOS transistor is configured by providing a drain electrode 22 on the drain region 14 and a source electrode 23 on the source region 16 and the contact region 17.

The above-mentioned LDMOS transistor is designed to have a large channel width by forming the source / drain regions 16 and 14 in a stripe shape, thereby coping with a large current operation. The n ⁺ -type buried layer 12 is used to form the p ⁺ -type silicon substrate 10 and the p-type body region 1 when the LDMOS transistor is used as a high-side switch.
5 is provided to electrically separate the same from the drain 5 and is set to, for example, the same potential as the drain.

Next, a method of manufacturing the above-described LDMOS transistor will be described with reference to FIGS. 2 to 12 are cross-sectional views sequentially showing first to eleventh manufacturing steps of an LDMOS transistor, respectively.

First, as shown in FIG. 2, a mask material 24-1 is formed on a p ⁺ type silicon substrate 10 and patterned by a lithography technique so as to have an opening in a region where an n ⁺ type buried layer 12 is to be formed. I do. Then, using this mask material 24-1 as a mask, for example, As (Arseni
An n-type impurity such as c) is introduced into the surface of the p ⁺ -type silicon substrate 10 by ion implantation or the like.

Next, after the mask material 24-1 is removed,
As shown in FIG. 3, the n ⁻ type silicon layer 11 is
The entire surface is epitaxially grown by an emical vapor deposition method or the like. During the epitaxial growth of the n ⁻ -type silicon layer 11, the impurities contained in the n ⁻ -type buried layer 12 diffuse into the n ⁻ -type silicon layer 11 and the p ⁺ -type silicon substrate 10 to have a shape as illustrated. Become.

Subsequently, a mask material 24-2 is formed on the entire surface, and as shown in FIG. 4, the mask material 24-2 is patterned so as to have an opening in a region where the n ⁺ -type extraction electrode 18 is to be formed. Then, using this mask material 24-2 as a mask, n-type impurities such as P (Phosphorus) are introduced into the n ⁻ -type silicon layer 11 by ion implantation or the like.

Next, after removing the mask material 24-2,
The mask material 24-3 is formed again on the entire surface. And FIG.
As shown in (1), the mask material 24-3 is patterned so as to have an opening in a region where the p-type body region 15 is to be formed. Here, as shown in FIG. 1A, in the planar pattern on the n ⁻ type silicon layer 11, the p type body region 15
It is necessary to pattern the mask material 24-3 so that the outermost periphery of the mask material does not have a corner. Then, using this mask material 24-3 as a mask, B (Boro
n) and the like are introduced into the surface region of the n ⁻ type silicon layer 11 by an ion implantation method or the like.

Next, after removing the mask material 24-3, a mask material 24-4 is formed again on the entire surface. And
As shown in FIG. 6, the mask material 24-4 is patterned so as to have an opening in a region where the n ⁻ type offset region 13 is to be formed, which is surrounded by the region where the p type body region 15 is to be formed. Thereafter, using the mask material 24-4 as a mask, P, which is an n-type impurity, is introduced into the n ⁻ -type silicon layer 11 by an ion implantation method or the like.

[0029] Then, after removing the mask material 24-4, by heat treatment, carried out the diffusion of impurities implanted in the step described above with reference to FIG. 4 to FIG. 6, n ⁺ -type 7 Extraction electrode 18, p-type body region 1
5 and an n ⁻ type offset region 13 are formed.

Next, as shown in FIG. 8, n ^- LOCOS on a part of the type offset region 13 (LOCal Oxidation of
A thick oxide film 20 is formed by a Silicon) method. This thick oxide film 20 is provided at the edge of the striped n ⁻ type offset region 13 and surrounds the center of the n ⁻ type offset region 13. Subsequently, for example, a silicon oxide film 19 or the like serving as a gate insulating film is formed on the entire surface.

Next, a polycrystalline silicon film is formed on the entire surface of the thick oxide film 20 and the gate oxide film 19 by, for example, a CVD method or the like. Then, as shown in FIG. 9, a gate electrode is formed by patterning a polycrystalline silicon film so as to be present over part of the thick oxide film 20 and the gate oxide film 19 and to surround the n ⁻ type offset region 13. 21
To form

Next, a mask material 24-5 is formed on the entire surface,
As shown in FIG. 10, patterning is performed so as to have openings in regions where the source and drain regions 16 and 14 are to be formed.
The pattern has a stripe shape for the drain region and a shape surrounding the drain region for the source region. And this mask material 24-
Using the gate electrode 5 and the gate electrode 21 as a mask, an n-type impurity such as As is introduced into the p-type body region 15 and the n ⁻ -type offset region 13 by an ion implantation method or the like.

Then, after removing the mask material 24-5,
A mask material 24-6 is formed again on the entire surface, and the mask material 24-6 is patterned so as to have an opening in a region where the p ⁺ -type contact region 17 is to be formed, as shown in FIG. Then, using this mask material 24-6 as a mask, p
B, which is a type impurity, is introduced into the p-type body region 15 by an ion implantation method or the like.

After the mask material 24-6 is removed, a heat treatment is performed to diffuse and activate the impurities introduced in the steps described with reference to FIGS.
As shown in FIG. 3, the source and drain regions 16, 14 and p ⁺
A mold contact region 17 is formed.

Thereafter, a source electrode 23 is formed on the source region 16 and the p ⁺ -type contact region 17 and the drain region 1 is formed.
The LDMOS transistor as shown in FIG.

FIG. 1 manufactured by the above method.
The state of the depletion layer formed around the body region in the LDMOS transistor having the structure shown in FIGS. 13A and 13B will be described with reference to FIGS. FIG.
1A and 1B are enlarged views of a region 25 in FIG. 1B, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line DD ′ in FIG. It is.

[0037] As illustrated, n ^- p between the -type silicon layer 11 and the body region 15 in the offset region 13
A depletion layer 26 is formed by the n-junction. Here, a depletion layer is formed by a pn junction with p-type body region 15.
^{The −} type offset region 13 is surrounded by the p type body region 15. That is, the depletion layer extending from the body region 15 toward the offset region 13 extends toward the region surrounded by the body region 15. As a result, at a certain applied voltage, the body region 1
If the depletion layer width extending from 5 is d1, a depletion layer that expands with a width of d1 from two directions is synthesized at the corners of the body region 15 and the depletion layer width is d2 larger than d1. Becomes

Further, as shown in FIG. 1A, the outer peripheral corner in the planar shape of the p-type body region 15 is formed in an arc shape. The radius of this arc shape can be designed to an arbitrary value, and the larger the radius, the larger the width of the depletion layer formed in this region. Therefore, electric field concentration in this region can also be avoided.

As described above, by expanding the depletion layer in the region surrounded by body region 15, body region 15
The width of the depletion layer generated at the corners can be made larger than that at other corners. That is, in the conventional structure, the corner portion, which is the location where the electric field concentration occurs, is the portion where the electric field is most difficult to concentrate. Also, the depletion layer extending outward from body region 15 is
By eliminating the corners in the planar shape of No. 5, an electric field concentration location is prevented from occurring. As a result, specifically, the distance between the source and the drain was 6.5 μm, and the offset length was 3.3 μm.
m, the impurity dose of the offset region is 2.0 × 10
^In the LDMOS transistor set to ¹² cm ⁻² , the breakdown voltage was 22 V in the conventional structure, whereas in the LDMOS transistor having the structure described in the present embodiment, the breakdown voltage was 77 V, and the breakdown voltage was significantly improved. .

In the LDMOS transistor according to the present embodiment, the depletion layer generated by the pn junction with the body region is formed so as to extend into the region surrounded by the body region 15 so that the corner of the body region is formed. Depletion layer width is increased. Therefore, the electric field concentration in this region can be suppressed, and the breakdown voltage of the LDMOS transistor can be improved. In this embodiment, an LDMOS transistor has been described as an example. However, the gist of the present invention is to configure one of the pn junctions and surround the region where the depletion layer is mainly formed with the other region of the pn junction. As a result, the depletion layer is efficiently expanded to prevent the occurrence of electric field concentration. Therefore, the present invention can be applied to all the semiconductor elements to which this purpose can be applied with appropriate modifications.

Next, a second embodiment of the present invention will be described with reference to FIG. In the present embodiment, the LDMOS transistor described in the first embodiment is applied to a motor driver, and FIG. 14 is a circuit diagram of the motor driver.

As shown in the figure, the motor driver has a drain connected to a power supply Vcc and a gate to which a signal S1 is input, and a MOS transistor Tr.
MOS transistor having a drain connected to the source, a source connected to GND, and a signal S2 input to the gate
A MOS transistor Tr.3 whose drain is connected to the power supply Vcc and a signal S3 is input to the gate;
The drain of the S transistor Tr.3 is connected to the drain, the source is connected to GND, and the signal S4 is input to the gate of the MOS transistor Tr.4, and the MOS transistor Tr.1,
This is an etch bridge circuit including a motor M provided between a connection node of Tr.2 and a connection node of MOS transistors Tr.3 and Tr.4. The MOS transistors Tr.1 to Tr.4 included in this etch bridge circuit are LDMOS transistors having the structure described in the first embodiment.

In the motor driver having the above configuration, when the MOS transistors Tr.1 and Tr.4 are turned on by setting the input signals S1 and S4 to "High" level, current is supplied to the motor M. Then, the motor M is driven.

Here, the MOS transistors Tr.1 and Tr.3
Is used as a high-side switch because the source is connected to the load, while MOS transistors Tr.2 and Tr.4
Needs to be used as a low-side switch because the source is connected to GND.

However, by using the LDMOS transistor having the structure described in the first embodiment, the MOS transistors used as the high-side switch and the low-side switch can be used.
The transistors can have the same structure. Therefore, the manufacturing process of the motor driver can be simplified. Further, as described in the first embodiment, the structure capable of improving the withstand voltage can effectively prevent the motor from being damaged.

It should be noted that the present invention is not limited to the above-described embodiment, and that various modifications can be made in the implementation stage without departing from the scope of the invention. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

[0047]

As described above, according to the present invention, it is possible to provide a semiconductor device capable of suppressing occurrence of an electric field concentration portion and realizing a high breakdown voltage by effectively increasing the width of the depletion layer.

[Brief description of the drawings]

FIG. 1 is for describing a structure of an LDMOS transistor according to a first embodiment of the present invention;
(A) is a plan view, (b) is a diagram of FIG.
Sectional drawing along the C 'line.

FIG. 2 is a sectional view showing a first manufacturing step of the LDMOS transistor according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a second manufacturing step of the LDMOS transistor according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a third manufacturing step of the LDMOS transistor according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth manufacturing step of the LDMOS transistor according to the first embodiment of the present invention;

FIG. 6 is a sectional view showing a fifth manufacturing step of the LDMOS transistor according to the first embodiment of the present invention;

FIG. 7 is a sectional view showing a sixth manufacturing step of the LDMOS transistor according to the first embodiment of the present invention;

FIG. 8 is a sectional view showing a seventh manufacturing step of the LDMOS transistor according to the first embodiment of the present invention;

FIG. 9 is a sectional view showing an eighth manufacturing step of the LDMOS transistor according to the first embodiment of the present invention;

FIG. 10 is an LDMOS according to the first embodiment of the present invention.
FIG. 13 is a cross-sectional view illustrating a ninth manufacturing process of a transistor.

FIG. 11 is an LDMOS according to the first embodiment of the present invention.
FIG. 14 is a sectional view showing a tenth manufacturing step of the transistor.

FIG. 12 is an LDMOS according to the first embodiment of the present invention.
FIG. 21 is a sectional view of an eleventh manufacturing process of a transistor.

FIG. 13 shows an LDMOS according to the first embodiment of the present invention.
FIGS. 4A and 4B are diagrams illustrating a state of a depletion layer in a transistor, wherein FIG. 4A is a plan view and FIG.
Sectional drawing along the -D 'line.

FIG. 14 is a circuit diagram of a motor driver according to a second embodiment of the present invention.

15A and 15B are diagrams for explaining the structure of a conventional LDMOS transistor, in which FIG. 15A is a plan view and FIG. 15B is a cross-sectional view taken along line AA ′ in FIG.

16A and 16B are diagrams showing a state of a depletion layer in a conventional LDMOS transistor, and FIG. 16A is a plan view,
FIG. 2B is a cross-sectional view taken along line BB ′ in FIG.

[Explanation of symbols]

10,100 ... semiconductor substrate 11, 110 ... n ^- -type silicon layer 12,120 ... ^{n +} -type buried layer 13,130 ... offset region 14, 140 ... drain region 15, 150 ... the body region 16, 160 ... source region 17, 170 contact region 18, 180 extraction electrode 19, 190 gate insulating film 20, 200 thick insulating film 21, 210 gate electrode 22, 220 drain electrode 23, 230 source electrode 24-1-6 mask material 25, 250: region 26, 260: depletion layer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akio Nakagawa 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba R & D Center (reference) 5F040 DA20 DA22 DC01 EB01 EB02 EC07 EC18 EC22 EE01 EF01 EF11 EF18 EM01 FC02 FC05 5H571 BB07 CC01 FF05 HA09

Claims (4)

[Claims] A first conductive type offset region provided in a surface region of a first conductive type semiconductor region; and a second conductive type offset region provided in a surface region of the semiconductor region so as to surround the offset region. A conductive type body region; a first conductive type drain region provided in a stripe shape in a surface region of the offset region; and a second conductive region provided in the surface region of the body region so as to surround the offset region. A semiconductor device comprising: a one-conductivity-type source region; and a gate electrode provided at least on the body region between the drain region and the source region with a gate insulating film interposed therebetween. 2. The semiconductor device according to claim 1, wherein a corner of the outer periphery of the planar shape of the body region has an arc shape having a predetermined radius. 3. The semiconductor device according to claim 1, wherein said semiconductor region is an epitaxial growth layer provided on a semiconductor substrate of a second conductivity type. 4. A buried layer of a first conductivity type provided in a junction region between the semiconductor substrate and the semiconductor region, and an extraction electrode provided in the semiconductor region and connected to the buried layer. 4. The semiconductor device according to claim 3, wherein: