JPH1174505A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device by which difference in characteristics due to location can be prevented. SOLUTION: A transistor 21 is provided with a gate electrode 22 in the form of a square frame. Since each side of the gate electrode 22 is inclined by 45 deg. from the direction of crystal, the form of the gate electrode 22 in the direction of crystal does not change even if it is formed with a rotation by 90 deg.. Also, since the relative position of a drain area 24 and a source area 26 to the gate electrode 22 does not change with rotation, change in characteristics can be prevented even if it is formed with a rotation by 90 deg..

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
More specifically, the present invention relates to a layout of a field effect transistor (FET) such as a MOS type formed on a chip of a semiconductor device.

2. Description of the Related Art In recent semiconductor devices, higher integration and higher speed have been promoted, and the number of transistors formed on a chip of the semiconductor device has been increased, and restrictions on the arrangement have been increased. For this reason, there is a demand for a transistor having a layout in which a large number of transistors can be efficiently arranged and formed, and the layout is not easily restricted.

[0003]

2. Description of the Related Art Conventionally, a semiconductor device is provided with a plurality of output circuits for outputting a plurality of output signals output from an internal circuit to the outside of the device. The plurality of output circuits have the same output characteristics because they output signals having the same characteristics. In addition, the output circuit is required to have high driving capability. An output circuit with high driving capability is configured by arranging a plurality of circuit cells each including one output transistor or a plurality of transistors having a large gate width in parallel. An output circuit having the same output characteristics is composed of a plurality of output transistors and circuit cells formed symmetrically in the vertical and horizontal directions.

[0004]

Incidentally, the output circuit may need to be formed in a shape rotated by 90 degrees due to a reduction in the chip area and restrictions on the pin arrangement of the package in some cases. For example, in the semiconductor device 11 of FIG.
In the drawing, output circuits 12a arranged along upper and lower sides,
12b is formed in a vertically symmetric shape. The output circuits 12c and 12d arranged along the left and right sides are formed in a symmetrical shape. Further, output circuits 12c and 12d
Are formed in a shape obtained by rotating the output circuits 12a and 12b by 90 degrees.

[0005] However, the transistors constituting the output circuits 12a to 12d are formed in the same size so as to have the same characteristics, but a difference may occur. For example, the transistors 15 and 16 in FIGS.
They are formed in the same size on the same wafer. But,
The two transistors 15 and 16 have different characteristics. This difference in characteristics is due to the fact that the direction of impurity diffusion is caused by the difference in the crystal direction of the wafer. Since the directionality of diffusion affects the movement of carriers, characteristics are different depending on the direction in which the transistor is formed. Therefore, it has been troublesome to change the size of the transistor or change the layout of the output circuit. That is, the arrangement of the conventional transistor is restricted.

Therefore, as shown in FIG. 10C, a transistor 17 in which the gate electrodes G are formed in a lattice pattern is considered. In this transistor 17, since the drain region D is formed in the vertical direction and the horizontal direction of the source region S,
Even if the transistor is formed by being rotated by 90 degrees, characteristics equivalent to those of the original transistor can be obtained. However, in the transistor 17, since the gate G formed along the up-down direction and the gate G formed along the left-right direction must be common, it is not used for the purpose of controlling the potential of each gate G separately. Difficult,
Since the region where the transistor is formed is large, the arrangement efficiency is deteriorated. This increases the chip area and increases the cost of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing a difference in characteristics due to arrangement.

[0008]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor device at a position sandwiching a gate electrode, the first region being a source region or a drain region.
And a second region serving as a drain region or a source region, wherein the gate electrode is formed in a substantially square frame shape independent of other gate electrodes, and a region surrounded by the gate electrode Was defined as a first region, the second region was formed so as to sandwich each side of the gate electrode with respect to the first region, and a semiconductor layer below the gate electrode was defined as a channel.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a plurality of the square frame-shaped gate electrodes are connected in tandem such that corner portions of the gate electrodes overlap in one diagonal direction. did.

[0010] The invention described in claim 3 is the invention according to claim 1 or 2.
In the semiconductor device described in the above, each side of the gate electrode is formed so as to form an angle of 45 degrees with a crystal direction of a substrate forming the semiconductor device.

The invention according to claim 4 is the invention according to claim 2 or 3.
2. The transistor comprising the semiconductor device according to the
A plurality of regions were arranged in parallel with a space between them. According to a fifth aspect of the present invention, a plurality of transistors each including the semiconductor device according to the second or third aspect are arranged in parallel, and adjacent transistors share a second region between the transistors. The gate electrodes of the two transistors shared are arranged to be separated from each other.

The invention according to claim 6 is the invention according to claims 2 to 5
In the semiconductor device according to any one of the above, no channel is formed below a corner portion connecting the gate electrode.

According to the first aspect of the present invention, in a semiconductor device, a first region serving as a source region or a drain region and a drain region or a source are provided in a semiconductor layer at a position sandwiching a gate electrode. A second area serving as an area is provided. Further, since the gate electrode is formed in a substantially square frame shape independently of other gate wirings, even if the arrangement is rotated by 90 degrees, the shape of the gate electrode and the first region surrounded by the gate electrode Since the relative position of the second region sandwiching the gate electrode does not change, the difference in characteristics due to the arrangement is small.

According to the second aspect of the present invention, a plurality of square frame-shaped gate electrodes are connected in tandem such that corner portions of the gate electrodes overlap in one diagonal direction, and the difference in characteristics due to the arrangement is small. As a result, the effective gate width of the gate electrode increases.

According to the third aspect of the present invention, each side of the gate electrode is formed so as to form an angle of 45 degrees with the crystal direction of the substrate forming the semiconductor device. Since the angle of the gate electrode with respect to the direction does not change, there is little difference in characteristics based on the crystal direction.

According to the fourth aspect of the present invention, a plurality of transistors, each of which is made of a semiconductor device and has a small difference in characteristics depending on the arrangement, are arranged in parallel with the second region being separated. According to a fifth aspect of the present invention, a plurality of transistors each including the semiconductor device according to the second or third aspect are arranged in parallel. The second region between the adjacent transistors is shared, and the gate electrodes of the two transistors sharing the second region are arranged apart from each other, so that each gate electrode can be individually controlled.

According to the sixth aspect of the present invention, since no channel is formed below the corner connecting the gate electrode, the second region sandwiching the corner is separated.
The difference in characteristics due to the arrangement is further suppressed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic plan view showing a layout of the MOS transistor 21. The transistor 21 has a square frame-shaped gate electrode 22.
Is provided. The gate electrode 22 is formed such that each side is inclined by 45 degrees with respect to the crystal direction of the wafer (the direction of arrow 23 in FIG. 1).

The transistor 21 is formed on a semiconductor chip having a side along the crystal direction. In a general MOS transistor constituting a semiconductor device, the gate electrode 22 is formed along a crystal direction or a direction perpendicular to the crystal direction.

The semiconductor layer in a region surrounded by the gate electrode 22 becomes a drain region 24, and the drain region 24
Is formed. Therefore, the gate electrode 22 is connected to the drain contact 2
The contact 5 is formed around the contact 5.

A rectangular source region 26 is formed in the semiconductor layer at a position outside each side of the gate electrode 22, respectively.
Source contacts 27 connected to the respective source regions 26 are formed. Note that the region surrounded by the gate electrode 22 may be the source region 26, and the outside of each side of the gate electrode 22 may be the drain region 24.

The gate electrode 22 is connected to a gate wiring 28 formed along one diagonal of the square (vertical direction in the figure). A circuit that controls the transistor 21, for example, an internal circuit (not shown) controls the potential of the gate electrode 22 via the gate wiring 28. To the drain contact 25, a drain wiring 29 formed above the gate electrode 22 is connected. Each source contact 27 is connected by a source wiring 30 formed in a layer above the gate electrode 22.

The transistor 21 having the layout shown in FIG. 1 operates as a P-channel MOS transistor or an N-channel MOS transistor due to impurities diffused in the drain region 24 and the source region 26. For example, impurities such as antimony are diffused into the drain region 24 and the source region 26 in order to form an N-type diffusion region in a semiconductor device manufacturing process. In the semiconductor layer below the gate electrode 22, a channel is formed by the potential of the gate electrode 22. Thereby, the transistor 21 operates as an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor).

This transistor 21 is equivalent to four NMOS transistors TN1 to TN4 to which a gate G and a drain D are connected, as shown in FIG. Then, the source wiring 30 of FIG. 1 connects the sources S of the NMOS transistors TN1 to TN4. Therefore, the transistor 21 includes four NMOS transistors TN1 to TN1.
TN4 is connected in parallel.

The drain region 24 and the source region 2
6, in the manufacturing process of the semiconductor device, impurities such as boron are diffused to form a P-type diffusion region. This allows
The transistor 21 operates as a P-channel MOS transistor (hereinafter, referred to as a PMOS transistor). As shown in FIG. 2B, this transistor 21 has four PMOs each having a gate G and a drain D connected to each other.
This is equivalent to the S transistors TP1 to TP4. And
The source line 30 in FIG.
Sources S1 to TP4 are connected. Therefore, the transistor 21 includes four PMOS transistors TP1 to TP4
Are connected in parallel.

In the transistor 21 configured as described above, each side of the gate electrode 22 has a width of 4 with respect to the crystal direction.
Since it is tilted by 5 degrees, the shape of the gate electrode 22 with respect to the crystal direction does not change even if it is formed into a shape rotated by 90 degrees.
Further, the relative positions of the drain region 24 and the source region 26 with respect to the gate electrode 22 are the same as before rotation. Therefore, even if the transistor 21 is formed in a shape rotated by 90 degrees, the characteristics hardly change. That is,
The transistor 21 has a structure that is not easily restricted by arrangement.

The effective gate width of the transistor 21 is substantially equal to the sum of the lengths of the sides of the square frame-shaped gate electrode 22. When the conventional transistors 15 and 16 (see FIGS. 10A and 10B) are formed to have the same effective gate width, the junction area of the drain region is equal to the junction area of the drain region 24 in the transistor 21 of the present embodiment. Much larger than. In addition, there is a conventional transistor in which two gate electrodes are formed in parallel and a junction area is reduced by using a region sandwiched between the gate electrodes as a drain region. However, also in this conventional transistor, the junction area of the drain region is larger than the junction area of the drain region 24 in the transistor 21 of the present embodiment.

That is, the transistor 21 of the present embodiment comprises:
The junction area of the drain region 24 is smaller than that of a conventional transistor having a gate electrode formed with the same effective gate width. Reducing the junction area is effective in reducing the drain capacitance and reducing the load capacitance. A transistor with a small load capacity operates at high speed. Therefore, the transistor 21 of the present embodiment is more suitable for high-speed operation than a conventional transistor.

The transistor 21 configured as described above
Are used to configure the output transistor 31 of FIG. The output circuit 12b in FIG. 9 includes one or more output transistors 31. Note that the above transistor 21 is hereinafter referred to as a basic transistor 21.

FIG. 3 is a schematic layout diagram of the output transistor 31. The output transistor 31 includes a plurality of basic transistors 21. The plurality of basic transistors 21 are arranged along the diagonal direction of the gate electrode 22.
Arranged in columns. Adjacent basic transistors 21 are arranged such that corner portions 22a of gate electrode 22 overlap. Therefore, the gate electrodes 22 of the adjacent basic transistors 21 are connected by the overlapping of the corner portions 22a. That is, the gate electrodes 22 of all the basic transistors 21 arranged in one row along the diagonal direction are connected to each other at the arranged diagonal corners 22a.

The source region 26 between the two basic transistors 21 arranged adjacent to each other is
Shared to. The drain contacts 25 of the plurality of basic transistors 21 arranged in one column are connected to a drain wiring 29. An output signal of an internal circuit (not shown) is applied to the drain region 24 of each basic transistor 21 via the drain wiring 29 and each drain contact 25.

The transistor 31 constructed as described above is connected to the gate electrode 2 of the basic transistor 21 constituting the transistor 31.
Since each side of 2 is inclined 45 degrees with respect to the crystal direction, 9
Even if the gate electrode 22 is formed in a shape rotated by 0 degrees, the shape of the gate electrode 22 with respect to the crystal direction does not change. Further, the relative positions of the drain region 24 and the source region 26 with respect to the gate electrode 22 are the same as before rotation. Therefore, even if the output transistor 31 is formed in a shape rotated by 90 degrees, the characteristics hardly change. That is, the output transistor 31
Has a structure that is less susceptible to placement restrictions. Therefore, since the other output circuits 12c and 12d can be formed by rotating the layout of each output circuit 12b of FIG. 9 by 90 degrees, there is no need to change the layout. The output circuit 12a is formed by inverting the output circuit 12b in the vertical direction.

The effective gate width of the output transistor 31 increases because the square frame-shaped gate electrodes 22 are connected so that the corners 22a overlap each other along the diagonal direction. Moreover, since the junction area of the drain region 24 of each basic transistor 21 is small, the output transistor 31 is suitable for high-speed operation.

As another form, FIG. 4 is a partial layout diagram of the output circuit 12b of FIG. 9, and is a layout diagram in which the source region 26 of the adjacent output transistor 31 in FIG. 3 is shared.

At this time, the adjacent output transistor 31
Are arranged such that the gate electrodes 22 are separated from each other. The gate electrode 22 is formed based on a preset design rule so as to have a minimum interval satisfying the rule. Furthermore, adjacent output transistors 31 share a source region 26 therebetween. The source region 26 is formed as one continuous region by separating the gate electrode 22.

At this time, as shown in FIG. 4, the output transistors 31 are displaced along a diagonal line indicating the direction in which the basic transistors 21 are arranged. Specifically, since the gate electrode 22 of the basic transistor 21 is formed in a square shape, it has a first diagonal line indicating the direction in which the basic transistors 21 are arranged, and a second diagonal line orthogonal to the first diagonal line. Each output transistor 31 is arranged along the second diagonal direction.

In FIG. 4, the first to fifth output transistors 31a to 31e are arranged in order from the right end to the left end.
The second output transistor 31b is arranged to be shifted downward in the drawing along the first diagonal line with respect to the first output transistor 31a. The third output transistor 31c is connected to the second output transistor 31c.
The output transistor 31b is arranged to be shifted upward in the drawing along the first diagonal line with respect to the output transistor 31b. The third output transistor 31c is arranged at the same position as the first output transistor 31a in the first diagonal direction.

Similarly, the fourth output transistor 31d is
The third output transistor 31c is arranged so as to be shifted downward in the drawing and at the same position as the second output transistor 31b in the first diagonal direction. Further, the fifth output transistor 31e is arranged to be shifted upward with respect to the fourth output transistor 31d,
The first and third output transistors 31a and 31c are arranged at the same position in the first diagonal direction.

That is, each of the output transistors 31a to 31e
Are alternately displaced along the first diagonal direction. By arranging the output transistors 31a to 31e in such a manner, the intervals between the transistors 31a to 31e become narrower than in the case where the output transistors 31a to 31e are arranged without being shifted. This is effective in reducing the area occupied by the plurality of output transistors 31.

The shape of the gate electrode 22 does not change even if the output transistors 31a to 31e arranged as shown in FIG. The positional relationship between the source region and the drain region with the gate electrode 22 interposed therebetween is not different from that before rotation. Therefore, the characteristics of the output transistors 31a to 31e before rotation are almost the same as the characteristics after rotation, so that a difference in characteristics can be suppressed.

The output transistors 31a to 31
In e, the source region and the drain region may be exchanged. That is, the operation is performed by exchanging signals supplied to the wirings 29 and 30. Even in this case, the area of the source region 26 in FIG. 4 is small because the gate electrodes 22 of the adjacent output transistors are formed close to each other. Therefore, even if the source region and the drain region are exchanged, the junction area of the drain region does not increase, so that an output transistor that can operate at high speed can be configured.

In the first to fifth output transistors 31a to 31e thus configured, the gate electrode 28 and the drain wiring 29 are not connected. Therefore, an internal circuit (not shown) controls each of the output transistors 31a to 31e individually. Such output transistors 31a to 31
e is used, for example, in the D / A converter of FIG.

This D / A converter has a plurality of voltage dividing resistors 41 whose voltage dividing ratio is set in advance. Each voltage dividing resistor 41 is connected to one external terminal 43 via a transfer gate 42 composed of a pair of a PMOS transistor and an NMOS transistor. The transistors forming the transfer gate 42 are 2n output transistors 31 (n is the number of voltage dividing resistors 41, and each is n P and NMOS transistors) arranged as shown in FIG. That is, the drain of each output transistor 31 is connected to the voltage dividing resistor 41, and all the sources are connected to the external terminal 4.
3 is connected. The internal circuit controls the gate potential of each output transistor 31 to turn on and off the transfer gate 42 including the output transistor 31. Then, the divided voltage of the voltage dividing resistor 41 appears at the external terminal 43 via the transfer gate 42 which is turned on.

As described above, the output transistors 31 formed in the layout shown in FIG. 4 can individually control the potential of the gate electrode 22. Although the output transistors 31a to 31e in FIG. 4 are alternately shifted upward or downward along the first diagonal direction, as shown in FIG. In the same direction along the first diagonal direction.

By the way, in the output transistor 31 shown in FIGS. 3, 4 and 6, as shown in FIG.
No channel is formed in the corner portion 22a to which 2 is connected. For example, as shown in FIG. 8, the thickness of the oxide film 51 formed below the gate electrode 22 is increased only in the portion 52 of the corner portion 22a. As a result, no channel is formed below the corner portion 22a. This is effective in reducing a change in characteristics in the direction in which the output transistor 31 is formed.

That is, when a channel is formed in the corner portion 22a, conduction is made through the channel in which the source regions (left and right source regions in the drawing) 26 sandwiching the corner portion 22a are formed. When the output transistor 31 is rotated by 90 degrees, the direction in which the source region conducts is rotated by 90 degrees with the rotation. That is, in the output transistor 31 rotated by 90 degrees, the source region 26 conducts in a direction orthogonal to the conduction direction before the rotation. The conduction of the source region 26 causes a difference in the characteristics of the output transistor 31. Therefore, preventing the channel from being formed in the corner portion 22a is effective in suppressing the difference in the characteristics of the output transistors since the conduction of the source region 26 is eliminated. That is, by not forming a channel below the corner portion 22a, restrictions on the arrangement of the output transistor 31 can be further reduced.

As described above, the present embodiment has the following advantages. The transistor 21 and the output transistor 31 formed using the transistor 21 as a layout unit are:
A gate electrode 22 having a square frame shape is provided. Gate electrode 22
Are inclined 45 degrees with respect to the crystal direction.
The shape of the gate electrode 22 with respect to the crystal direction does not change even if it is formed in a shape rotated by degrees. Further, the relative positions of the drain region 24 and the source region 26 with respect to the gate electrode 22 are the same as before rotation. As a result, even if the transistor 21 is formed in a shape rotated by 90 degrees, the difference in characteristics can be suppressed, and the transistor 21 can be less likely to be restricted by the arrangement.

In the transistor 21 and the output transistor 31, the square frame-shaped gate electrode 22 is formed so as to surround the drain contact 25, so that the junction area of the drain region 24 is reduced. As a result, the transistor 21 and the output transistor 31 suitable for high-speed operation
Can be configured.

The corner portion 22 for connecting the gate electrode 22
The thickness of the portion 52 below the portion a is increased so that no channel is formed below the corner portion 22a. As a result, the source region 26 sandwiching the corner portion 22a is separated and no conduction occurs, so that a difference in characteristics due to conduction of the source region 26 can be suppressed.

[0050]

As described in detail above, according to the present invention,
A semiconductor device capable of suppressing a difference in characteristics due to arrangement can be provided.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a MOS transistor according to an embodiment.

FIGS. 2A and 2B are equivalent circuit diagrams of a MOS transistor according to an embodiment.

FIG. 3 is a layout diagram in which transistors of one embodiment are connected in cascade;

FIG. 4 is a layout diagram in which transistors of one embodiment are arranged vertically and horizontally.

FIG. 5 is a partial circuit diagram of a D / A converter using the transistor of FIG.

FIG. 6 is a layout diagram showing another arrangement of FIG. 4;

FIG. 7 is a partially enlarged layout diagram of another transistor.

FIG. 8 is a sectional view taken along line AA of FIG. 7;

FIG. 9 is a schematic layout diagram of a semiconductor device.

10A to 10C are layout diagrams of a conventional MOS transistor.

[Explanation of symbols]

 22 gate electrode 24 drain region as first or second region 26 source region as second or first region

Claims (6)

[Claims] 1. A semiconductor layer at a position sandwiching a gate electrode,
In a semiconductor device including a first region serving as a source region or a drain region and a second region serving as a drain region or a source region, the gate electrode is formed in a substantially square frame shape independent of other gate electrodes. A region surrounded by the gate electrode is defined as a first region, and the second region is formed so as to sandwich each side of the gate electrode with respect to the first region. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a plurality of the square frame-shaped gate electrodes are connected in tandem so that corner portions of the gate electrodes overlap in one diagonal direction. 3. The semiconductor device according to claim 1, wherein each side of the gate electrode forms an angle of 45 degrees with a crystal direction of a substrate forming the semiconductor device. 4. A semiconductor device in which a plurality of transistors each comprising the semiconductor device according to claim 2 or 3 are arranged in parallel with the second region being separated. 5. A semiconductor device according to claim 2, wherein a plurality of transistors are arranged in parallel, and adjacent transistors share a second region between the transistors.
A semiconductor device in which gate electrodes of two transistors sharing a region are arranged apart from each other. 6. The semiconductor device according to claim 2, wherein a channel is not formed below a corner portion connecting the gate electrode.