CN101650967A - Buffer structure of hardware silicon intellectual property - Google Patents
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Abstract
The invention relates to a buffer structure of hardware silicon intellectual property. A first internal memory and a second internal memory are respectively provided with a memory space with 2N m sites, wherein the first internal memory and the second internal memory are respectively a first region and a second region, the first region consists of a memory space with 0-(N-1)th m sites, and the second region consists of a memory space with Nth-(2N-1)th m sites. A write circuit is used for writing an even number address datum of source data into the second region of the second internal memory, an odd number address datum of the source data into the second region of the first internal memory, an even number address datum of target data into the first region of the first internal memory, and an odd number address datum of the target data into the first region of the second internal memory.
Description
Technical field
The invention relates to the technical field of integrating system-on-a-chip, refer to a kind of buffer structure of hardware silicon intellectual property especially.
Background technology
When carrying out integrated circuit (IC) design or hardware silicon intellectual property (Silicon Intellectual Property, be called for short SIP) design, regular meeting is built-in impact damper (Buffer) in circuit, uses for the hardware silicon intellectual property real-time operation or when reading and writing data operation.And according to the difference of various application, the framework that the impact damper in the hardware silicon intellectual property is formed also can some difference.Good buffer architecture can allow hardware silicon intellectual property the use high resilience and use simply, and therefore also writing of software can not cause restriction, advanced buffer architecture even can allow hardware area more dwindle is to save cost.
In the hardware silicon intellectual property design, similar computings such as " Source+Destination → Destination " is common in hardware silicon intellectual property utilization buffer approach.Wherein, " Source+Destination → Destination " is that expression is by reading a source data in the internal memory and reading a target data by identical internal memory or other internal memories, after this source data and this target data execution additive operation, and then the result is written back in the internal memory of original this target data of storage, and cover this target data with the additive operation result.This kind computing is non-only to be defined in additive operation, and other are as subtraction, shift operation or (OR) computing, and (AND) computing, mutual exclusion or (XOR) wait computing also often to be used in during hardware silicon intellectual property designs.
When design " Source+Destination → Destination " computing related hardware, known technology is respectively to deposit source data and target data with two impact dampers that separate, and pending data is restored after computing in the impact damper of target data.Fig. 1 is that impact damper uses synoptic diagram in the known technology.As shown in the figure, impact damper 110 is made up of the static random access memory (SRAM) of two 64x32 positions.When this impact damper 110 was applied in the color processing, it was that Alpha (A), Red (R), Green (G), Blue (B) are respectively with 8 positions representatives that the internal arithmetic of the hardware silicon intellectual property that color is handled and the data of storage are to use color format.Just each pixel is represented with one group ARGB, and the platform color representation mode of practical application also is so, so the framework of this impact damper 110 can just cooperate the platform use of ARGB8888 when access.
If use this ARGB8888 cell format on different platforms, then the framework of static random access memory just must be done change, to meet the demand in the use.
Another kind of known platform color representation mode is the RGB565 form.In Installed System Memory, each pixel 16 bit representations, and each word group (word) is 32 and is the access unit an of the best.That is, each word group can store the data of 2 pixels.Each sequential cycle (ClockCycle) is read a word group when system, but the value that must write two pixels is when entering the impact damper of hardware silicon intellectual property, and the framework of the impact damper of hardware silicon intellectual property just need be adjusted to the framework of Fig. 2 among Fig. 1.As shown in Figure 2, each is splitted into two different static random access memories source impact damper and target buffer, to reach the purpose of two pixels of access simultaneously.When system reads a word group, this hardware silicon intellectual property is through simple circuit conversion, take into the value that reads apart two pixel values, and allow the pixel of odd number and even number deposit in respectively in the different static random access memories, be used for reaching the function of two pixels of access simultaneously.
Though the buffer architecture of Fig. 2 has solved the problem of two pixels of access simultaneously, the internal memory on the entity must be divided into four, causes the waste on the storage area, and has increased some extra control circuits, increases many hardware costs.Hence one can see that, and the buffer structure of known hardware silicon intellectual property still has the space of improvement.
Summary of the invention
The object of the present invention is to provide a kind of buffer structure of hardware silicon intellectual property, to avoid the problem of storage area that known technology is produced waste.
Another object of the present invention is to provide a kind of buffer structure of hardware silicon intellectual property, to reduce whole hardware cost.
According to a characteristic of the present invention, the present invention proposes a kind of buffer structure of hardware silicon intellectual property, and it comprises one first internal memory, one second internal memory and a write circuit.This first internal memory has the memory space of a 2N m position, this first internal memory is divided into a first area and a second area, this first area is made up of by the memory space of individual m position, the 0th m position to the (N-1) the position, this second area is made up of by the memory space of individual m position, N m position to the (2N-1) the position, in the middle of, N, m are positive integer.This second internal memory has the memory space of a 2N m position, this second internal memory is divided into a first area and a second area, this first area is made up of by the memory space of individual m position, the 0th m position to the (N-1) the position, and this second area is made up of by the memory space of individual m position, N m position to the (2N-1) the position.This write circuit is connected to this first internal memory and this second internal memory, so that this first internal memory and this second internal memory are carried out write activity.Wherein, this write circuit is written to the even address data of a source data second area of this second internal memory, this write circuit is written to the odd address data of this source data the second area of this first internal memory, this write circuit is written to the first area of this first internal memory with the even address data of a target data, and this write circuit is written to the odd address data of this target data the first area of this second internal memory.
Description of drawings
Fig. 1 is that impact damper uses synoptic diagram in the known technology;
Fig. 2 is the configuration diagram of the impact damper of known hardware silicon intellectual property;
Fig. 3 is the block scheme of the buffer structure of hardware silicon intellectual property of the present invention;
Fig. 4 is the synoptic diagram of this write circuit of the present invention with the data write memory;
Fig. 5 is the synoptic diagram of the system perspective of internal memory of the present invention;
Fig. 6 is the circuit diagram of write circuit of the present invention;
To be the present invention write the write sequential chart of the odd address data of the even address data of a pixel of target data and a pixel to internal memory a sequential to Fig. 7 (1a) simultaneously in the cycle;
The storage sequential chart of internal memory in program process when Fig. 7 (1b) is Fig. 7 (1a);
To be the present invention write the write sequential chart of the odd address data of the even address data of a pixel of source data and a pixel to internal memory a sequential to Fig. 7 (1c) simultaneously in the cycle;
The storage sequential chart of internal memory in program process when Fig. 7 (1d) is Fig. 7 (1c);
Fig. 7 (2a) be the present invention a sequential read simultaneously in the cycle even address data of target data and source data the even address data read sequential chart;
When Fig. 7 (2b) is Fig. 7 (2a) in the program process internal memory read sequential chart;
Fig. 8 is the comparison diagram of known technology and usable floor area of the present invention.
Embodiment
Fig. 3 is the block scheme of the buffer structure of hardware silicon intellectual property of the present invention, and it has one first internal memory 310, one second internal memory 320 and a write circuit 330.
This first internal memory 310 has the memory space of a 2N m position, this first internal memory is divided into a first area and a second area, this first area is made up of by the memory space of individual m position, the 0th m position to the (N-1) the position, this second area is made up of by the memory space of individual m position, N m position to the (2N-1) the position, in the middle of, N, m are positive integer.
This second internal memory 320 has the memory space of a 2N m position, this second internal memory is divided into a first area and a second area, this first area is made up of by the memory space of individual m position, the 0th m position to the (N-1) the position, and this second area is made up of by the memory space of individual m position, N m position to the (2N-1) the position.
It is connected to this first internal memory 310 and this second internal memory 320 this write circuit 330, so that this first internal memory 310 and this second internal memory 320 are carried out write activities.
Fig. 4 is the synoptic diagram of this write circuit 330 of the present invention with the data write memory.This write circuit 330 with the even address data of a source data (SA0 ..., SA62) be written to the second area of this second internal memory 320.This write circuit 330 with the odd address data of this source data (SA1 ..., SA63) be written to the second area of this first internal memory 310.This write circuit 330 with the even address data of a target data (DA0 ..., DA62) be written to the first area of this first internal memory 310.This write circuit 330 with the odd address data of this target data (DA1 ..., DA63) be written to the first area of this second internal memory 320.
As shown in Figure 4, this target data is to be positioned over the first area of this first internal memory 310 and the first area of this second internal memory 320 respectively.Putting of this source data then is that even address data (even pixel) are placed in the second area of this second internal memory 320 with the second area of odd address data (odd pixel) pendulum at this first internal memory 310.This kind disposing way pixel that will belong to same computing by chance is placed in different internal memory the inside, allows the hardware silicon intellectual property also can the computing once of each period treatment and the access of impact damper when carrying out computing, and reaches best processing speed.DA0 pixel data (target data) among Fig. 4 places the first area of this first internal memory 310, and SA0 pixel data (source data) places the second area of this second internal memory 320, does computing so can take out simultaneously.DA1 pixel data (target data) and SA1 (source data) pixel data also are to be positioned in the different internal memories.
Fig. 5 is the synoptic diagram of the system perspective of internal memory of the present invention.That is, by the framework of this first internal memory 310 of data storing viewpoint and this second internal memory 320.As shown in Figure 5, this target data is to be stored in the first area of first internal memory 310 and the first area of this second internal memory 320.And this source data is to be stored in the second area of first internal memory 310 and the second area of this second internal memory 320.By the system perspective viewpoint, the storage of this target data and source data is very simple, it mainly is these write circuit 330 meeting executive address handoff functionalities of the present invention, can allow a software that the impact damper of hardware silicon intellectual property is treated as and have only two internal memories that separate, and this software need not special processing.The target buffer that solid box 510 representative systems are seen among Fig. 5, frame of broken lines 520 is represented the source impact damper.
Fig. 6 is the circuit diagram of write circuit of the present invention.This write circuit 330 comprise first with a Men Zhidi four and door 610～640 and first multiplexer to the four multiplexers 650～680.This first multiplexer 650 is connected to an address bus of this first internal memory 310, this second multiplexer 660 is connected to a data bus of this first internal memory 310, this first write signal pin that is connected to this first internal memory 310 with door 610, this second is connected to an enable signal pin of this first internal memory 310 with door 620.The 3rd multiplexer 670 is connected to the address bus of this second internal memory 320, the 4th multiplexer 680 is connected to the data bus of this second internal memory 320, the 3rd a write signal pin that is connected to this second internal memory 320 with door 630, the 4th is connected to an enable signal pin of this second internal memory 320 with door 640.
This first multiplexer 650 receives an odd address BufB_Addr_Odd of this source data and an even address BufA_Addr_Even of this target data, producing the Input Address signal of this first internal memory 310, and export this address bus (unified) SRAM_0_Addr of this first internal memory to 320 address bus.This second multiplexer 660 receives an odd address data BufB_Din_Odd of this source data and an even address data BufA_Din_Even of this target data, producing the input data signal of this first internal memory, and export this data bus SRAM_0_Din of this first internal memory to.
The 3rd multiplexer receives 670 and receives an even address BufB_Addr_Even of this source data and an odd address BufA_Addr_Odd of this target data, producing the Input Address signal of this second internal memory, and export this address bus SRAM_1_Addr of this second internal memory to.The 4th multiplexer 680 receives an even address data BufB_Din_Even of this source data and an odd address data BufA_Din_Odd of this target data, to produce this data bus SRAM_1_Din of this second internal memory.
This first receives a write signal BufA_WEn_Even of the even address of the write signal BufB_WEn_Odd of odd address of these source datas and this target data with door 610, producing a write signal of this first internal memory, and export this write signal pin SRAM_0_WEn of this first internal memory to.This second receives an enable signal BufA_CEn_Even of the even address of the enable signal BufB_CEn_Odd of odd address of these source datas and this target data with door 620, producing an enable signal of this first internal memory, and export this enable signal pin SRAM_0_CEn of this first internal memory to.
The 3rd receives a write signal BufA_WEn_Odd of the odd address of the write signal BufB_WEn_Even of even address of these source datas and this target data with door 630, producing a write signal of this second internal memory, and export this write signal pin SRAM_1_WEn of this second internal memory to.The 4th receives an enable signal BufA_CEn_Odd of the odd address of the enable signal BufB_CEn_Even of even address of these source datas and this target data with door 640, producing an enable signal of this second internal memory, and export this enable signal pin SRAM_1_CEn of this first internal memory to.
By this write circuit 330 of the present invention, with the executive address handoff functionality, so the storage of this target data and source data can become very simple, has only two internal memories that separate and can allow this software that the impact damper of hardware silicon intellectual property is treated as.For this software, the technology of the present invention is penetrating (transparent), promptly this software need not any modification access first internal memory 310 and second internal memory 320 apace.
As mentioned above, when part SRAM first internal memory 310 as described in Figure 6, second internal memory 320 and write circuit 330 are integrated, wherein, described first internal memory 310 and second internal memory 320 are divided into a first area and a second area, the area dividing mode is as indicated above, first area in 310 is in order to the even address data BufA_EVEN of storage target data, second area in 310 is in order to the odd address data BufB_ODD of storage source data, first area in 320 is in order to the odd address data BufA_ODD of storage target data, second area in 320 is in order to the even address data BufB_EVEN of storage source data, and these two SRAM carry out access control by said write circuit 330, so, system (System) is equivalent to identify 4 groups of SRAM with kernel (IP), and when carrying out access simultaneously, the priority memory access power on first internal memory and second internal memory is respectively:
During access simultaneously, priority memory access power is: BufA_EVEN＞BufB_ODD on first internal memory;
During access simultaneously, priority memory access power is: BufA_ODD＞BufB_EVEN on second internal memory.
In actual applications, BufA_EVEN and BufB_ODD be access simultaneously not, and BufA_ODD and BufB_EVEN be access simultaneously not, therefore has following 2 kinds of application:
Use in the 1:32bit bus system, when system in SRAM during access data, each sequential cycle is contained 32bit, can two pixels of access (Pixel), do control by WEn and CEn to SRAM, can realize:
(11), in the cycle, write the first area of the BufA_EVEN of a pixel, and write the first area of the BufA_ODD of a pixel, referring to Fig. 7 (1a) and Fig. 7 (1b) to second memory to first memory 1 sequential;
(12), in the cycle, write the second area of the BufB_EVEN of a pixel, and write the second area of the BufB_ODD of a pixel, with reference to figure 7 (1c) and Fig. 7 (1d) to first memory to second memory 1 sequential;
When using the 2:IP end and being Source (BufA)+Destination (BufB) → Buffer computing,, do control by CEn and can realize reading simultaneously and carrying out point-to-point computing SRAM based on such scheme of the present invention, as s0+d0, s1+d1, specifically there are 2 kinds of application in s2+d2...:
(21), the BufA_EVEN+BufB_EVEN computing, because BufA_EVEN adheres to different entity SRAM separately with BufB_EVEN, thus can read out computing simultaneously, with reference to figure 7 (2a) and Fig. 7 (2b);
(22), BufA_ODD+BufB_ODD is because BufA_ODD adheres to different entity SRAM separately with BufB_ODD, so can read out computing simultaneously.
Fig. 8 is the comparison diagram of known technology and usable floor area of the present invention.As shown in Figure 2, known technology system uses the static random access memory of 4 64x32 positions to constitute an impact damper.The technology of the present invention is to use the static random access memory of 2 128x32 positions to constitute an impact damper.Fig. 8 is to use the static random access memory of the technology of the present invention to constitute an impact damper, the result that it is synthesized in TSMC 0.13 micron system.As shown in Figure 8, the buffer structure of the technology of the present invention can be saved the area of many hardware really.
Purpose of the present invention for only use two independently internal memory to constitute the impact damper of hardware silicon intellectual property.When color data deposits impact damper in, utilize write circuit 330 of the present invention, deposit in special arrangement mode in the impact damper of hardware silicon intellectual property, and the special read-write demand of this arrangement mode can reach color data can allow reading and writing data the time and use the time.
As shown in the above description, known technology is in order to support color form storing modes different on the different platform, the internal memory composition mode of the impact damper of hardware silicon intellectual property is utilized the access of coming of four internal memory branches instead, but in fact, the impact damper of hardware silicon intellectual property splits into four internal memories and forms the waste that can cause the space, and the complexity that increases access circuit.Yet the present invention only uses the framework of two internal memories to be the basis, with simple circuit data is put into the impact damper of hardware silicon intellectual property with special rehearsal mode, the complexity in the time of can saving the impact damper of the area of hardware and software operation hardware silicon intellectual property.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (10)
1, a kind of buffer structure of hardware silicon intellectual property, it comprises:
One first internal memory, it has the memory space of a 2N m position, this first internal memory is divided into a first area and a second area, this first area is made up of by the memory space of individual m position, the 0th m position to the (N-1) the position, this second area is made up of by the memory space of individual m position, N m position to the (2N-1) the position, in the middle of, N, m are positive integer;
One second internal memory, it has the memory space of a 2N m position, this second internal memory is divided into one the 3rd zone and one the 4th zone, the 3rd zone is made up of by the memory space of individual m position, the 0th m position to the (N-1) the position, and the 4th zone is made up of by the memory space of individual m position, N m position to the (2N-1) the position; And
One write circuit is connected to this first internal memory and this second internal memory, in order to this first internal memory and this second internal memory are carried out write activity;
Wherein, this write circuit is written to the even address data of a source data in the 4th zone of this second internal memory, this write circuit is written to the odd address data of this source data the second area of this first internal memory, this write circuit is written to the first area of this first internal memory with the even address data of a target data, and this write circuit is written to the odd address data of this target data in the 3rd zone of this second internal memory.
2, buffer structure as claimed in claim 1 is characterized in that:
This write circuit comprise first with Men Zhidi four and door and first multiplexer to the, four multiplexers, this first multiplexer is connected to an address bus of this first internal memory, this second multiplexer is connected to a data bus of this first internal memory, this first is connected to a write signal pin of this first internal memory with door, this second is connected to an enable signal pin of this first internal memory with door, the 3rd multiplexer is connected to the address bus of this second internal memory, the 4th multiplexer is connected to the data bus of this second internal memory, the 3rd is connected to a write signal pin of this second internal memory with door, and the 4th is connected to an enable signal pin of this second internal memory with door.
3, buffer structure as claimed in claim 2 is characterized in that:
This first multiplexer receives the odd address of this source data and the even address of this target data, in order to producing the Input Address signal of this first internal memory, and exports this address bus of this first internal memory to.
4, buffer structure as claimed in claim 2 is characterized in that:
This second multiplexer receives the odd address data of this source data and the even address data of this target data, in order to producing the input data signal of this first internal memory, and exports this data bus of this first internal memory to.
5, buffer structure as claimed in claim 2 is characterized in that:
The 3rd multiplexer receives the even address of this source data and the odd address of this target data, in order to producing the Input Address signal of this second internal memory, and exports this address bus of this second internal memory to.
6, buffer structure as claimed in claim 2 is characterized in that:
The 4th multiplexer receives the even address data of this source data and the odd address data of this target data, in order to producing the input data signal of this second internal memory, and exports this data bus of this second internal memory to.
7, buffer structure as claimed in claim 2 is characterized in that:
This first receives a write signal of the even address of the write signal of odd address of this source data and this target data with door, in order to producing a write signal of this first internal memory, and exports this write signal pin of this first internal memory to.
8, buffer structure as claimed in claim 2 is characterized in that:
This second receives an enable signal of the even address of the enable signal of odd address of this source data and this target data with door, in order to producing an enable signal of this first internal memory, and exports this enable signal pin of this first internal memory to.
9, buffer structure as claimed in claim 2 is characterized in that:
The 3rd receives a write signal of the odd address of the write signal of even address of this source data and this target data with door, in order to producing a write signal of this second internal memory, and exports this write signal pin of this second internal memory to.
10, buffer structure as claimed in claim 2 is characterized in that:
The 4th receives an enable signal of the odd address of the enable signal of even address of this source data and this target data with door, in order to producing an enable signal of this second internal memory, and exports this enable signal pin of this second internal memory to.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681082A (en) * | 2013-11-26 | 2015-06-03 | 国际商业机器公司 | Method for write and read collision avoidance in single port memory devices and semiconductor chip |
| CN111610933A (en) * | 2020-05-22 | 2020-09-01 | 芯颖科技有限公司 | Data storage method, device and system based on dynamic update of RAM data |
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2009
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681082A (en) * | 2013-11-26 | 2015-06-03 | 国际商业机器公司 | Method for write and read collision avoidance in single port memory devices and semiconductor chip |
| CN104681082B (en) * | 2013-11-26 | 2018-06-01 | 格芯公司 | Reading and write conflict avoiding method and its semiconductor chip in single-port memory device |
| CN111610933A (en) * | 2020-05-22 | 2020-09-01 | 芯颖科技有限公司 | Data storage method, device and system based on dynamic update of RAM data |
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