JPS63175953A - Sequential access memory - Google Patents

Abstract

PURPOSE:To suppress the increase in the number of constituting elements even when a storing capacity is increase by dividing a ring pointer to constitute more than three address decoders, and executing addressing above three- dimension. CONSTITUTION:The ring pointer is divided to constitute the more than three address decoders to carry out the addressing above the three-dimension. For instance, when a writing start signal is inputted, the output signal r1 of the ring pointer WR1 and the output signal a1 of the ring pointer WA1 go to H level, and the output signals r2-rn and a2 go to L level. These signals are inputted to AND gates G1-G2n address data A1 go to the H level, A2-A2n go to the L level to execute the addressing. Thereafter, the output signal of the H level steps one by one in a write address row counter WR for every one clock pulse, makes a round in the write address row counter WR and a write address column counter WC steps by one.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequential access memory used in the fields of communication and signal processing.

[Conventional technology]

FIG. 4 is a system diagram showing a conventional elastic store circuit. In FIG. 4, CI1 to C44 are store cells, WR is a write address row counter, WC is a write address column counter, RR is a read address row counter, RC is a read address column counter, and WR1
~WR4, WC1~WC4, RRI~RR4, RCI~
RC4 is a ring pointer. In addition, WS is a write start signal, DI is input data, R3 is a read start signal, D
o is output data.

Next, the operation will be explained. When the write start signal WS is input from the outside, in the write address row counter WR, only the ring pointer WRI becomes the "H" level, and the ring pointers WR2 to WR4 become the rLJ level. Similarly, in the write address column counter WC, only the ring pointer WCI is at the rHJ level, and the ring pointers WC2 to WC4 are at the rLJ level.

After this, every time a clock pulse (not shown) is input, the rHJ level is transmitted to the write address row counter WR in the order of ring pointer WRI → WR2 → WR3-WR4, and the level of ring pointer WR4 = "H".
One clock later, the level of ring pointer WRI =
becomes “H” and at the same time the write address column counter W
Also in C, the level of ring pointer WCI = rLJ
.

The level of ring pointer WC2 becomes "H".

As described above, the address is incremented one by one and the store cell is accessed. For reading, read start signal R3
This results in an operation similar to writing.

[Problem that the invention seeks to solve]

Since the conventional elastic store circuit is configured as described above, one ring pointer must be provided for each column and row of store cells, and the ring pointer has a large number of components compared to the store cell. Since a large number of elements are required, there is a problem in that the total number of constituent elements increases.

The present invention has been made in view of these points, and an object thereof is to obtain a sequential access memory that can suppress an increase in the number of constituent elements even if the storage capacity is increased.

[Means for solving problems]

In order to achieve such an object, the present invention uses a ring pointer to increment addresses one by one and sequentially write and read data in a sequential access memory, in which the ring pointer is divided into three
This device is configured with three or more address decoders and performs addressing in three or more dimensions.

[Effect]

In the sequential access memory according to the present invention, addressing in three or more dimensions is performed.

〔Example〕

FIG. 1 shows an elastic store circuit as an embodiment of a sequential access memory according to the present invention.

In Figure 1, CIl~C(2n)(2n) is (2n
) A store cell forming a store circuit with a capacity of (2n) bits, WA is an auxiliary write address row counter,
WAI, WA2 are ring pointers, 01~G (2n)
is an AND gate, and the write address low counter W
R and the auxiliary write address row counter WA correspond to the write address row counter WR in FIG. Also, r
1~rn, at, a2 are ring pointers WR1~WRn
, signals output from WA 1 and WA 2, A - A
(2n) is address data. In FIG. 1, the same or equivalent parts as in FIG. 4 are given the same reference numerals.

The elastic store circuit shown in FIG. 1 has three address decoders. That is, they are a write address row counter WR, an auxiliary write address row counter WA, and a write address column counter WC.

Next, the operation will be explained. In the elastic store circuit configured as shown in Fig. 1, the write start signal WS
(See Figure 4) is input, the ring pointer WR
The output signal r1 of I and the output signal a1 of ring pointer WAI become rHJ level, and the output signals r2 to rn and a
2 is the rLJ level. These signals are input to AND gates 01 to G (2n), and address data A1 is
The HJ level, A2 to A (2n), becomes the rLJ level, and addressing is performed.

From this point on, the "H" level output signal in the write address row counter WR increments one by one for each clock pulse and makes one round in the write address row counter WR, that is, WR1→WR2→...→ W
When the rHJ level output shifts to Rn-4WR1, the output signal a1 becomes the "L" level and the output signal a2 becomes the rHJ level. Write address low counter WR is next 1
When the circuit rotates, the output signal a1 becomes "H" level and a2 becomes "L" level.
level, and the write address column counter WC becomes 1.
Take one step forward.

Since this embodiment operates as described above, when the number of stored cells is the same, the number of ring pointers of the write address row counter WR is halved compared to the conventional example.

An example of a 16-bit x 16-bit elastic child circuit is shown in FIG. 2 as a second embodiment.

In FIG. 2, C is a 16-bit by 16-bit store cell matrix, and G is a group of AND gates. In this second embodiment, both the write address row counter WR and the auxiliary write address row counter WA are composed of four ring pointers, and the write address row counter WR is configured with four ring pointers.
r4, auxiliary write address row counter WA outputs four signals a1 to a4. In addition, the write address column counter WC outputs 16 signals b1 to b according to the 16 bits.
Outputs 16.

In this second embodiment, the auxiliary write address row counter WA is composed of four pieces, so when the number of store cells is the same, the number of write address row counters WR is 1/1 compared to the conventional example. It becomes 4.

A time chart in the second embodiment is shown in FIG.

In FIG. 3, (a) shows a clock, and (b) to (
d) is the output signal of the write address row counter WR, (
Q) to (h) indicate the output signals of the auxiliary write address row counter WA, and (i) and (J) indicate the output signals of the write address column counter WC. As can be seen from FIG. 3, the number of write address row counters WR can be reduced in inverse proportion to the number of output signals of auxiliary write address row counter WA.

Above 1st. In the explanation of the operation of the second embodiment, only the write operation is shown, but the read operation also operates in the same manner by using the same configuration. That is, the number of ring pointers of the read address row counter RR can be decreased in inverse proportion to the number of output signals of the auxiliary read address row counter (not shown).

Note that in the above embodiment, the write address row counter W
Although the addressing is changed in the order of R→auxiliary write address row counter WA−write address column counter WC, this order is arbitrary, and the same effect can be achieved regardless of the order.

Further, in the above embodiment, the address decoder is three-dimensional, but it may be four-dimensional as well, which has the effect of further reducing the number of constituent elements.

Further, in the above embodiment, the case of an elastic store circuit has been described, but other sequential access memories may be used, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As explained above, the present invention divides the ring pointer to configure three or more address decoders and performs three-dimensional or more addressing, thereby reducing the number of ring pointers in the write address row counter to the auxiliary write address row counter. The number of ring pointers of the read address row counter can be decreased in inverse proportion to the number of output signals of the auxiliary read address row counter, so even if the storage capacity is increased, the number of component elements can be reduced. It has the effect of suppressing the increase in

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an elastic store circuit as an embodiment of the sequential access memory according to the present invention, FIG. 2 is a system diagram showing the second embodiment, and FIG. 3 is the circuit of FIG. 2. FIG. 4 is a system diagram showing a conventional elastic store circuit. WR...Write address row counter, WA...Auxiliary write address row counter, WC...Write address column counter, WRI~WRn, WAI, WA
2. CI 1-G (2n) (2n)...Store cell, G1-G (2n)...And gate.

Claims (2)

[Claims] (1) In a sequential access memory that uses a ring pointer to increment addresses one by one and sequentially write and read data, the ring pointer is divided to configure three or more address decoders, and the three-dimensional A sequential access memory characterized by performing the above addressing. (2) Claim 1, characterized in that the sequential access memory is an elastic store circuit.
Sequential access memory as described in section.