CN101645301A - 一种用于读数据采样的温度自适应调整方法及装置 - Google Patents
一种用于读数据采样的温度自适应调整方法及装置 Download PDFInfo
- Publication number
- CN101645301A CN101645301A CN200910085035A CN200910085035A CN101645301A CN 101645301 A CN101645301 A CN 101645301A CN 200910085035 A CN200910085035 A CN 200910085035A CN 200910085035 A CN200910085035 A CN 200910085035A CN 101645301 A CN101645301 A CN 101645301A
- Authority
- CN
- China
- Prior art keywords
- sampling
- clk
- temperature
- read data
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (12)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910085035.9A CN101645301B (zh) | 2009-05-27 | 2009-05-27 | 一种用于读数据采样的温度自适应调整方法及装置 |
US12/786,776 US8315114B2 (en) | 2009-05-27 | 2010-05-25 | Memory controllers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910085035.9A CN101645301B (zh) | 2009-05-27 | 2009-05-27 | 一种用于读数据采样的温度自适应调整方法及装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101645301A true CN101645301A (zh) | 2010-02-10 |
CN101645301B CN101645301B (zh) | 2013-06-12 |
Family
ID=41657137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910085035.9A Expired - Fee Related CN101645301B (zh) | 2009-05-27 | 2009-05-27 | 一种用于读数据采样的温度自适应调整方法及装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8315114B2 (zh) |
CN (1) | CN101645301B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102055406A (zh) * | 2010-10-22 | 2011-05-11 | 中兴通讯股份有限公司 | 驱动器时序差的处理方法及装置 |
CN103019302A (zh) * | 2012-12-07 | 2013-04-03 | 北京星网锐捷网络技术有限公司 | 基于温度变化动态调整时序的方法、装置及网络设备 |
CN103226969A (zh) * | 2013-01-11 | 2013-07-31 | 昆山慧凝微电子有限公司 | Ddr2读写操作数字延迟链工艺-温度-电压控制器电路 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8272781B2 (en) * | 2006-08-01 | 2012-09-25 | Intel Corporation | Dynamic power control of a memory device thermal sensor |
CN101692346B (zh) * | 2009-06-19 | 2013-06-26 | 无锡中星微电子有限公司 | 一种存储器数据采样装置及一种采样控制器 |
US8355294B2 (en) * | 2011-03-18 | 2013-01-15 | Freescale Semiconductor, Inc | Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations |
JP2013065372A (ja) * | 2011-09-16 | 2013-04-11 | Elpida Memory Inc | 半導体装置およびそれを利用した情報処理システム |
US9368172B2 (en) * | 2014-02-03 | 2016-06-14 | Rambus Inc. | Read strobe gating mechanism |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5642386A (en) * | 1994-06-30 | 1997-06-24 | Massachusetts Institute Of Technology | Data sampling circuit for a burst mode communication system |
US6226204B1 (en) * | 1997-08-30 | 2001-05-01 | Kabushuki Kaisha Toshiba | Semiconductor integrated circuit device |
CN1665135A (zh) * | 2004-01-20 | 2005-09-07 | 三星电子株式会社 | 延迟信号产生器电路以及包括该电路的存储器系统 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7215584B2 (en) * | 2005-07-01 | 2007-05-08 | Lsi Logic Corporation | Method and/or apparatus for training DQS strobe gating |
US7685393B2 (en) * | 2006-06-30 | 2010-03-23 | Mosaid Technologies Incorporated | Synchronous memory read data capture |
JP2009176371A (ja) * | 2008-01-25 | 2009-08-06 | Nec Electronics Corp | 半導体集積回路装置とそのテスト方法 |
-
2009
- 2009-05-27 CN CN200910085035.9A patent/CN101645301B/zh not_active Expired - Fee Related
-
2010
- 2010-05-25 US US12/786,776 patent/US8315114B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5642386A (en) * | 1994-06-30 | 1997-06-24 | Massachusetts Institute Of Technology | Data sampling circuit for a burst mode communication system |
US6226204B1 (en) * | 1997-08-30 | 2001-05-01 | Kabushuki Kaisha Toshiba | Semiconductor integrated circuit device |
CN1665135A (zh) * | 2004-01-20 | 2005-09-07 | 三星电子株式会社 | 延迟信号产生器电路以及包括该电路的存储器系统 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102055406A (zh) * | 2010-10-22 | 2011-05-11 | 中兴通讯股份有限公司 | 驱动器时序差的处理方法及装置 |
CN102055406B (zh) * | 2010-10-22 | 2014-08-13 | 中兴通讯股份有限公司 | 驱动器时序差的处理方法及装置 |
CN103019302A (zh) * | 2012-12-07 | 2013-04-03 | 北京星网锐捷网络技术有限公司 | 基于温度变化动态调整时序的方法、装置及网络设备 |
CN103019302B (zh) * | 2012-12-07 | 2015-07-22 | 北京星网锐捷网络技术有限公司 | 基于温度变化动态调整时序的方法、装置及网络设备 |
CN103226969A (zh) * | 2013-01-11 | 2013-07-31 | 昆山慧凝微电子有限公司 | Ddr2读写操作数字延迟链工艺-温度-电压控制器电路 |
CN103226969B (zh) * | 2013-01-11 | 2015-08-05 | 昆山慧凝微电子有限公司 | Ddr2读写操作数字延迟链工艺-温度-电压控制器电路 |
Also Published As
Publication number | Publication date |
---|---|
US20100306459A1 (en) | 2010-12-02 |
US8315114B2 (en) | 2012-11-20 |
CN101645301B (zh) | 2013-06-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101645301B (zh) | 一种用于读数据采样的温度自适应调整方法及装置 | |
JP5537568B2 (ja) | 信号受信回路、メモリコントローラ、プロセッサ、コンピュータ及び位相制御方法 | |
CN102981776B (zh) | 双倍数据率虚拟静态随机存取存储器及其控制器、存取与操作方法、写入与读取方法 | |
US8115529B2 (en) | Device and control method of device | |
EP1903446B1 (en) | Apparatus and method for controlling a memory interface | |
US7586337B2 (en) | Circuit for switching between two clock signals independently of the frequency of the clock signals | |
KR20060044526A (ko) | 메모리 인터페이스 제어 회로와 메모리 인터페이스 제어방법 | |
KR100540487B1 (ko) | 데이터 출력제어회로 | |
KR20060101334A (ko) | 메모리 인터페이스 제어 회로 | |
KR100988809B1 (ko) | 반도체 메모리 장치 및 출력인에이블 신호 생성 방법 | |
CN108038068B (zh) | 一种基于ddr读数据同步方法及系统 | |
US10163469B2 (en) | System and method for write data bus control in a stacked memory device | |
JPH09139076A (ja) | 半導体記憶装置 | |
CN101692346A (zh) | 一种存储器数据采样装置及一种采样控制器 | |
US7493461B1 (en) | Dynamic phase alignment for resynchronization of captured data | |
US8754656B2 (en) | High speed test circuit and method | |
KR102685395B1 (ko) | 반도체 장치, 반도체 시스템 및 반도체 장치의 동작 방법 | |
US8307236B2 (en) | Oversampling-based scheme for synchronous interface communication | |
TWI433164B (zh) | 以內部時脈存取資料之資料存取裝置與相關方法 | |
US6972998B1 (en) | Double data rate memory devices including clock domain alignment circuits and methods of operation thereof | |
US8947956B2 (en) | Delay circuit and latency control circuit of memory, and signal delay method thereof | |
JP5221609B2 (ja) | Dllを共用してサンプリング位相設定を行うホストコントローラ | |
WO2013042233A1 (ja) | 半導体装置 | |
CN113726335B (zh) | 时钟控制电路、时钟电路和电子设备 | |
Wang et al. | Design and implementation of DDR SDRAM controller based on FPGA in satellite navigation system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: WUXI VIMICRO CO., LTD. Free format text: FORMER OWNER: BEIJING ZHONGXING MICROELECTRONICS CO., LTD. Effective date: 20110402 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100083 16/F, SHINING BUILDING, NO. 35, XUEYUAN ROAD, HAIDIAN DISTRICT, BEIJING TO: 214028 610, NATIONAL INTEGRATED CIRCUIT DESIGN PARK (CHUANGYUAN BUILDING), NO. 21-1, CHANGJIANG ROAD, WUXI NEW DISTRICT, JIANGSU PROVINCE |
|
TA01 | Transfer of patent application right |
Effective date of registration: 20110402 Address after: 214028 national integrated circuit design (21-1), Changjiang Road, New District, Jiangsu, Wuxi, China, China (610) Applicant after: Wuxi Vimicro Co., Ltd. Address before: 100083 Haidian District, Xueyuan Road, No. 35, the world building, the second floor of the building on the ground floor, No. 16 Applicant before: Beijing Vimicro Corporation Effective date of registration: 20110402 Address after: 214028 national integrated circuit design (21-1), Changjiang Road, New District, Jiangsu, Wuxi, China, China (610) Applicant after: Wuxi Vimicro Co., Ltd. Address before: 100083 Haidian District, Xueyuan Road, No. 35, the world building, the second floor of the building on the ground floor, No. 16 Applicant before: Beijing Vimicro Corporation |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130612 Termination date: 20190527 |