CN101636834A - Semiconductor device and manufacture method thereof - Google Patents

Semiconductor device and manufacture method thereof Download PDF

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Publication number
CN101636834A
CN101636834A CN200780052210A CN200780052210A CN101636834A CN 101636834 A CN101636834 A CN 101636834A CN 200780052210 A CN200780052210 A CN 200780052210A CN 200780052210 A CN200780052210 A CN 200780052210A CN 101636834 A CN101636834 A CN 101636834A
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film
dielectric film
pattern
lower electrode
semiconductor device
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CN200780052210A
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CN101636834B (en
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吉村铁夫
渡边健一
大塚敏志
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Fujitsu Semiconductor Memory Solution Ltd
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A kind of semiconductor device and manufacture method thereof are provided, and semiconductor device has capacitor, and this capacitor has: dielectric film, and it is formed on the top of semiconductor substrate 1; Capacity cell, it has the capacitor lower electrode 11b that is formed on the dielectric film 7, the upper surface that is formed on capacitor lower electrode 11b and the dielectric film on the side 13, is formed on the dielectric film 13 and the electric capacity upper electrode 19b broader than capacitor lower electrode 11b, wherein, this electric capacity upper electrode 19b is made of first metal pattern of metal film; Wiring 19a, 19b, it is formed on the dielectric film 7, is made of second metal pattern of described metal film.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to semiconductor device and manufacture method thereof, particularly have the semiconductor device and the manufacture method thereof of the MIM capacity cell of the structure that between lower metal film and upper metal film, forms dielectric film.
Background technology
(Metal-Insulator-Metal: metal-insulator-metal) capacity cell is used as the capacity cell of the high frequency analog integrated circuit that requires the high speed operation with MIM.(Metal-Insulator-Semiconductor: metal-insulator semiconductor (MIS)) capacity cell can reduce dead resistance and parasitic capacitance to the MIM capacity cell with respect to MOS.
As the MIM capacity cell, for example, in TOHKEMY 2003-318269 communique (patent documentation 1), record such structure, promptly, have: be formed on following membrane electrode film on the interlayer dielectric, that constitute by aluminium bronze (AlCu), be formed on down the dielectric film on the membrane electrode film, be formed on the last membrane electrode film on the dielectric film.
In addition, in TOHKEMY 2004-303908 communique (patent documentation 2), record: to being formed at the AlCu film portrayal pattern on the interlayer dielectric, on interlayer dielectric, form the upper electrode that forms the MIM capacity cell when connecting up thus, wherein, above-mentioned interlayer dielectric covered substrate.
In TOHKEMY 2006-210952 communique (patent documentation 3), record: with the MIM capacity cell of patent documentation 2 same structures in, make the thickness of capacitor lower electrode thinner, in the contact site formation interlayer dielectric thereunder that will be connected with capacitor lower electrode than electric capacity thickness of upper electrode.
In the MIM capacity cell that patent documentation 2, patent documentation 3 are put down in writing, capacitor lower electrode, capacitor insulating film and electric capacity upper electrode have identical flat shape.
In addition, in JP special table 2003-526927 communique (patent documentation 4), record such MIM capacitor, that is, have the capacitor lower electrode of same level shape and dielectric film, be formed on electric capacity upper electrode on the dielectric film with the shape narrower than dielectric film.
Patent documentation 1:JP spy opens the 2003-318269 communique
Patent documentation 2:JP spy opens the 2004-303908 communique
Patent documentation 3:JP spy opens the 2006-210952 communique
The special table of patent documentation 4:JP 2003-526927 communique
Summary of the invention
Yet, for example, as shown in figure 16, form successively on the interlayer dielectric 101 first barrier metal film 102, AlCu film 103, second barrier metal film 104, dielectric film 105 and on membrane electrode film 106, then, upper electrode film 106 and dielectric film 105 are portrayed pattern respectively, form the MIM capacity cell that patent documentation 1 is put down in writing through such operation.
Generally, be formed for constituting the AlCu film 103 of the following membrane electrode film of MIM capacity cell 100 by sputter process, thereby make AlCu film 103 constitute the polycrystal structure, crystal size is inhomogeneous, the degree of depth of the recess that produces owing to the crystal crystal boundary has nothing in common with each other, and therefore causes producing on the surface of AlCu film 103 concavo-convex.AlCu film 103 is thick more, and this is concavo-convex remarkable more.
On the other hand, in the side of MIM capacity cell 100,, thereby form wiring 107a, 107b to same first barrier metal film 102, AlCu film 103 and second barrier metal film, 104 portrayal patterns.Under these circumstances,, form AlCu film 103 thicker, therefore make the concavo-convex difference on AlCu film 103 surfaces become big in order to make the resistance decreasing of wiring 107a, 107b.
If the concavo-convex difference of AlCu film 103 becomes big, then make the membrane thickness unevenness of formation dielectric film 105 thereon, can produce the place that electric field is concentrated, thereby might cause leakage current to flow through, on the dielectric film on its protuberance 105, produce insulation damages.
Relative therewith, shown in Figure 17 A, in the MIM capacity cell that patent documentation 2,3 is put down in writing, between AlCu film 103 and first barrier metal film 102 below it, be formed with dielectric film 105, therefore, dielectric film 105 can not be subjected to the concavo-convex influence that produces on the upper surface of AlCu film 103.In such structure, first barrier metal film 102 becomes lower electrode, and AlCu film 103 becomes upper electrode.
But,, then be difficult to control the etched terminal point of AlCu film 103 as if AlCu film 103 thickenings.Thereby, when in AlCu film 103, undercut taking place, can cause the leakage current of transverse direction to increase.
On the other hand, also etched to dielectric film 105 after AlCu film 103 shown in Figure 17 B carry out under the etched situation superfluously, thus make AlCu film 103 identical with the shape of dielectric film 105.Its result makes first barrier metal film (lower electrode) 102 and AlCu film (upper electrode) 103 approaching at the circumference of dielectric film 105, and leakage current is flow through between them easily.
Especially, if increase the charge capacity of MIM electric capacity 100 and make dielectric film 105 attenuation, then therefore the etching control of dielectric film 105 difficulty that also becomes makes AlCu film 103 identical with the flat shape of first barrier metal film 102 by the portrayal pattern easily.
The purpose of this invention is to provide a kind of semiconductor device and manufacture method thereof that can improve the characteristic of capacity cell.
Solve the method for problem
According to technical scheme of the present invention, have: capacity cell, it has the capacitor lower electrode that is formed on the dielectric film, is formed on the upper surface of capacitor lower electrode and the electric capacity dielectric film on the side, is formed on the electric capacity dielectric film and the electric capacity upper electrode broader than capacitor lower electrode, wherein, this electric capacity upper electrode is made of first metal pattern of metal film; Wiring, it is formed on the dielectric film, is made of second metal pattern of metal film.
The effect of invention
Pattern by the metal film that constitutes wiring constitutes the electric capacity upper electrode, and the electric capacity upper electrode is formed the shape broader than capacitor lower electrode, further the electric capacity dielectric film is formed the upper surface of covering capacitor lower electrode and the shape of side.
Thus, under the situation that constitutes the electric capacity upper electrode by the metal film that constitutes wiring, also can make electric capacity upper electrode and capacitor lower electrode identical with the electric capacity dielectric film or more than it, can be suppressed at the leakage current of the circumference of capacity cell in the distance of circumference.
Description of drawings
Figure 1A～Fig. 1 M is the semiconductor device of expression first embodiment of the invention and the profile that forms operation thereof.
Fig. 1 D.
Fig. 1 G.
Fig. 1 J.
Fig. 1 L.
Fig. 2 A～Fig. 2 K is the semiconductor device of expression first embodiment of the invention and the vertical view that forms operation thereof.
Fig. 2 D.
Fig. 2 G.
Fig. 2 J.
Fig. 3 A～Fig. 3 D is the semiconductor device of expression second embodiment of the invention and the profile that forms operation thereof.
Fig. 3 C.
Fig. 4 A～Fig. 4 C is the semiconductor device of expression second embodiment of the invention and the vertical view that forms operation thereof.
Fig. 4 C.
Fig. 5 A～Fig. 5 J is the semiconductor device of expression third embodiment of the invention and the profile that forms operation thereof.
Fig. 5 D.
Fig. 5 F.
Fig. 5 H.
Fig. 5 J.
Fig. 6 is the vertical view of the 3rd～the 5th semiconductor device of expression embodiment of the present invention.
Fig. 7 is the profile that carries out the state after wet type (wet) is handled behind the dielectric film portrayal pattern of expression to the capacity cell in the semiconductor device that constitutes third embodiment of the invention.
Fig. 8 A represent to constitute third embodiment of the invention semiconductor device capacity cell and with reference to the charge capacity of the capacity cell of (reference); Fig. 8 B represents to constitute the leakage current characteristic of the capacity cell of the capacity cell of semiconductor device of third embodiment of the invention and reference.
Fig. 9 A～Fig. 9 G is the semiconductor device of expression four embodiment of the invention and the profile that forms operation thereof.
Fig. 9 D.
Fig. 9 F.
Figure 10 A～Figure 10 C is the semiconductor device of expression four embodiment of the invention and another the routine profile that forms operation thereof.
Figure 11 A～Figure 11 H is the semiconductor device of expression fifth embodiment of the invention and the profile that forms operation thereof.
Figure 11 D.
Figure 11 G.
Figure 12 is the vertical view of the semiconductor device of expression sixth embodiment of the invention.
Figure 13 A～Figure 13 J is at the semiconductor device of sixth embodiment of the invention and forms the profile of observing from the I-I line of Figure 12 in the operation.
Figure 13 C.
Figure 13 E.
Figure 13 G.
Figure 13 I.
Figure 14 A～Figure 14 H is at the semiconductor device of sixth embodiment of the invention and forms the profile of observing from the II-II line of Figure 12 in the operation.
Figure 14 C.
Figure 14 E.
Figure 14 G.
Figure 14 I.
Figure 15 is a profile of representing semiconductor device as a reference.
Figure 16 is the profile of the semiconductor device of expression first prior art.
Figure 17 A, Figure 17 B are respectively the profiles of the semiconductor device of second, third prior art of expression.
Embodiment
Below, based on accompanying drawing embodiments of the present invention are elaborated.
(first execution mode)
Figure 1A～Fig. 1 M is the profile of formation operation of the semiconductor device of expression first embodiment of the invention; Fig. 2 A～Fig. 2 K is the vertical view of formation operation of the semiconductor device of expression first embodiment of the invention.In addition, Figure 1A is the profile at the V-V line place of Fig. 2 A.
At first, shown in Figure 1A, Fig. 2 A, on first interlayer dielectric 2 that is formed on the semiconductor substrate 1 of silicon etc., form first barrier metal film, 3, the first leading electrolemma 4 and second barrier metal film 5 successively by sputter, wherein, above-mentioned first interlayer dielectric 2 is made of silicon oxide film.
For example, form titanium (Ti) film of 40nm and the two-layer structure of titanium nitride (TiN) film that thickness is 100nm and be used as first, second barrier metal film 3,5, for example, formation thickness is that AlCu (aluminium bronze) film of 1 μ m is used as the first leading electrolemma 4.
Then, on second barrier metal film 5, apply photoresist, and make its exposure, development, thus the corrosion-resisting pattern (not shown) of formation wiring shape.Then, corrosion-resisting pattern is used as mask,, each film till second barrier metal film, 5 to first barrier metal film 3 is carried out etching by reactive ion etching (RIE) method of utilizing the chlorine serial gas.Under these circumstances, carry out excessive erosion, thus not residual first barrier metal film 3.
Thus, will remain in first barrier metal film, 3, the first leading electrolemma 4 of corrosion-resisting pattern (not shown) below and second barrier metal film 5 wiring 6a, 6b as ground floor.Then, the corrosion-resisting pattern on wiring 6a, the 6b of removal ground floor.
Then, shown in Figure 1B, Fig. 2 B,, on first interlayer dielectric 2, be formed for covering second interlayer dielectric 7 of wiring 6a, the 6b of ground floor by the CVD method.For example, use the gas growing silicon oxide film that contains TEOS (tetraethoxysilane) or silane-based gas, thereby as second interlayer dielectric 7.
Then, by cmp (CMP) method, the upper surface of second interlayer dielectric 7 is carried out planarization.Then, on second interlayer dielectric 7, apply resist 8, and make its exposure, development, thereby for example on wiring 6a, 6b, form peristome 8a～8d.
And then, shown in Fig. 1 C, Fig. 2 C, as mask, be the RIE method of reacting gas for example by using fluorine with resist 8, second interlayer dielectric 7 is carried out anisotropic etching, on wiring 6a, 6b, form the through hole 7a～7d of ground floor thus.
After removing resist 8, shown in Fig. 1 D, Fig. 2 D, in the through hole 7a～7d of ground floor, form the through hole plug-in unit 10a～10d of ground floor.Form the through hole plug-in unit 10a～10d of ground floor by following operation.
That is,, on the bottom surface of through hole 7a～7d and the internal face and second interlayer dielectric 7, form conducting barrier metal film 9a, for example form the TiN film, follow, in the through hole 7a～7d of ground floor, imbed tungsten (W) film 9b by sputter.For example, use the gas that contains tungsten hexafluoride, by CVD method growth W film 9b.
Then,, W film 9b, conducting are ground with barrier metal film 9a, thereby remove W film 9b, conducting barrier metal film 9a from the upper surface of second interlayer dielectric 7 by the CMP method.Thus, with the W film 9b, conducting is used as ground floor with barrier metal film 9a the through hole plug-in unit 10a～10d that remain in the through hole 7a～7d of ground floor.
In addition, also can use metals such as tantalum (Ta), molybdenum (Mo), aluminium (Al), Ti to replace tungsten.
Then, shown in Fig. 1 E, Fig. 2 E, on the through hole plug-in unit 10a～10d of ground floor and second interlayer dielectric 7, form the 3rd barrier metal film 11.For example, form TiN film that Ti film that thickness is 40nm and thickness is 100nm successively as the 3rd barrier metal film 11 by sputter.In addition, also can form the Ta film and replace the Ti film, in addition, also can form TaN and replace the TiN film.
Then, on the 3rd barrier metal film 11, apply resist, and make its exposure, development, form corrosion-resisting pattern 12a, the 12c of wiring usefulness and the corrosion-resisting pattern 12b that capacitor lower electrode is used thus.
Corrosion-resisting pattern 12a, the 12c of wiring usefulness is configured in through hole plug-in unit 10a, the 10d position overlapped of the ground floor of its part and regulation.In addition, the corrosion-resisting pattern 12b that capacitor lower electrode is used for example has dimetric flat shape, and is formed on through hole plug-in unit 10b, 10c position overlapped with other ground floors.
Then, shown in Fig. 1 F, Fig. 2 F, using chlorine is gas, by the RIE method the 3rd barrier metal film 11 is carried out anisotropic etching, the 3rd barrier metal film 11 of corrosion-resisting pattern 12a, 12c below that will remain in wiring usefulness thus is as below wiring barrier metal film 11a, 11c, in addition, will remain in the 3rd barrier metal film 11 of the corrosion-resisting pattern 12b below that capacitor lower electrode uses as capacitor lower electrode 11b.
After removing corrosion-resisting pattern 12a～12c, shown in Fig. 1 G, Fig. 2 G, below form dielectric film 13 on wiring barrier metal film 11a, 11c, capacitor lower electrode 11b and second interlayer dielectric 7.Forming thickness by the CVD method is that the silicon oxide film of 40nm is as dielectric film 13.For example, employed reacting gas is the gas that contains silane-based gas or TEOS when forming silicon oxide film.In addition, also can form silicon nitride film, tantalum-oxide film waits and replaces silicon oxide film.
Then, shown in Fig. 1 H, Fig. 2 H, on dielectric film 13, apply photoresist, and make its exposure, development, thereby form corrosion-resisting pattern 14.Corrosion-resisting pattern 14 forms flat shape overlapping with capacitor lower electrode 11b and that expose around the capacitor lower electrode 11b.
Then, corrosion-resisting pattern 14 as mask, is carried out anisotropic etching by the RIE method to dielectric film 13.At dielectric film 13 is under the situation of silicon oxide film, for example, is that gas is used as etching gas with fluorine.
Then, shown in Fig. 1 I, Fig. 2 I, by sputter, for example, dielectric film 13, below wiring barrier metal film 11a, 11c and second interlayer dielectric 7 form the 4th barrier metal film 15, the second leading electrolemma 16, the 5th barrier metal film 17 on the whole successively, wherein, above-mentioned the 4th barrier metal film 15 is that the TiN film of 40nm constitutes by thickness, the above-mentioned second leading electrolemma 16 is that the AlCu film of 1 μ m constitutes by thickness, and above-mentioned the 5th barrier metal film 17 is that the Ti film of 5nm and the stepped construction of the TiN film that thickness is 100nm constitute by thickness.
In addition, also AlSi film, AlSiCu film can be used as the second leading electrolemma 16, to replace the AlCu film.In addition, also can use the TaN film to replace constituting the TiN film of the 4th, the 5th barrier metal film 15,17, also can use the Ta film to replace constituting the Ti film of the 5th barrier metal film 17.
Then, on the 5th barrier metal film 17, apply photoresist, and make its exposure, development, thus, shown in Fig. 1 J, Fig. 2 J, form corrosion-resisting pattern 18a, the 18c of wiring usefulness and the corrosion-resisting pattern 18b that upper electrode is used.
The corrosion-resisting pattern 18b that upper electrode is used has the shape overlapping with capacitor lower electrode 11b and dielectric film 13.And, form such shape, that is, at least a portion of the outer peripheral edges of the corrosion-resisting pattern 18b that upper electrode is used is between the outer peripheral edges of the outer peripheral edges of dielectric film 13 and capacitor lower electrode 11b.In addition, form such shape, that is, edge portion from capacitor lower electrode 11b on transverse direction of the edge portion of the corrosion-resisting pattern 18b that upper electrode is used extends, and for example, extends about 0.3 μ m～1.0 μ m.
Under such state, 18a～18c is used as mask with corrosion-resisting pattern, by the RIE method each film till the 5th barrier metal film 17 to the 4th barrier metal film 15 and below wiring barrier metal film 11a, 11c is carried out anisotropic etching.With chlorine is that gas is used as etching gas.In addition, after carrying out etching, remove corrosion-resisting pattern 18a～18c.
In addition, also can between corrosion-resisting pattern 18a～18c and the 5th barrier metal film 17, form silicon oxide film, then, to silicon oxide film portrayal pattern, and used as being hard mask.
Thus, shown in Fig. 1 K, Fig. 2 K, remaining in the 4th barrier metal film 15 of the corrosion-resisting pattern 18b below that upper electrode uses, leading electrolemma 16, the 5th barrier metal film 17 becomes electric capacity upper electrode 19b.And, constitute MIM capacity cell Q by electric capacity upper electrode 19b, dielectric film 13 and capacitor lower electrode 11b 1
In addition, below wiring barrier metal film 11a, 11c, the 4th barrier metal film 15, the second leading electrolemma 16 and the 5th barrier metal film 17 of corrosion-resisting pattern 18a, the 18c below of wiring usefulness wiring 19a, the 19c as the second layer will be remained in.
Yet with condition enactment be: the thickness of the second leading electrolemma 16 of formation electric capacity upper electrode 19b is thicker, and the etch-rate of the second leading electrolemma 16 is higher, and therefore, the dielectric film 13 of its below is also by continuous etching.
Thus, make electric capacity upper electrode 19b roughly consistent with dielectric film 13 outer peripheral edges separately, but the side of capacitor lower electrode 11b is covered by dielectric film 13, and, the edge portion of electric capacity upper electrode 19b is positioned at the oblique upper of the edge portion of capacitor lower electrode 11b across dielectric film 13, therefore the distance of their edge portion is become more than the thickness of dielectric film 13.
By the shape of change electric capacity upper electrode 19b, the interval between the edge portion of adjustment capacitor lower electrode 11b and the edge portion of electric capacity upper electrode 19b, thus be suppressed at the capacity cell Q that is used to form the MIM capacity cell easily 1Edge portion leakage current takes place.
Then, shown in Fig. 1 L,, on second interlayer dielectric 7, be formed for covering MIM capacity cell Q by the CVD method 1And the 3rd interlayer dielectric 20 of wiring 19a, the 19c of the second layer.For example, constitute the 3rd interlayer dielectric 20, use gases such as TEOS, silane to grow by silicon oxide film.
And then, in wiring 19a, the 19c of the second layer and going up separately of electric capacity upper electrode 19b, in the 3rd interlayer dielectric 20, forming the through hole 20a～20d of the second layer, portion forms the through hole plug-in unit 21a～21d of the second layer within it.
In addition, the formation of the through hole plug-in unit 21a～21d of the through hole 20a～20d of the second layer, the second layer is identical with the formation of the through hole 7a～7d of ground floor, through hole plug-in unit 10a～10d, handles forming by metal film forming, photoetching process, CMP.
Then, shown in Fig. 1 M, on the 3rd interlayer dielectric 19, form wiring 25a～25c of the 3rd layer.Wiring 25a～25c of the 3rd layer is made of the stepped construction of the 6th barrier metal film the 22, the 3rd leading electrolemma 23 and the 7th barrier metal film 24.Similarly stepped construction is portrayed pattern with wiring 6a, the 6b of ground floor, form wiring 25a～25c of the 3rd layer thus by photoetching process.
For example, form thickness and be the Ti film of 40nm and two-layer structure that thickness is the TiN of 100nm and be used as the 6th, the 7th barrier metal film 22,24, for example, the AlCu film that forms thickness and be 1 μ m is used as the 3rd leading electrolemma 23.
Then, though not special diagram, the further interlayer dielectric of formation top, wiring etc.
At the MIM of aforesaid structure capacity cell Q 1In, for the edge portion of the electric capacity upper electrode 19b that constitutes by the second leading electrolemma 16 identical etc., portray pattern continuously with the edge portion of the dielectric film 13 of its below with wiring 19a, the 19c of the second layer.
Thus, electric capacity upper electrode 19b forms and dielectric film 13 same flat shapes, dielectric film 13 forms and covers capacitor lower electrode 11b and flat shape on every side thereof, the edge portion that therefore can make the edge portion of electric capacity upper electrode 19b and capacitor lower electrode 11b on transverse direction at a distance of desirable distance.Therefore, can be suppressed at MIM capacity cell Q 1The upper/lower electrode of edge portion between leakage current takes place.
(second execution mode)
Fig. 3 A～Fig. 3 D is the profile of formation operation of the semiconductor device of expression second embodiment of the invention; Fig. 4 A, Fig. 4 C are the vertical views of formation operation of the semiconductor device of expression second embodiment of the invention.In addition, in Fig. 3 A～Fig. 3 D, Fig. 4 A～Fig. 4 C, represent identical key element with the Reference numeral that Figure 1A～Fig. 1 M, Fig. 2 A～Fig. 2 K is identical.
At first, shown in Fig. 3 A, Fig. 3 A, similarly on first interlayer dielectric 2, form wiring 6a, the 6b of ground floor, and then on wiring 6a, the 6b of ground floor and first interlayer dielectric 2, form second interlayer dielectric 7 with first execution mode.Then, on wiring 6a, the 6b of ground floor, form the through hole plug-in unit 10a～10d of ground floor, then, by the method identical with first execution mode, wiring barrier metal film 11a, 11c and capacitor lower electrode 11b below forming on second interlayer dielectric 7.And then, form capacitor lower electrode 11b and the dielectric film 13 that is used to cover its peripheral shape.
Then, shown in Fig. 3 B, Fig. 4 B, by sputter, dielectric film 13, below wiring barrier metal film 11a, 11c and second interlayer dielectric 7 form the 4th barrier metal film 15, second leading electrolemma 16 and the 5th barrier metal film 17 on the whole successively.
Then, on the 5th barrier metal film 17, apply photoresist, and make its exposure, development, form corrosion-resisting pattern 28a, the 28c of wiring usefulness and the corrosion-resisting pattern 28b that upper electrode is used thus.
The corrosion-resisting pattern 28b that upper electrode is used has the flat shape overlapping with capacitor lower electrode 11b and dielectric film 13.And at least a portion of the outer peripheral edges of the corrosion-resisting pattern 28b that the electric capacity upper electrode is used is exposed about 0.3～1.0 μ m from the side of the outer peripheral edges of dielectric film 13.That is, the corrosion-resisting pattern 28b that uses of electric capacity upper electrode is formed broader than dielectric film 13.
Under such state, 28a～28c is used as mask with corrosion-resisting pattern, by RIE method or sputter, each film till the 5th barrier metal film 17 to the 4th barrier metal film 15 and below wiring barrier metal film 11a, 11c is carried out anisotropic etching.Under the situation of using the RIE method, be that gas is used as etching gas with chlorine.In addition, after carrying out etching, remove corrosion-resisting pattern 28a～28c.
Thus, shown in Fig. 3 C, Fig. 4 C, below wiring barrier metal film 11a, the 11c, the 4th barrier metal film 15, the second leading electrolemma 16, the 5th barrier metal film 17 that remain in corrosion-resisting pattern 28a, the 28c below of wiring usefulness become wiring 29a, the 29c of the second layer.
In addition, remain in the 4th barrier metal film 15 of the corrosion-resisting pattern 28b below that upper electrode uses, leading electrolemma 16, the 5th barrier metal film 17 and become electric capacity upper electrode 29b.And, constitute MIM capacity cell Q by electric capacity upper electrode 29b, dielectric film 13 and capacitor lower electrode 11b 2
Therefore the corrosion-resisting pattern 28b that upper electrode is used forms the shape that its periphery exposes from dielectric film 13, and to 4 barrier metal film 15, leading electrolemma 16, when the 5th barrier metal film 17 is carried out etching, the size of dielectric film 13 becomes initial shape.
Then, shown in Fig. 3 D,, form the through hole plug-in unit 21a～21d of the 3rd interlayer dielectric 19, the second layer, wiring 25a～25c of the 3rd layer by the process identical with first execution mode.
At above MIM capacity cell Q 2In, electric capacity upper electrode 29b is formed broader than the dielectric film 13 of its below, and therefore, the distance between the outer peripheral edges of capacitor lower electrode 11b and electric capacity upper electrode 29b is identical from the width that capacitor lower electrode 11b exposes with dielectric film 13.
Therefore, enough big by the amount that dielectric film 13 is exposed, prevent between the circumference of capacitor lower electrode 11b and electric capacity upper electrode 29b, leakage current to take place.
(the 3rd execution mode)
Fig. 5 A～Fig. 5 J is the profile of formation operation of the semiconductor device of expression third embodiment of the invention.In addition, Fig. 6 is the vertical view of the wiring configuration of MIM capacity cell in the semiconductor device of expression third embodiment of the invention and periphery thereof.
In Fig. 5 A, by plasma CVD method, on the semiconductor substrate 31 of silicon etc., for example be formed with that thickness is first silicon oxide film 32 of hundreds of nm～1000nm, for example the thickness of Xing Chenging is 500nm.In addition, the gas that will contain TEOS or silane-based gas is used as its reacting gas that is used for growing silicon oxide film 32.
In addition, by the CVD method, be formed with first silicon nitride film 33 on first silicon oxide film 32, its thickness is 30nm～50nm.In addition, for example, ammonia and silane are used as the reacting gas that is used for the grown silicon nitride film.
And then, on first silicon nitride film 33, be formed with second silicon oxide film 34.And,, on second silicon oxide film 34 and first silicon nitride film 33, be formed with wiring groove 34a～34d by using the photoetching process of resist (not shown).The part wiring is formed on via capacity cell with groove 34a, 34b and forms on the path of below, zone.
In connecting up, be formed with the copper wiring 35a～35d of ground floor with groove 34a～34d.The copper wiring 35a～35d of formation ground floor as described below.
That is,, form barrier metal film, seed membrane on the inner surface of groove 34a～34d and bottom surface, then,, in connecting up, fill copper film with groove 34a～34d by electroplating in wiring by sputter.Then, by the CMP method, remove barrier metal film, seed membrane and copper film on second silicon oxide film, 34 upper surfaces.Thus, with remain in wiring with the copper film in groove 34a～34d as the copper 35a～35d that connects up.
For example, forming thickness is that tantalum (Ta) film of 30nm～50nm is as barrier metal film.In addition, for example, form thickness by sputter and be about the copper film of 100nm as seed membrane.
Then, by the CVD method, form second silicon nitride film 36 on the copper wiring 35a～35d of second silicon oxide film 34 and ground floor, its thickness for example is 30nm～50nm.And then, by plasma CVD method, on second silicon nitride film 35, form the 3rd silicon oxide film 37.
In addition, second silicon nitride film 36 becomes the copper nonproliferation film of the copper wiring 35a～35d of ground floor.
Under aforesaid state, shown in Fig. 5 B, the through hole 37a～37d of the degree of depth of the part of the wiring 35a～35d of formation arrival ground floor in the 3rd silicon oxide film 37 and second silicon nitride film 36.Under these circumstances, also form through hole 37a, 37b being present on copper wiring 35a, the 35b that capacity cell forms the ground floor below the zone.
Then, in through hole 37a～37d, form through hole plug-in unit 38a～38d.That is, in through hole 37a～37d, form titanium (Ti) and be used as glue (being close to) film, then, with tungsten hexafluoride (WF 6) be used for source gas, in through hole 37a～37d, fill tungsten (W) film by the CVD method.Then,, remove glued membrane and W film, will remain in the interior W film of through hole 37a～37d thus as through hole plug-in unit 38a～38d from the upper surface of the 3rd silicon oxide film 37 by the CMP method.
Then, shown in Fig. 5 C, on through hole plug-in unit 38a～38d and the 3rd silicon oxide film 37, form lower electrode film 39.By sputter, the film that forms thickness and be function 50nm～100nm, the performance barrier metal for example forms the TiN film as lower electrode film 39 as lower electrode film 39.
And then, on lower electrode film 39, apply photoresist, and make its exposure, development, thus the corrosion-resisting pattern 40 that the capacitor lower electrode with flat shape of formation capacitor lower electrode is used.
Then, corrosion-resisting pattern 40 is used as mask, lower electrode film 39 is carried out etching.Thereby, shown in Fig. 5 D, will remove the residual lower electrode film 39 in corrosion-resisting pattern 40 backs as capacitor lower electrode 39a.
In addition, also can above through hole plug-in unit 38c, 38d beyond capacity cell forms the zone, form corrosion-resisting pattern (not shown), thus the residual for example lower electrode film 39 of isolated shape on through hole plug-in unit 38c, 38d.Thus, can prevent the through hole plug-in unit 38c, the 38d that constitute by tungsten (W) after operation in impaired.
Then, shown in Fig. 5 E, on capacitor lower electrode 39a and the 3rd silicon oxide film 37, form dielectric film 41 and conductivity diaphragm 42 successively.By using the plasma CVD method of TEOS, form thickness and be about the silicon oxide film of 40nm as dielectric film 41.In addition, for example, form thickness by sputter and be about the TiN film of 30nm as conductivity diaphragm 42.
Then, on conductivity diaphragm 42, apply photoresist, and make its exposure, development, form the corrosion-resisting pattern 43 that capacitor dielectric with and shape that from its outer peripheral edges expose overlapping with capacitor lower electrode 39a is used thus.This corrosion-resisting pattern 43 is formed to comprise and is positioned at through hole plug-in unit 38a, the shape above the 38b that capacity cell forms the zone.
Then, corrosion-resisting pattern 43 is used as mask, conductivity diaphragm 42 and dielectric film 41 are carried out etching.After this etching, dielectric film 41 is still kept the upper surface that is formed on capacitor lower electrode 39a and the state on the side.
Then, shown in Fig. 5 F, for example,, remove corrosion-resisting pattern 43 by using the ashing of oxygen plasma.Under these circumstances, conductivity diaphragm 42 prevents that plasma and ion from entering in the dielectric film 41.
Then, shown in Fig. 5 G, below forming successively on conductivity diaphragm 42, the 3rd silicon oxide film 37 and through hole plug-in unit 38c, the 38d barrier metal film 43, leading electrolemma 44, above barrier metal film 45.
For example, form thickness by sputter and be about the TiN film of 40nm as below barrier metal film 43.In addition, for example form the leading electrolemma 44 of AlCu film conduct that thickness is 1 μ m.And then, for example form form the TiN film that Ti film that thickness is 5nm and thickness is 100nm successively stepped construction as top barrier metal film 45.
At this, shown in the dotted line of Fig. 5 G, also can below form Ti on the following film of barrier metal film 43 and be close to film 43a.Ti is close to film 43a and forms for the close property that improves the 3rd silicon oxide film 37 and TiN film.Also can similarly use the formation that Ti is close to film 43a in the following embodiments.
In addition, also can form the Ta film and replace the Ti film, also can form TaN and replace the TiN film, and then, the AlSi film also can be formed, the AlSiCu film waits and replaces the AlCu film.
Then, shown in Fig. 5 H, apply photoresist on the barrier metal film 45 up, and make its exposure, development, form corrosion-resisting pattern 46b, the 46c of upper electrode the corrosion-resisting pattern 46a that uses and the usefulness that connects up thus.The corrosion-resisting pattern 46a that upper electrode is used has the overlapping and shape that expose from its periphery with dielectric film 41.
In addition, the wiring usefulness corrosion-resisting pattern 46b, 46c have with capacity cell form the zone beyond through hole plug-in unit 38c, the overlapping shape of 38d.
Then, corrosion-resisting pattern 46a, 46b, 46c are used as mask, top barrier metal film 45, leading electrolemma 44 and below barrier metal film 43 are carried out etching by the RIE method.At this moment, for example be that gas is used as reacting gas with chlorine.
In addition, also can corrosion-resisting pattern 46a～46c and above form silicon oxide film between the barrier metal film 45, then, to silicon oxide film portrayal pattern, and used as being hard mask.Also can adopt hard mask in the following embodiments.
Then; if remove corrosion-resisting pattern 46a, 46b, 46c; then shown in Fig. 5 I, remaining in the top barrier metal film 45 on capacitor lower electrode 39a, the dielectric film 41, leading electrolemma 44, below barrier metal film 43 and conductivity diaphragm 42 becomes electric capacity upper electrode 47.Thereby, constitute MIM capacity cell Q by electric capacity upper electrode 47, dielectric film 41 and capacitor lower electrode 39a 3
In addition, the zone beyond the electric capacity upper electrode 39a will remain in wiring 48a, the 48b etc. that top barrier metal film 45, leading electrolemma 44, below barrier metal film 43 on through hole plug-in unit 38c, the 38d of ground floor is used as the second layer.
MIM capacity cell Q 3, wiring 48a, 48b etc. for example be formed flat shape as shown in Figure 6.
Then, shown in Fig. 5 J, by the CVD method, in capacitor Q 3, form the 4th silicon oxide film 50, the 3rd silicon nitride film 51, the 5th silicon oxide film 52 successively on wiring 48a, 48b and the 3rd silicon oxide film 37.In addition, after forming the 4th silicon oxide film 50, planarization is carried out on its surface by the CMP method.
Then, by using the photoetching process of corrosion-resisting pattern, to the 5th silicon oxide film 52, the 3rd silicon nitride film 51 and the 4th silicon oxide film 50 portrayal patterns, thereby at MIM capacitor Q 3Electric capacity upper electrode 47 on and wiring form through hole 50a～50c respectively on 48a, the 48b.
Then, by photoetching process,, form a part and the overlapping wiring groove 52a～52c of through hole 50a～50c thus to the 5th silicon oxide film 52 portrayal patterns.Under these circumstances, in the etching of the 5th silicon oxide film 52, for example adopting and having used CF is the method for plasma etching of gas, still because the 3rd silicon nitride film 51 is brought into play the function of etching block films, therefore controls the degree of depth of wiring groove 52a～52c easily.Then, by adjusting gaseous species or condition of plasma, remove the 3rd silicon nitride film 51 that exposes from wiring groove 52a～52c selectively, thereby wiring groove 52a～52c is deepened.
Then, by sputter, forming thickness in wiring groove 52a～52c successively is the TaN film of 30nm～50nm and the copper seed membrane that thickness is 100nm, and then, by electroplating, fill copper film therein.In addition, by the CMP method, remove the TaN film, copper seed membrane and the copper film that are formed on the 5th silicon oxide film 52 upper surfaces.
Thus, wiring groove 52a～52c and below through hole 50a～50c in form the wiring and the conductive membrane 53～55 of bimetal mosaic structure.
Then, though not shown, form multilayer wirings such as silicon oxide film, copper wiring and conducting portion.
For MIM capacitor Q with aforesaid structure 3Dielectric film 41, portray pattern with the conductivity diaphragm 42 that forms above it, therefore during the clean after removing corrosion-resisting pattern 46a or carrying out, conductivity diaphragm 42 prevents MIM capacitor Q 3Dielectric film 41 directly contact with plasma, ion or solution.
Relative therewith, if the oxygen plasma that generates in order to carry out ashing treatment shines directly into dielectric film 41, can make dielectric film 41 impaired, therefore might cause the thickness change of dielectric film 41, and withstand voltage diminishing.
But; in the present embodiment; shown in Fig. 5 F; form such structure; promptly; because the top of dielectric film 41 is covered by conductivity diaphragm 42, therefore the irradiation that is difficult to take place owing to oxygen plasma, ion makes its impaired situation, thereby is difficult to take place thickness change and the degradation of breakdown voltage that its damage causes.
In addition, for after operation in also remove etch residue etc., supply with the solution of hydrofluoric acid or ammonium fluoride to the surface of the 3rd silicon oxide film 37.Under these circumstances, as shown in Figure 7, the outer peripheral edges of the dielectric film 41 that is covered by conductivity diaphragm 42 are not by the solution etching, thereby dwindle a little, but can not cause the thickness change on dielectric film 41.
At dwindling of dielectric film 41, consider wet processed, as long as, just do not have obstacle in advance to the broader pattern of dielectric film 41 portrayals.But after carrying out wet processed, dielectric film 41 needs to cover the outer peripheral edges of capacitor lower electrode 39a and it is exposed, and therefore, preferably controls the indentation amount of the circumference of the caused dielectric film 41 of wet processed.
Thus, the dielectric film 41 that prevents to have formed by present embodiment pattern is impaired, suppresses the membranous deterioration of dielectric film 41.
In addition, when below when forming the Ti film below the barrier metal film 43, constitute conductivity diaphragm 42 by the TiN film, prevent that thus Ti is to dielectric film 41 diffusions.
The some of Ti film is to 37 diffusions of the 3rd silicon oxide film, thereby the raising close property on the other hand, if be diffused into dielectric film 41, then can cause MIM capacity cell Q 3Withstand voltage decline, produce fixed charge.But, in the present embodiment, dielectric film 41 and below be formed with the conductivity diaphragm 42 that constitutes by TiN between the barrier metal film 43, prevent that therefore Ti to dielectric film 31 diffusions, preventing the deterioration of capacitance characteristic.
Yet, the MIM capacity cell Q that constitutes on dielectric film 41, forming conductivity diaphragm 42 3The MIM capacity cell of the reference that constitutes with do not form conductivity diaphragm 42 on dielectric film 41 has been investigated charge capacity and leakage current respectively, and its result has obtained the result shown in Fig. 8 A, Fig. 8 B.Hence one can see that, by conductivity diaphragm 42 protection dielectric films 41, can suppress the deterioration of capacity cell characteristic thus.
At the MIM capacity cell of reference, can further improve the capacity cell characteristic by adjusting formation condition.
In addition, the test of using in Fig. 8 A, Fig. 8 B has following structure with element: be formed with a plurality of MIM capacity cells in the tetragonal zone of about 2mm * 2mm, wherein, the structure of this MIM capacity cell is, the capacitor lower electrode size is made as about 90 μ m * 90 μ m, and then the distance between capacitor lower electrode periphery and the dielectric film periphery is made as 0.5 μ m.
(the 4th execution mode)
Fig. 9 A～Fig. 9 G is the profile of formation operation of the semiconductor device of expression four embodiment of the invention.In addition, in Fig. 9 A～Fig. 9 G, represent identical key element with the Reference numeral that Fig. 5 A～Fig. 5 J is identical.
In Fig. 9 A, similarly on semiconductor substrate 31, be formed with first silicon oxide film 32, first silicon nitride film 33 and second silicon oxide film 34 successively with the 3rd execution mode.And, in second silicon oxide film 34 and first silicon nitride film 33, be formed with the copper wiring 35a～35d of ground floor.
In addition, on second silicon oxide film 34 and copper wiring 35a～35d, be formed with second silicon nitride film 36 and the 3rd silicon oxide film 37 successively.And then, on the 3rd silicon oxide film 37 and second silicon nitride film 36, be formed with the through hole plug-in unit 38a～38d of the ground floor that is connected with the copper wiring 35a～35d of ground floor.
Under such state, for example,, on the 3rd silicon oxide film 37 and through hole plug-in unit 38a～38d, form the TiN film as lower electrode film 39 by sputter, wherein, the thickness of this TiN film is 50nm～100nm.Then, by the method identical,, thereby form capacitor lower electrode 39a to lower electrode film 39 portrayal patterns with the 3rd execution mode.
Yet, in the present embodiment, except the through hole plug-in unit 38a, the 38b that are positioned at capacitor lower electrode 39a below, also individually residual lower electrode film 39 on conducting portion 38c, 38d, and with them as conductivity dish 39b, 39c.Thus, prevent the through hole plug-in unit 38c, the 38d that constitute by W after operation in impaired.
Then, shown in Fig. 9 B, form dielectric film 57 on capacitor lower electrode 39a, conductivity dish 39b, 29c and the 3rd silicon oxide film 37, its thickness for example is 100nm～150nm.
Can be with the silicon oxide film that for example uses the reacting gas that contains silane or TEOS, form by plasma CVD method as dielectric film 57, the silicon nitride film that also use can be contained the reacting gas of silane and ammonia, forms by the CVD method etc. is applied to dielectric film 57.
Then, shown in Fig. 9 C,, dielectric film 57 is carried out anisotropic etching, makes it remain in capacitor lower electrode 39a, conductivity dish 39b thus by sputter, RIE method etc., on the side of 29c as the sidewall 57s of insulating properties.Under these circumstances, the thickness of sidewall 57s makes the face that exposes of sidewall 57s become the inclined-plane from the side of capacitor lower electrode 39a, conductivity dish 39b, 29c to the outside steadily and attenuation continuously thus.
Then, shown in Fig. 9 D,, form dielectric film 41, conductivity protection 42 on 29c, insulating properties sidewall 57s and the 3rd silicon oxide film 37 successively at capacitor lower electrode 39a, conductivity dish 39b.Under these circumstances, by using the plasma CVD method of TEOS, form thickness and be about the silicon oxide film of 40nm as dielectric film 41.In addition, by sputter, form thickness and be about the TiN film of 30nm as conductivity diaphragm 42.
At the sidepiece of capacitor lower electrode 39a, dielectric film 41 and conductivity diaphragm 42 are formed on to have on the sidewall 57s that exposes the inclined-plane stably.The thickness of dielectric film 41, conductivity protection 42 is roughly even.
Then, on conductivity diaphragm 42, apply photoresist, and make its exposure, development, thereby form the corrosion-resisting pattern 58 that capacitor dielectric is used at capacitor lower electrode 39a with from the zone that its periphery is exposed.Then, corrosion-resisting pattern 58 is used as mask, conductivity diaphragm 42 and dielectric film 41 are carried out etching.
Thus,, thereby form the upper surface of covering capacitor lower electrode 39a and the shape of side, and then to conductivity diaphragm 42 portrayal patterns, thereby formation covers the shape of the upper surface of dielectric film 41 to dielectric film 41 portrayal patterns.In the etching of conductivity diaphragm 42, for example using chlorine is gas, and in the etching of dielectric film 41, for example using fluorine is gas.
Under these circumstances, etching condition is set at: on the sidewall 57s of electrode disk 39b, 39c sidepiece, do not stay conductivity diaphragm 42 at least.
Then, shown in Fig. 9 E, after being carried out etching, dielectric film 41 and conductivity diaphragm 42 remove corrosion-resisting pattern 58.As its removal method, for example, use ashing based on oxygen plasma.Under these circumstances, prevent the influence of plasma by conductivity diaphragm 42 to dielectric film 41.In addition; after carrying out ashing, when using hydrofluoric acid etc. to clean the 3rd silicon oxide film 37 surperficial, side etching (side etching) can enter into dielectric film 41 a little; but because 42 protections of conductivity diaphragm, so the thickness of dielectric film 41 can not reduce.
Then, shown in Fig. 9 F, by the method identical with the 3rd execution mode, below forming on conductivity diaphragm 42, the 3rd silicon oxide film 37 and the conductivity dish 39c, 389 barrier metal film 43, leading electrolemma 44 and above barrier metal film 45.
Then, with the 3rd execution mode similarly, form corrosion-resisting pattern (not shown) up on the barrier metal film 45, then, corrosion-resisting pattern is used as mask, top barrier metal film 45, leading electrolemma 44 and below barrier metal film 43 are carried out etching.
Then, if remove corrosion-resisting pattern, then shown in Fig. 9 G, remain in the top of capacitor lower electrode 39a, dielectric film 41 and the top barrier metal film 45 of periphery thereof, leading electrolemma 44, below barrier metal film 43 becomes electric capacity upper electrode 47.In addition, the conductivity diaphragm 42 on the dielectric film 41 becomes the part of electric capacity upper electrode 47.
Then, constitute MIM capacity cell Q by electric capacity upper electrode 47, dielectric film 41 and capacitor lower electrode 39a 4
In addition, the zone beyond electric capacity upper electrode 39a will remain in conductivity dish 39c, and the top barrier metal film 45 on the 39d, leading electrolemma 44, below barrier metal film 43 are used as wiring 48a, the 48b etc. of the second layer.
MIM capacity cell Q 4, wiring 48a, 48b etc. the plane for example roughly the same with shape shown in Figure 6.
Then, though not special diagram similarly forms the 4th silicon oxide film, the 3rd silicon nitride film etc. with the 3rd execution mode.By the CVD method, form the 51, the 5th silicon oxide film 52 successively.
At above MIM capacity cell Q 4In, on capacitor lower electrode 39a and conductivity dish 39b, 39c side separately, be formed with insulating properties sidewall 57s, the thickness of this insulating properties sidewall 57s slowly changes in the outside, and therefore, the precipitous ladder that can eliminate on capacitor lower electrode 39a and conductivity dish 39b, each side of 39 is poor.
Thus; even with respect to real estate; form dielectric film 41 and conductivity diaphragm 42 under the many condition of the accumulating amount of vertical composition, also make the dielectric film 41 on the side of capacitor lower electrode 39a and conductivity dish 39b, 39c and the uniform film thickness of conductivity diaphragm 42.
In addition,, on sidewall 57s, be formed with dielectric film 41 and conductivity diaphragm 42 in capacitor lower electrode 39a and conductivity dish 39b, 39 side, and its uniform film thickness, can be with MIM capacity cell Q 4The anti-possible trouble that terminates in of deterioration in characteristics.And the sidewall 57s of insulating properties also has the function that the sidepiece of the sidepiece that makes capacitor lower electrode 39a and electric capacity upper electrode 47 separates, and therefore can suppress leakage current and flow through these electrodes 39a, 47 circumference.
Relative therewith; under the precipitous situation of the ladder difference of capacitor lower electrode 39a sidepiece; if under with respect to the many conditions of the accumulating amount of the vertical composition of real estate, form film; then cover relatively poorly at sidewall; cause dielectric film 41 and conductivity diaphragm 42 in the local attenuation in the corner of ladder difference; thereby cause on its part, in dielectric film 41, flowing through leakage current easily, can not obtain MIM capacity cell Q 4The capacity cell characteristic that requires.
And then, same with the 3rd execution mode, for MIM capacitor Q 4Dielectric film 41; portray pattern continuously with the conductivity diaphragm 42 that forms above it; therefore prevent that dielectric film 41 from directly contacting with plasma, ion or solution when removing corrosion-resisting pattern 46a or carry out thereafter clean; help to improve the capacity cell characteristic; wherein, above-mentioned corrosion-resisting pattern 46a is portrayal corrosion-resisting pattern 46a as mask during pattern.
Yet, when thereby lower electrode film 39 portrayal patterns are formed capacitor lower electrode 39a and conductivity dish 39b, 39c, if carry out excessive erosion, then shown in Figure 10 A, on the 3rd silicon oxide film 37, the zone beyond capacitor lower electrode 39a and conductivity dish 39b, 39c forms recess 37u.
Recess 37u makes the ladder difference on capacitor lower electrode 39a and conductivity dish 39b, the 39c sidepiece become big, more needs to improve ladder and covers (step coverage).
Therefore, shown in Figure 10 B, on capacitor lower electrode 39a, conductivity dish 39b, 39c and recess 37u, form thick dielectric film 57, and in vertical direction it is carried out anisotropic etching, thereby form sidewall 57s.
Thus, shown in Figure 10 C,, also can make the thickness of dielectric film 41 and conductivity diaphragm 42 roughly even by sidewall 57s even become big owing to the reason beyond the thickness of capacitor lower electrode 39a and conductivity dish 39b, 39c causes its ladder difference on every side.
(the 5th execution mode)
Figure 11 A～Figure 11 H is the profile of formation operation of the semiconductor device of expression fifth embodiment of the invention.In addition, in Figure 11 A～Figure 11 H, represent identical key element with the Reference numeral that Fig. 5 A～Fig. 5 J is identical.
In Figure 11 A, same with the 3rd execution mode, on semiconductor substrate 31, be formed with first silicon oxide film 32, first silicon nitride film 33 and second silicon oxide film 34 successively.And, in second silicon oxide film 34 and first silicon nitride film 33, be formed with the copper wiring 35a～35d of ground floor.
In addition, on second silicon oxide film 34 and copper wiring 35a～35d, be formed with second silicon nitride film 36 and the 3rd silicon oxide film 37 successively.And then, on the 3rd silicon oxide film 37 and second silicon nitride film 36, be formed with the through hole plug-in unit 38a～38d of the ground floor that is connected with the copper wiring 35a～35d of ground floor.
Under such state, by sputter, on the 3rd silicon oxide film 37 and through hole plug-in unit 38a～38d, form a TiN film 59a and W film 59b successively as the lower electrode film, wherein, the thickness of the one TiN film 59a for example is 30nm～50nm, and the thickness of W film 59b for example is 150nm～200nm.
And then, on W film 59b, apply photoresist, and make its exposure, development, thereby formation has the corrosion-resisting pattern 60 that the capacitor lower electrode of the flat shape of capacitor lower electrode is used.
Then, corrosion-resisting pattern 60 being used as mask, is the RIE method of gas by using chlorine for example, and a TiN film 59a and a W film 59b are carried out etching.Then, shown in Figure 11 B, will remove residual TiN film 59a in corrosion-resisting pattern 60 backs and the 2nd W film 59b as capacitor lower electrode 59.
Then, shown in Figure 11 C, by sputter, on capacitor lower electrode 59 and the 3rd silicon oxide film 37, form the 2nd TiN film 60a and the 2nd W film 60b successively as conducting film, wherein, the thickness of the 2nd TiN film 60a for example is 30nm～50nm, and the thickness of the 2nd W film 60b for example is 150nm～200nm.
Then, shown in Figure 11 D,, the 2nd TiN film 60a and the 2nd W film 60b are carried out anisotropic etching, thereby make it as the sidewall 60 of conductivity and residual, constitute the part of capacitor lower electrode 59 by sputter, RIE method etc.Under these circumstances, the film thickness distribution of sidewall 60 changes laterally reposefully from capacitor lower electrode 59 sides, and therefore making it expose face becomes the inclined-plane.In addition, conductivity sidewall 60 constitutes the part of capacitor lower electrode 59.
In addition, the constituent material of capacitor lower electrode 59 and sidewall 60 is not limited only to TiN, W, also can use its metal or metallic compound in addition.In addition, capacitor lower electrode 59 and sidewall 60 are not limited only to two-layer structure, also can be the above sandwich constructions of single layer structure or 3 films.
Then, shown in Figure 11 E, on capacitor lower electrode 59, conductivity sidewall 60 and the 3rd silicon oxide film 37, form dielectric film 41, conductivity diaphragm 42 successively.Under these circumstances, by using the plasma CVD method of TEOS, form thickness and be about the silicon oxide film of 40nm as dielectric film 41.In addition, form thickness by sputter and be about the TiN film of 30nm as conductivity diaphragm 42.
The dielectric film 41 of capacitor lower electrode 59 sidepieces and conductivity diaphragm 42 are formed on the sidewall 60 with inclined-plane stably, so their thickness is roughly even on whole base plate.
Then, same with the 3rd execution mode, on conductivity diaphragm 42, apply photoresist, and make its exposure, development, thereby form the corrosion-resisting pattern 61 that capacitor dielectric is used in capacitor lower electrode 59 with from the zone that its periphery is exposed.Then, corrosion-resisting pattern 51 is used as mask, conductivity diaphragm 42 and dielectric film 41 are carried out etching.
Thus, with the upper surface of covering capacitor lower electrode 59 and the shape of side, to dielectric film 41 portrayal patterns, and then, to cover the shape of dielectric film 41 upper surfaces, to conductivity diaphragm 42 portrayal patterns.In the etching of conductivity diaphragm 42, for example using chlorine is gas, and in the etching of dielectric film 41, for example using fluorine is gas.
Then, shown in Figure 11 F, after being carried out etching, dielectric film 41 and conductivity diaphragm 42 remove corrosion-resisting pattern 61.As its removal method, for example, use ashing based on oxygen plasma.Under these circumstances, prevent the influence of plasma by conductivity diaphragm 42 to dielectric film 41.In addition, after carrying out ashing, when cleaning the 3rd silicon oxide film 37 surfaces such as use hydrofluoric acid, side etching can enter into dielectric film 41 a little, but owing to conductivity diaphragm 42 is protected, so the thickness of dielectric film 41 can not reduce.
Then, shown in Figure 11 G, by the method identical with the 3rd execution mode, below forming on conductivity diaphragm 42, the 3rd silicon oxide film 37 and conductivity dish 39b, the 39c barrier metal film 43, leading electrolemma 44 and above barrier metal film 45.
Then, with the 3rd execution mode similarly, form corrosion-resisting pattern (not shown) up on the barrier metal film 45, then, corrosion-resisting pattern is used as mask, top barrier metal film 45, leading electrolemma 44 and below barrier metal film 43 are carried out etching.
Then, if remove corrosion-resisting pattern, then shown in Figure 11 H, remaining in the top barrier metal film 45 of capacitor lower electrode 59 and dielectric film 41 tops, leading electrolemma 44, below barrier metal film 43 becomes electric capacity upper electrode 47.In addition, the conductivity diaphragm 42 on the dielectric film 41 becomes the part of electric capacity upper electrode 47.
Then, constitute MIM capacity cell Q by electric capacity upper electrode 47, dielectric film 41 and capacitor lower electrode 59 5
In addition, the zone beyond electric capacity upper electrode 39a will remain in wiring 48a, the 48b etc. that are used as the second layer through the top barrier metal film 45 on the path of conducting portion 38c, 38d, leading electrolemma 44, below barrier metal film 43.
MIM capacity cell Q 5, wiring 48a, 48b etc. the plane for example with MIM capacity cell Q shown in Figure 6 3Shape roughly the same.
Then, though not special diagram similarly forms the 4th silicon oxide film, the 3rd silicon nitride film etc. with the 3rd execution mode.By the CVD method, form the 51, the 5th silicon oxide film 52 successively.
At above MIM capacity cell Q 5In, the sidepiece of capacitor lower electrode 59 is made of conductivity sidewall 60, and therefore, the precipitous ladder that can eliminate on the capacitor lower electrode 39a that is used to form dielectric film 41 and conductivity dish 39b, each side of 39 is poor.
Thus,, form dielectric film 41 and conductivity diaphragm 42 under the many condition of the accumulating amount of vertical composition, also make the dielectric film 41 of sidewall of capacitor lower electrode 59 and the uniform film thickness of conductivity diaphragm 42 even with respect to real estate.
Thus, on the side of capacitor lower electrode 59, the uniform film thickness of dielectric film 41 and conductivity diaphragm 42, thus can be with MIM capacity cell Q 5The anti-possible trouble that terminates in of deterioration in characteristics.
In addition, same with the 3rd execution mode, for MIM capacitor Q 5Dielectric film 41; portray pattern continuously with the conductivity diaphragm 42 that forms above it; therefore during the clean after removing corrosion-resisting pattern 61 or carrying out; prevent that plasma, ion or solution from making dielectric film 41 deteriorations; wherein, above-mentioned corrosion-resisting pattern 61 becomes mask when the portrayal pattern.
(the 6th execution mode)
Figure 12 is the vertical view of the semiconductor device of expression sixth embodiment of the invention.In addition, Figure 13 A～Figure 13 J is the profile of expression from the formation operation of the semiconductor device of the sixth embodiment of the invention of the I-I line observation of Figure 12; Figure 14 A～Figure 14 H is the profile from the formation operation of the semiconductor device of the sixth embodiment of the invention of the II-II line observation of Figure 12.In addition, in Figure 12, Figure 13 A～U13J, Figure 14 A～Figure 14 H, represent identical key element with the Reference numeral that Fig. 5 A～Fig. 5 J is identical.
In Figure 12, semiconductor device has capacity cell zone A, wiring area B, fuse zone C, moisture resistance ring region D and other zones, on these regional A～D, according to the operation formation MIM capacity cell Q of following explanation 6, wiring 71, blow out fuse (molten disconnected Off エ one ズ) 67, moisture resistance ring 80.In addition, being shaped as of moisture resistance ring 80: the outer peripheral edges along the semiconductor device of shaped like chips are surrounded semiconductor circuit.
Below, and form the structure that operation together illustrates semiconductor device.
At first, same with the 3rd execution mode in Figure 13 A, on semiconductor substrate 31, be formed with first silicon oxide film 32, first silicon nitride film 33 and second silicon oxide film 34 successively.And, in second silicon oxide film 34 and first silicon nitride film 33, in capacity cell zone A, wiring area B, be formed with copper wiring 35a, 35c respectively.
In moisture resistance ring region D, on first silicon oxide film 32, be formed with the first ring groove 32g of the degree of depth that arrives semiconductor substrate 31 inside, and then, in second silicon oxide film 34 and first silicon nitride film 33, be formed with first ring overlapping and broad second encircle and use groove 34g than it with groove 32g.First, second ring is formed ring-type with groove 32g, 34g, to surround semiconductor circuit.
In encircling with groove 32g, 34g, first, second is formed with first ring 63 of the bimetal mosaic structure that forms simultaneously with copper wiring 35a, 35c.First ring 63 has the stepped construction of TaN barrier film and copper film.
In addition, in the fuse zone C, shown in Figure 14 A, in first silicon oxide film 32, be formed with two first crackle block film groove 32e with the degree of depth that arrives semiconductor substrate 31 inside with the interval about 4 μ m.And, in second silicon oxide film 34 and first silicon nitride film 33, be formed with the first crackle block film overlapping and than its second broad crackle block film groove 34e with groove 32e.
Be formed with the first crackle block film 64 of the bimetal mosaic structure that forms simultaneously with copper wiring 35a, 35c in groove 32e, 34e at first, second crackle block film.The first crackle block film 64 has the stepped construction of TaN barrier film and copper film.
And then, by the CVD method, on first ring, 63, the first crackle block film 64, copper wiring 35a, 35c and second silicon oxide film 34, be formed with second silicon nitride film 36 and the 3rd silicon oxide film 37 successively.
Under such state, shown in Figure 13 B, pass through photoetching process, to the 3rd silicon oxide film 37 and second silicon nitride film, 36 portrayal patterns, thereby on a part that is positioned at copper wiring 35a, 35c on capacity cell zone A and the wiring area B, form through hole 37a, 37c, and, be positioned at formation the 3rd ring groove 37g on the ring of first on the moisture resistance ring region D 63.
Meanwhile, as shown in Figure 14B,, on the first crackle block film 64, form, and the zone between two the 3rd crackle block film groove 37e forms fuse groove 37f than its 3rd broad crackle block film groove 37e in the fuse zone C.Fuse has the length of 1.5 μ m～50 μ m and the width of about 0.5 μ m with groove 37f.
Then, respectively by sputter and plasma CVD method, encircle with groove 37g and fuse formation TiN barrier film and W film among the groove 37f with groove 37e, the 3rd in through hole 37a, 37c, the prevention of the 3rd crackle.
Then, by the CMP method, remove barrier film, W film on the 3rd silicon oxide film 37.Thus, stop with groove 37e and fuse with barrier film, W film among the groove 37f with groove 37g, the 3rd crackle remaining in through hole 37a, 37c, the 3rd ring, being used separately as is through hole plug-in unit 38a, 38c, second ring 65, second crackle block film 66 and the fuse 67.In addition, the central authorities at fuse 67 are formed with the caused recess of CMP.This form depends on employed fuse widths.Has the tendency that further produces recess when width conforms to.
Then, shown in Figure 13 C, Figure 14 C,, on the 3rd silicon oxide film 37, be formed for covering the lower electrode film 39 of through hole plug-in unit 38a, 38c, second ring 65, the second crackle block film 66 and fuse 67 by sputter.
And then, on lower electrode film 39, apply photoresist, and make its exposure, development, thus, be formed for covering the corrosion-resisting pattern 69a that the lower electrode in the zone that comprises through hole plug-in unit 38a is used at capacity cell zone A, be formed for covering the corrosion-resisting pattern 68c of the dish usefulness of through hole plug-in unit 38c in the wiring area B, be formed for covering respectively the corrosion-resisting pattern 68e that corrosion-resisting pattern 68f that the fuse of the fuse 67 and the second crackle block film 66 uses and crackle block film are used in the fuse zone C, be formed for covering the corrosion-resisting pattern 68g of the ring usefulness of second ring 65 in the ring region D.
Then, corrosion-resisting pattern 68a, 68c, 68e, 68f, 68g as mask, by sputter, RIE etc., are carried out etching to lower electrode film 39.Then, remove corrosion-resisting pattern 68a, 68c, 68e, 68f, 68g.
Shown in Figure 13 D, Figure 14 D; form figuratum lower electrode film 67 thus and make the capacitor lower electrode 39a that is connected with through hole plug-in unit 38a at capacity cell zone A; make the conductivity dish 39c that is used for individually covering through hole plug-in unit 38c in the wiring area B; make diaphragm 39f, the 39e that is used to cover the fuse 67 and the second crackle block film 66 in the fuse zone C; and then, make the conductivity dish 39g that is used to cover second ring 65 in moisture resistance ring region D.
During to lower electrode film 39 portrayal patterns, carry out etching superfluously, form recess 37u on the surface of the 3rd silicon oxide film 37 that exposes from corrosion-resisting pattern 68a, 68c, 68e, 68f, 68g.In order to prevent leakage current, carry out the etching of surplus by remove the electric conducting material that is used to constitute lower electrode film 39 from the 3rd silicon oxide film 37 surface.
Then, shown in Figure 13 E, Figure 14 E, on capacitor lower electrode 39a, conductivity dish 39f etc., form dielectric film 41, conductivity diaphragm 42 successively.In addition, for example same with the 3rd execution mode, constitute dielectric film 41, conductivity diaphragm 42 by silicon oxide film, TiN film respectively.
Then, on conductivity diaphragm 42, apply photoresist, and make its exposure, development, thereby form the corrosion-resisting pattern 43 that capacitor dielectric is used at capacitor lower electrode 39a with from the zone that its periphery is exposed.
Then, corrosion-resisting pattern 43 is used as mask, for example,, conductivity diaphragm 42 and dielectric film 41 is carried out etching by sputter, RIE etc.Conductivity diaphragm 42 and dielectric film 41 are carried out excessive erosion, thereby the constituent material that prevents conductivity diaphragm 42 remains on the surface of the 3rd silicon oxide film 37.By this excessive erosion, the recess 37u that is formed on the 3rd silicon oxide film 37 is deepened.
Then, shown in Figure 13 F, Figure 14 F, for example,, remove corrosion-resisting pattern 43 by ashing based on oxygen plasma.Under these circumstances, protect dielectric film 41 by conductivity diaphragm 42 from plasma, ion or solution.
Then, shown in Figure 13 G, Figure 14 G, below forming successively on conductivity diaphragm 42, the 3rd silicon oxide film 37 and through hole plug-in unit 38c, the 38d barrier metal film 43, leading electrolemma 44 and above barrier metal film 45.In addition, can form Ti and be close to the basilar memebrane that film is used as below barrier metal film 43.
And then, apply photoresist on the barrier metal film 45 up, and make its exposure, development, thereby form the corrosion-resisting pattern 70g that the corrosion-resisting pattern 70c of corrosion-resisting pattern 70a that upper electrode uses, wiring usefulness, corrosion-resisting pattern 70f that fuse electrodes is used, corrosion-resisting pattern 70e that the crackle block film is used and protective ring are used.
The corrosion-resisting pattern 70a that upper electrode is used is overlapping and have a size that extends to from the zone that its periphery is exposed at capacity cell zone A and dielectric film 41 and conductivity diaphragm 42.In addition, in the wiring area B, the corrosion-resisting pattern 70c of wiring usefulness has the overlapping shape with through hole plug-in unit 38c.In the fuse zone C, the corrosion-resisting pattern 70f that fuse electrodes is used is formed on the two ends position overlapped with fuse 65, and in addition, the corrosion-resisting pattern 70e that the crackle block film is used is formed in the scope that covers the second crackle block film 66.And in moisture resistance ring region D, the corrosion-resisting pattern 70g that protective ring is used is formed the frame shape, with overlapping with the 3rd ring 39g.
Then, these corrosion-resisting patterns 70a, 70c, 70f, 70e, 70g are used as mask, below barrier metal film 43, leading electrolemma 44 and top barrier metal film 45 are carried out anisotropic etching by sputter, RIE etc.Then, remove corrosion-resisting pattern 70a, 70c, 70f, 70e, 70g.
Pattern by such below barrier metal film 43, leading electrolemma 44 and top barrier metal film 45 forms, shown in Figure 13 H, Figure 14 H, A forms electric capacity upper electrode 47 in the capacity cell zone, forms the wiring 71 that is connected with through hole plug-in unit 38c in the wiring area B across conductivity dish 39c.In addition,, form the electrode 72,73 that is connected with the two ends of blow out fuse 67, form the 3rd crackle block film 75 at its two ends in the fuse zone C.And then, form Fourth Ring 74 in moisture resistance ring region D.
Thus, at capacity cell zone A, constitute MIM capacity cell Q by electric capacity upper electrode 71, dielectric film 41 and capacitor lower electrode 39a 6In addition, same with the 3rd execution mode, at MIM capacity cell Q 6In, the conductivity diaphragm 42 on the dielectric film 41 constitutes the part of electric capacity upper electrode 41, and then, when formation Ti is close to film below electric capacity upper electrode 41, the function of the conductivity diaphragm 42 performance Ti nonproliferation films on the dielectric film 41.
In addition, constitute moisture resistance ring 80 by first to fourth ring 63,65,39g, 74.Moisture resistance ring 80 is formed the frame shape along the substrate periphery, has to prevent that moisture etc. from seeing through the interface of each film from the outside and the function of invading.And then, continuous stacked metal film or metallic compound film constitute first to fourth crackle block film 64,66,39e, 75 on film thickness direction, therefore, first to fourth crackle block film 64,66,39e, 75 have such function, promptly, when making blow out fuse 67 fusing by laser radiation, prevent to spread laterally at its crackle that produces on every side owing to its collision.
Yet, when to below barrier metal film 43, leading electrolemma 44, top barrier metal film 45 portrayal patterns, carry out superfluous etching, thereby prevent that metal material from remaining on the surface of the 3rd silicon oxide film 37.Thus, the part of the lip-deep recess 37u of the 3rd silicon oxide film 37 is further deepened.
In addition, by this superfluous etching,, make the diaphragm 39f attenuation of exposing from electrode 72,73 in the fuse zone C.Thus, when making blow out fuse 67 fusing by irradiating laser, diaphragm 39f can not stop its fusing.In addition, also can shown in Figure 13 I, remove the diaphragm 39f that exposes from electrode 72,73, more easily make the fusing of fuse 65 thus by etching.
Employed mask is not limited only to photoresist during in addition, to portrayal patterns such as leading electrolemmas 44.For example, also can photoresist and above corrosion-resisting pattern 70a, 70c, 70f, 70e, 70g are portrayed pattern as mask to silicon oxide film after forming silicon oxide film (not shown) on the barrier metal film 45, thereby they are used as hard mask.
Then, shown in Figure 13 J, Figure 14 H, form the 4th silicon oxide film 77, the 3rd silicon nitride film 78.
In the above-described embodiment, when lower electrode film 39 portrayal patterns are formed capacitor lower electrode 39a, to lower electrode film 39 portrayal patterns, it is shaped as and individually covers through hole plug-in unit 38c, blow out fuse 67, the second crackle block film and second ring 66 that is formed on wiring area B, fuse zone C and the moisture resistance ring region D simultaneously.At this, through hole plug-in unit 38c, blow out fuse 67, the second crackle block film and second ring 66 are made of TiN barrier film and W film.
According to soup and the treatment conditions used for surface removal etch residue, easily the W film is carried out etching sometimes from the 3rd silicon oxide film 37.But through hole plug-in unit 38c, blow out fuse 67, the second crackle block film and second ring 66 are in by the state of the pattern covers of lower electrode film 39, therefore can be not impaired because of the soup of handling.
Yet; if under the state of the W film that is used to constitute blow out fuse 67 with diaphragm 39f covering, wet processed is carried out on the surface to the 3rd silicon oxide film 37 in soup, then as shown in figure 15; blow out fuse 67 is by the solution etching, thereby its recess 67u is deepened easily.Its result envisions following situation,, above blow out fuse 67, forms emptying aperture 79 easily in the 4th silicon oxide film 77, the 3rd silicon nitride film 78 that is.By changing the thickness and the shape of top dielectric film, make fusing instability based on the blow out fuse 67 of laser.
Therefore, as present embodiment, cover the film reduction that blow out fuse 67 helps to prevent blow out fuse 67 with the metal film that constitutes capacitor lower electrode 39a.
More than Shuo Ming execution mode is a typical case; to those skilled in the art; the combination of the inscape of its each execution mode, its distortion and change are conspicuous; and; to those skilled in the art, the various distortion that can carry out above-mentioned execution mode under the situation of the invention scope that the scope that does not break away from principle of the present invention and ask for protection is put down in writing are conspicuous.

Claims (20)

1. semiconductor device is characterized in that having:
Semiconductor substrate,
Dielectric film, it is formed on the semiconductor substrate top,
Capacity cell, the electric capacity upper electrode that it has the capacitor lower electrode that is formed on the described dielectric film, the upper surface that is formed on described capacitor lower electrode and the dielectric film on the side, is made of first metal pattern of metal film, described metal film is formed on the described dielectric film and is broader than described capacitor lower electrode
Wiring, it is formed on the described dielectric film, is made of second metal pattern of described metal film.
2. semiconductor device according to claim 1 is characterized in that,
The outer peripheral edges of described electric capacity upper electrode are extended the outside of the outer peripheral edges that expand to described dielectric film.
3. semiconductor device according to claim 1 and 2 is characterized in that,
Have the conductivity diaphragm, this conductivity diaphragm is formed on the upper surface of described dielectric film, and, the lower surface engages of the upper surface of this conductivity diaphragm and side and described electric capacity upper electrode.
4. according to any described semiconductor device in the claim 1 to 3, it is characterized in that,
Have sidewall, this sidewall is formed on the side of described capacitor lower electrode, and this sidewall has low more more laterally continuously inclined-plane.
5. according to any described semiconductor device in the claim 1 to 4, it is characterized in that,
Have the conductivity plug-in unit, this conductivity plug-in unit is formed in the described dielectric film, and is connected with the lower surface of described capacitor lower electrode.
6. according to each described semiconductor device in the claim 1 to 5, it is characterized in that,
Described metal film has the lip-deep film of being close to that is formed on described dielectric film.
7. according to each described semiconductor device in the claim 1 to 6, it is characterized in that,
Side at described capacity cell, have second conductivity plug-in unit that is formed in the described dielectric film and the conductive pattern that covers the upper surface of the described second conductivity plug-in unit, this conductive pattern is made of the conducting film identical with the material that constitutes described capacitor lower electrode.
8. according to each described semiconductor device in the claim 1 to 7, it is characterized in that,
Side at described capacity cell, have the 3rd conductivity plug-in unit that is formed in the described dielectric film and from the 3rd metal pattern of described the 3rd conductivity plug-in unit of top covering, the 3rd metal pattern is made of the described metal film that is used to constitute described electric capacity upper electrode.
9. according to each described semiconductor device in the claim 1 to 8, it is characterized in that,
In the side of described capacity cell, have fuse that is formed in the described dielectric film and the protection pattern that covers at least a portion of described fuse, this protection pattern is made of the conducting film identical with the material that constitutes described capacitor lower electrode.
10. according to each described semiconductor device in the claim 1 to 9, it is characterized in that,
Have respectively in described dielectric film and its multiple layer metal pattern that forms continuously up and down, at least a pattern of the 4th metal pattern that the part of described multiple layer metal pattern comprises the pattern of the conducting film that is used for constituting described capacitor lower electrode and is used to constitute the described metal film of described electric capacity upper electrode.
11. the manufacture method of a semiconductor device is characterized in that, comprises following operation:
On the dielectric film on the semiconductor substrate, form the operation of first metal film,
To described first metal film portrayal pattern, thus the operation of formation capacitor lower electrode,
On the upper surface of described capacitor lower electrode and side and described dielectric film, form the operation of dielectric film,
To described dielectric film portrayal pattern, thus the operation of the electric capacity dielectric film of the shape of the described upper surface of the described capacitor lower electrode of formation covering and side,
On described electric capacity dielectric film and described dielectric film, form the operation of second metal film,
Described second metal film is portrayed pattern, thereby forms the operation of the electric capacity upper electrode of the upper surface that covers described electric capacity dielectric film at least,
To described second metal film portrayal pattern, thereby on described dielectric film, form the operation that connects up.
12. the manufacture method of semiconductor device according to claim 11 is characterized in that,
For described electric capacity dielectric film and described electric capacity upper electrode, use mask portrayal pattern with layer.
13. the manufacture method of semiconductor device according to claim 11 is characterized in that,
For described electric capacity upper electrode, use with described electric capacity dielectric film overlapping and broader mask to portray pattern than described electric capacity dielectric film.
14. the manufacture method according to each described semiconductor device in the claim 11 to 13 is characterized in that, comprises following operation:
Before to described electric capacity dielectric film portrayal pattern, on described dielectric film, form the operation of conductivity diaphragm,
Before forming described second metal film, to described conductivity diaphragm portrayal pattern, thereby with the operation of pattern portrayal for the shape of the upper surface of the described electric capacity dielectric film of covering.
15. the manufacture method of semiconductor device according to claim 14 is characterized in that,
Comprise following operation: etched operation is carried out on the surface to the described dielectric film that exposes from the described conductivity diaphragm of portrayal behind the pattern.
16. the manufacture method according to each described semiconductor device in the claim 11 to 15 is characterized in that, comprises following operation:
On described capacitor lower electrode and described dielectric film whole, form the operation of film,
Described film is carried out etching, thereby make it remain in the operation of the side of described capacitor lower electrode as sidewall.
17. the manufacture method according to each described semiconductor device in the claim 11 to 16 is characterized in that, comprises following operation:
In described dielectric film, form the operation of plug-in unit,
At least one metal film in described first metal film and described second metal film is portrayed pattern, thereby be formed for covering the operation of the metal pattern on the described plug-in unit.
18. the manufacture method according to each described semiconductor device in the claim 11 to 17 is characterized in that, comprises following operation:
In described dielectric film, form the operation of fuse,
Described first metal film is portrayed pattern, thereby be formed for covering the operation of the diaphragm on the described fuse.
19. the manufacture method of semiconductor device according to claim 18 is characterized in that, comprises following operation:
By being used for etchant, the described diaphragm on the described fuse is carried out etched operation to described second metal film portrayal pattern.
20. the manufacture method according to each described semiconductor device in the claim 11 to 19 is characterized in that, comprises following operation:
In described dielectric film, form the operation of the first moisture resistance ring of first metal,
To described first metal film portrayal pattern, thus the operation of the second moisture resistance ring that formation is connected with the described first moisture resistance ring,
To described second metal film portrayal pattern, thereby form operation with overlapping the 3rd moisture resistance ring of the described second moisture resistance ring.
CN2007800522103A 2007-03-20 2007-03-20 Semiconductor device and method of manufacturing the same Expired - Fee Related CN101636834B (en)

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US8642400B2 (en) 2014-02-04
US20120190154A1 (en) 2012-07-26

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