TWI782805B - Capacitor structure and manufacturing method thereof - Google Patents

Abstract

A capacitor structure including a substrate, a dielectric layer, and a capacitor is provided. The dielectric layer is located on the substrate and has an opening. The capacitor includes a first electrode, an insulating layer, and a second electrode. The first electrode is located in the opening and has a first void. The insulating layer is located in the first void and has a second void. The insulating layer has a first upper surface and a second upper surface. The first upper surface is higher than the second upper surface. The second electrode is located on a sidewall of the second void and exposes a portion of the second upper surface of the insulating layer.

Description

Capacitor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and its manufacturing method, and in particular to a capacitor structure and its manufacturing method.

A capacitor is a passive component widely used in electronic products. However, how to reduce the process complexity and manufacturing cost of capacitors is the goal of ongoing efforts. For example, Chinese Patent Publication No. CN1532911 and Chinese Patent No. CN102446915 disclose that the manufacturing process of the capacitor can be integrated with the manufacturing process of the interconnection structure.

The invention provides a capacitor structure and a manufacturing method thereof, which can reduce manufacturing process complexity and manufacturing cost.

The invention provides a capacitor structure, including a substrate, a dielectric layer and a capacitor. The dielectric layer is on the base and has an opening. The capacitor includes a first electrode, an insulating layer and a second electrode. The first electrode is located in the opening and has a first void. The insulating layer is located in the first cavity and has a second cavity. The insulating layer has a first upper surface and a second upper surface. The first upper surface is higher than the second upper surface. The second electrode is located on the sidewall of the second cavity and exposes a part of the second upper surface of the insulating layer.

According to an embodiment of the present invention, in the above capacitor structure, the first electrode may be conformally located on the sidewall and the bottom surface of the opening.

According to an embodiment of the present invention, in the above capacitor structure, the insulating layer can be conformally located on the sidewall and the bottom surface of the first cavity.

According to an embodiment of the present invention, in the above capacitor structure, the second electrode does not completely cover the second upper surface of the insulating layer.

According to an embodiment of the present invention, in the above capacitor structure, the top view shape of the second electrode may be a ring shape.

According to an embodiment of the present invention, in the above capacitor structure, the height of the top surface of the first electrode may be equal to or lower than the height of the first upper surface of the insulating layer.

According to an embodiment of the present invention, in the above capacitor structure, the height of the top surface of the second electrode may be equal to or lower than the height of the first upper surface of the insulating layer.

The invention provides a method for manufacturing a capacitor structure, which may include the following steps. Provide the base. A dielectric layer is formed on the substrate. The dielectric layer has openings. form a capacitor. A method of forming a capacitor includes the following steps. A first electrode is formed in the opening. The first electrode has a first cavity. An insulating layer is formed in the first cavity. The insulating layer has a second void. The insulating layer has a first upper surface and a second upper surface. The first upper surface is higher than the second upper surface. A second electrode is formed on the sidewall of the second cavity. The second electrode exposes part of the second upper surface of the insulating layer.

According to an embodiment of the present invention, in the manufacturing method of the above capacitor structure, the method for forming the second electrode may include the following steps. A layer of conductive material is conformally formed in the second cavity and over the dielectric layer, the first electrode, and the insulating layer. An etching process is performed on the conductive material layer to form the second electrode.

According to an embodiment of the present invention, the manufacturing method of the above capacitor structure may further include the following steps. An over etching process is performed on the second electrode, so that the top surface of the second electrode is lower than the first upper surface of the insulating layer.

Based on the above, in the capacitor structure and its manufacturing method proposed by the present invention, since the manufacturing process of the capacitor structure can be integrated with the manufacturing process of the interconnection structure, the entire manufacturing process does not need to add any photomask, thereby reducing the complexity of the manufacturing process. manufacturing cost. In addition, in the capacitor structure and manufacturing method proposed by the present invention, the top view shape of the capacitor can be elastically adjusted to increase the capacitance of the capacitor.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

1A-1J are cross-sectional views of the fabrication process of capacitor structures according to some embodiments of the present invention. Figure 2 is a top view of a capacitor and vias according to some embodiments of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. Next, a dielectric layer 102 is formed on the substrate 100 . The dielectric layer 102 has an opening OP1. In some embodiments, the dielectric layer 102 further has an opening OP2. For example, a part of the dielectric layer 102 can be removed by a lithography process and an etching process, so as to form the opening OP1 and the opening OP2. The material of the dielectric layer 102 is, for example, silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

In some embodiments, the dielectric layer 102 may have a conductive layer 104a and a conductive layer 104b. In some embodiments, the conductive layer 104a and the conductive layer 104b can be wires. The material of the conductive layer 104 a and the conductive layer 104 b is, for example, metal such as aluminum. In addition, the opening OP1 can expose the conductive layer 104a, and the opening OP2 can expose the conductive layer 104b.

Referring to FIG. 1B , a conductive material layer 106 may be conformally formed in the openings OP1 and OP2 and on the dielectric layer 102 . Since the width W1 of the opening OP1 is greater than twice the thickness T1 of the conductive material layer 106 , the conductive material layer 106 in the opening OP may have a void V1 . In addition, since the width W2 of the opening OP2 is less than or equal to twice the thickness T1 of the conductive material layer 106 , the conductive material layer 106 can fill the opening OP2 . The material of the conductive material layer 106 is metal such as tungsten, for example. The method for forming the conductive material layer 106 is, for example, chemical vapor deposition.

Referring to FIG. 1C , an insulating material layer 108 may be conformally formed on the conductive material layer 106 . Since the width W3 of the void V1 is greater than twice the thickness T2 of the insulating material layer 108 , the insulating material layer 108 located in the void V1 may have a void V2 . The material of the insulating material layer 108 is, for example, silicon oxide (eg, tetraethyl orthosilicate (TEOS) silicon oxide), silicon nitride or a combination thereof. The method for forming the insulating material layer 108 is, for example, chemical vapor deposition.

Referring to FIG. 1D , a chemical mechanical polishing process may be performed on the insulating material layer 108 and the conductive material layer 106 to form an insulating layer 108 a , an electrode 106 a and a via 106 b. Thereby, the electrode 106a having the void V1 may be formed in the opening OP1, the insulating layer 108a having the void V2 may be formed in the void V1, and the via hole 106b may be formed in the opening OP2. The electrode 106a can be electrically connected to the conductive layer 104a, and the via hole 106b can be electrically connected to the conductive layer 104b. The electrode 106a can be conformally located on the sidewall and the bottom surface of the opening OP1. The insulating layer 108a can be conformally located on the sidewall and the bottom surface of the cavity V1. In addition, the insulating layer 108 a has an upper surface S1 and an upper surface S2 . The upper surface S1 is higher than the upper surface S2.

Referring to FIG. 1E , a conductive material layer 110 may be conformally formed in the cavity V2 and on the dielectric layer 102 , the electrode 106 a and the insulating layer 108 a. Since the width W4 of the void V2 is greater than twice the thickness T3 of the conductive material layer 110 , the conductive material layer 110 will not fill the void V2 . The material of the conductive material layer 110 is metal such as aluminum, for example. The method for forming the conductive material layer 110 is, for example, physical vapor deposition.

Next, a patterned photoresist layer 112 can be formed on the conductive material layer 110 . The patterned photoresist layer 112 can be formed by a photolithography process.

Referring to FIG. 1F , the conductive material layer 110 can be etched by using the patterned photoresist layer 112 as a mask to form the electrode 110 a and the conductive layer 110 b. Thereby, the electrode 110a can be formed on the sidewall of the cavity V2, and the conductive layer 110b electrically connected to the through hole 106b can be formed. In some embodiments, the conductive layer 110b can be a wire. After performing the etching process on the conductive material layer 110 , part of the dielectric layer 102 , the top surface TS1 of the electrode 106 a , the upper surface S1 of the insulating layer 108 a and part of the upper surface S2 of the insulating layer 108 a may be exposed. In addition, the electrode 110a exposes part of the upper surface S2 of the insulating layer 108a. That is, the electrode 110a does not completely cover the upper surface S2 of the insulating layer 108a. In some embodiments, the height of the top surface TS1 of the electrode 106a may be equal to the height of the upper surface S1 of the insulating layer 108a, and the height of the top surface TS2 of the electrode 110a may be equal to the height of the upper surface S1 of the insulating layer 108a, but the present invention It is not limited to this. The above etching process is, for example, a dry etching process.

Through the above method, the capacitor 114 and the interconnection structure 116 can be formed. The capacitor 114 includes an electrode 106a, an insulating layer 108a and an electrode 110a. The insulating layer 108a is located between the electrode 106a and the electrode 110a. The interconnect structure 116 includes a conductive layer 104b, a via 106b, and a conductive layer 110b electrically connected to each other.

Referring to FIG. 1G , an over-etching process may be performed on the electrode 110 a so that the height of the top surface TS2 of the electrode 110 a is lower than the height of the upper surface S1 of the insulating layer 108 a. In addition, in the above over-etching process, part of the electrode 106a can be removed, so that the height of the top surface TS1 of the electrode 106a is lower than the height of the upper surface S1 of the insulating layer 108a. In this embodiment, the height of the top surface TS1 of the electrode 106a may be lower than the height of the upper surface S1 of the insulating layer 108a, and the height of the top surface TS2 of the electrode 110a may be lower than the height of the upper surface S1 of the insulating layer 108a, but The present invention is not limited thereto. In other embodiments, the step of FIG. 1G may not be performed, whereby the height of the top surface TS1 of the electrode 106a may be equal to the height of the upper surface S1 of the insulating layer 108a, and the height of the top surface TS2 of the electrode 110a may be equal to the height of the insulating layer 108a The height of the upper surface S1. After the above process is performed, as long as the electrode 106a and the electrode 110a can be insulated from each other by the insulating layer 108a, it falls within the scope of the present invention.

Referring to FIG. 1H , the patterned photoresist layer 112 can be removed. The removal method of the patterned photoresist layer 112 is, for example, dry stripping or wet stripping.

Next, a dielectric layer 118 covering the dielectric layer 102 , the capacitor 114 and the interconnect structure 116 may be formed. In addition, the dielectric layer 118 can fill up the void V2. The material of the dielectric layer 118 is, for example, silicon oxide. The dielectric layer 118 is formed by, for example, chemical vapor deposition.

A patterned photoresist layer 120 may then be formed on the dielectric layer 118 . The patterned photoresist layer 120 can be formed by a photolithography process.

Referring to FIG. 1I , the patterned photoresist layer 120 can be used as a mask to remove part of the dielectric layer 118 to form the opening OP3 and the opening OP4 . The opening OP3 exposes the electrode 110a. The opening OP4 exposes the conductive layer 110b. In addition, a portion of the dielectric layer 118 is located in the void V2. A method for removing part of the dielectric layer 118 is, for example, a dry etching method.

Next, the patterned photoresist layer 120 can be removed. The removal method of the patterned photoresist layer 120 is, for example, a dry stripping method or a wet stripping method.

Referring to FIG. 1J, a through hole 122a may be formed in the opening OP3, and a through hole 122b may be formed in the opening OP4. The through hole 122a can be electrically connected to the electrode 110a. In addition, the interconnection structure 116 may further include a through hole 122b. The via hole 122b can be electrically connected to the conductive layer 110b. The material of the through hole 122 a and the through hole 122 b is, for example, metal such as tungsten. The method of forming the through hole 122a and the through hole 122b is, for example, to first form a conductive material layer (not shown) that fills the opening OP3 and the opening OP4, and then remove the outside of the opening OP3 and the opening OP4 by a chemical polishing process. layer of conductive material.

Hereinafter, the capacitor structure 10 of the above-mentioned embodiment will be described with reference to FIG. 1J . In addition, although the method for forming the capacitor structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 1J and FIG. 2 , the capacitor structure 10 includes a substrate 100 , a dielectric layer 102 and a capacitor 114 . The dielectric layer 102 is located on the substrate 100 and has an opening OP1. The capacitor 114 includes an electrode 106a, an insulating layer 108a and an electrode 110a. The electrode 106a is located in the opening OP1 and has a void V1. The insulating layer 108a is located in the void V1 and has a void V2. The insulating layer 108a has an upper surface S1 and an upper surface S2. The upper surface S1 is higher than the upper surface S2. The electrode 110a is located on the sidewall of the cavity V2 and exposes part of the upper surface S2 of the insulating layer 108a. The top view shape of the electrode 110a may be a ring ( FIG. 2 ). In addition, the top view shape of the capacitor 114 can be elastically adjusted to increase the capacitance of the capacitor 114 .

In addition, for the rest of the components in the capacitor structure 10, reference may be made to the descriptions of the above-mentioned embodiments. On the other hand, the material, arrangement, formation method and function of each component in the capacitor structure 10 have been described in detail in the above-mentioned embodiments, and will not be further described here.

In summary, in the capacitor structure 10 and its manufacturing method of the above-mentioned embodiments, since the manufacturing process of the capacitor structure 10 can be integrated with the manufacturing process of the interconnection structure 116, the entire manufacturing process does not need to add any photomask, thereby reducing Process complexity and manufacturing cost. In addition, in the capacitor structure 10 and the manufacturing method thereof in the above embodiments, the top view shape of the capacitor 114 can be elastically adjusted to increase the capacitance of the capacitor 114 .

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Capacitor structure 100: base 102,118: dielectric layer 104a, 104b, 110b: conductive layer 106,110: layer of conductive material 106a, 110a: electrodes 106b, 122a, 122b: through holes 108: insulating material layer 108a: insulating layer 112,120: Patterned photoresist layer 114: Capacitor 116: Internal connection structure OP1~OP4: opening S1, S2: upper surface T1~T3: Thickness TS1, TS2: top surface V1, V2: Void W1~W4: Width

1A-1J are cross-sectional views of the fabrication process of capacitor structures according to some embodiments of the present invention. Figure 2 is a top view of a capacitor and vias according to some embodiments of the present invention.

10: Capacitor structure

100: base

102,118: dielectric layer

104a, 104b, 110b: conductive layer

106a, 110a: electrodes

106b, 122a, 122b: through holes

108a: insulating layer

114: Capacitor

116: Internal connection structure

OP1~OP4: opening

S1, S2: upper surface

TS1, TS2: top surface

V1, V2: Void

Claims (10)

A capacitor structure comprising: base; a dielectric layer on the substrate and having openings; and Capacitors, including: a first electrode located in the opening and having a first cavity; an insulating layer located in the first cavity and having a second cavity, wherein the insulating layer has a first upper surface and a second upper surface, and the first upper surface is higher than the second upper surface; and The second electrode is located on the sidewall of the second cavity and exposes part of the second upper surface of the insulating layer. The capacitor structure of claim 1, wherein the first electrode is conformally located on sidewalls and bottom surfaces of the opening. The capacitor structure of claim 1, wherein the insulating layer is conformally located on sidewalls and bottom surfaces of the first cavity. The capacitor structure of claim 1, wherein the second electrode does not completely cover the second upper surface of the insulating layer. The capacitor structure according to claim 1, wherein the top view shape of the second electrode comprises a ring shape. The capacitor structure according to claim 1, wherein the height of the top surface of the first electrode is equal to or lower than the height of the first upper surface of the insulating layer. The capacitor structure according to claim 1, wherein the height of the top surface of the second electrode is equal to or lower than the height of the first upper surface of the insulating layer. A method of manufacturing a capacitor structure, comprising: provide the basis; forming a dielectric layer on the substrate, wherein the dielectric layer has openings; and forming a capacitor, wherein the forming method of the capacitor comprises: forming a first electrode in the opening, wherein the first electrode has a first cavity; An insulating layer is formed in the first cavity, wherein the insulating layer has a second cavity, the insulating layer has a first upper surface and a second upper surface, and the first upper surface is higher than the second upper surface surface; and A second electrode is formed on a sidewall of the second cavity, wherein the second electrode exposes part of the second upper surface of the insulating layer. The method for manufacturing a capacitor structure as claimed in claim 8, wherein the method for forming the second electrode comprises: conformally forming a layer of conductive material in the second cavity and over the dielectric layer, the first electrode, and the insulating layer; and An etching process is performed on the conductive material layer to form the second electrode. The method for manufacturing a capacitor structure as described in Claim 9, further comprising: An overetching process is performed on the second electrode, so that the top surface of the second electrode is lower than the first upper surface of the insulating layer.

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