JP3962402B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a seal ring formed so as to surround the periphery of a chip region and a method for manufacturing the same.

  Generally, a semiconductor device is manufactured by arranging a large number of IC circuits composed of a plurality of elements and having a predetermined function on a semiconductor wafer such as silicon.

  Further, a large number of chip areas arranged on the wafer are separated from each other by a scribe area (scribe line) provided in a lattice shape. After a large number of chip regions are formed on a single wafer through a semiconductor manufacturing process, the wafer is diced into individual chips along the scribe region, thereby forming a semiconductor device.

  However, when the wafer is diced and divided into individual chips, the chip area around the scribe line is subjected to a mechanical shock, resulting in partial cracks and chipping in the dicing section of the separated chip, that is, the semiconductor device. There is a case.

  With respect to this problem, Patent Document 1 proposes a technique for preventing cracks from propagating through the chip region during dicing by providing a seal ring that is a ring-shaped defense wall around the chip region.

  FIG. 19 shows a cross-sectional structure of a semiconductor device having a conventional seal ring (in a state of being built in a wafer).

  As shown in FIG. 19, a chip region 2 partitioned by a scribe region 3 is provided on a substrate 1 made of a wafer. A laminated structure of a plurality of interlayer insulating films 5 to 10 is formed on the substrate 1. An active layer 20 constituting an element is formed in the chip region 2 of the substrate 1. Plugs (vias) 21 connected to the active layer 20 are formed in the interlayer insulating film 5, wirings 22 connected to the plugs 21 are formed in the interlayer insulating film 6, and wirings 22 are connected to the interlayer insulating film 7. A plug 23 to be connected is formed, a wiring 24 connected to the plug 23 is formed in the interlayer insulating film 8, a plug 25 connected to the wiring 24 is formed in the interlayer insulating film 9, and the interlayer insulating film 10 A wiring 26 connected to the plug 25 is formed.

  Further, as shown in FIG. 19, in the laminated structure of the plurality of interlayer insulating films 5 to 10 at the peripheral portion of the chip region 2, a seal ring 4 that penetrates the laminated structure and continuously surrounds the chip region 2 is formed. Has been. For example, as shown in Patent Document 1, the seal ring 4 is formed by alternately using a wiring formation mask and a via formation mask. Specifically, the seal ring 4 includes a conductive layer 30 formed on the substrate 1, a seal via 31 formed on the interlayer insulating film 5 and connected to the conductive layer 30, and a seal via 31 formed on the interlayer insulating film 6. A seal wiring 32 to be connected, a seal via 33 formed on the interlayer insulating film 7 and connected to the seal wiring 32, a seal wiring 34 formed on the interlayer insulating film 8 and connected to the seal via 33, and formed on the interlayer insulating film 9. The seal via 35 is connected to the seal wiring 34, and the seal wiring 36 is formed in the interlayer insulating film 10 and connected to the seal via 35. In the present application, a portion of the seal ring formed by the wiring formation mask is referred to as a seal wiring, and a portion of the seal ring formed by the via formation mask is referred to as a seal via.

  Further, as shown in FIG. 19, on the laminated structure of a plurality of interlayer insulating films 5 to 10 provided with wirings (22, 24, 26), vias (21, 23, 25) and a seal ring 4. Is provided with a passivation film 11. The passivation film 11 has an opening on the wiring 26, and a pad 27 connected to the wiring 26 is formed in the opening.

In the semiconductor device shown in Patent Document 1, the passivation film on the seal ring is also opened, thereby exposing the upper portion of the seal ring.
JP 2001-23937 A

  However, the conventional semiconductor device has a problem that the passivation film is peeled off due to an impact when dicing the wafer, or the impact propagates through the passivation film and is transmitted to the inside of the chip region.

  In addition, as in the semiconductor device disclosed in Patent Document 1, when a passivation film on the seal ring is opened and the upper part of the seal ring is exposed in the opening, moisture from the outside is removed from the seal ring. It is not possible to sufficiently prevent entry into the area surrounded by.

  By the way, in order to prevent an increase in inter-wiring capacitance accompanying the miniaturization of semiconductor elements and wirings connected thereto, that is, a reduction in the processing speed of a semiconductor device, an increase in inter-wiring capacitance is prevented by using a low dielectric constant interlayer insulating film Technology has been developed.

  However, since the mechanical strength of the low dielectric constant interlayer insulating film is generally low, the resistance to stress generated during dicing in the low dielectric constant interlayer insulating film is higher than that of an interlayer insulating film made of a conventionally used material. It is insufficient. As a result, the low dielectric constant interlayer insulating film is more susceptible to damage during dicing. Therefore, in such a semiconductor device using an interlayer insulating film having a low dielectric constant, even if a seal ring is provided around the chip region by alternately using a via forming mask and a wiring forming mask as in the prior art. The impact during dicing cannot be sufficiently prevented. Specifically, since a conventional seal ring formed by alternately using a via formation mask and a wiring formation mask is composed of a large number of parts, the joint between the parts (for example, a seal via and a seal wiring) More joints). Further, as the number of joints between parts increases, a part where the parts are not connected to each other is likely to occur. As a result, these joints (or parts where the parts are not connected to each other) serve as a path of impact, so that it is impossible to prevent cracks and the like generated during dicing from propagating into the chip region.

  In view of the above, the present invention prevents chipping or cracking that occurs on the side surface of a chip (semiconductor device) due to dicing when the wafer is divided into individual chips from being propagated into the chip region, thereby preventing moisture resistance of the semiconductor device. The purpose is to prevent deterioration of reliability and reliability.

  In order to achieve the above object, a semiconductor device according to the present invention includes an element formed in a chip region of a substrate, a stacked structure of a plurality of interlayer insulating films formed on the substrate, and a plurality of interlayers in the chip region. A wiring formed in at least one of the insulating films and a plug formed in at least one of the plurality of interlayer insulating films in the chip region and connecting the element and the wiring or connecting the wirings; A seal ring, a wiring, a plug, and a seal ring that are formed so as to penetrate the multilayer structure and surround the chip region continuously (that is, without interruption) in the multilayer structure of a plurality of interlayer insulating films in the peripheral portion of the chip region And a protective film formed on the laminated structure of the plurality of interlayer insulating films provided with at least one of the plurality of interlayer insulating films in the chip region A dual damascene wiring having a structure in which the wiring and the plug connected to the wiring are integrated is formed, and a portion formed in the interlayer insulating film provided with the dual damascene wiring in the seal ring is integrally configured. The protective film has an opening on the seal ring, and a cap layer connected to the seal ring is formed in the opening.

  According to the semiconductor device of the present invention, since the protective film such as a passivation film has an opening on the seal ring, in other words, the protective film is partially discontinuously formed at the peripheral portion of the chip region. It is possible to prevent the protective film in the chip area from being peeled off continuously due to the impact during dicing. Further, it is possible to prevent an impact received by the protective film outside the chip region from propagating through the protective film and being transmitted to the inside of the chip region.

  In addition, since at least a part of the seal ring is integrally formed in the interlayer insulating film provided with the dual damascene wiring, in other words, the part has a structure without a “seam”, so that The number of “joints” between parts can be reduced. Accordingly, it is possible to prevent cracks and the like generated during dicing from propagating into the chip region via the “joint” and to prevent impurities from entering the chip region from the outside of the seal ring. it can.

  Further, a cap layer (for example, a cap layer made of a conductor) is embedded in the opening of the protective film on the seal ring, and a continuous structure of the cap layer and the seal ring body is formed. For this reason, compared to the case where no cap layer is provided, moisture and impurities that have entered from the scribe region during dicing may enter the chip region via the periphery of the chip region, that is, the opening of the protective film in the vicinity of the scribe region. Intrusion can be prevented.

  In the semiconductor device of the present invention, at least a part of the seal ring is embedded in a recess provided in one interlayer insulating film of the plurality of interlayer insulating films or at least two or more interlayer insulating films stacked on each other. The aspect ratio of the recess is preferably 3 or more.

  In this way, the number of “joints” between parts in the entire seal ring can be reliably reduced.

  In the semiconductor device of the present invention, the seal ring preferably has two or more branch structures in at least one of the plurality of interlayer insulating films.

  If it does in this way, the structure which the parts which comprise a seal ring will be connected via two or more branches (each branch will also be a part of a seal ring) is obtained. Specifically, in a certain layer, the chip region is surrounded by a double (or triple) structure of the partial seal ring. In addition, since the integral seal ring is formed by overlapping a plurality of branches in the layer, the seal ring has a mechanically strong structure. Therefore, even if the interlayer insulating film in the scribe region is broken due to stress generated during dicing, the seal ring functions as a protective wall when the breakdown of the interlayer insulating film in the scribe region proceeds toward the chip region or during dicing. Is prevented from propagating through the interlayer insulating film in the chip region.

  In the semiconductor device of the present invention, the seal ring preferably surrounds the chip region twice or more.

  In this case, the first seal ring (inner seal ring) that surrounds the chip region and the first seal ring that surrounds the chip region and the scribe region that is formed to surround the periphery of the chip region and the first seal ring One seal ring and at least one seal ring (outer seal ring) that are electrically insulated are formed. Therefore, even if the outer seal ring of the first seal ring is damaged due to stress from the blade of the dicing device during dicing, the impact will proceed into the chip region. It can be protected by one seal ring. Further, even if the outer seal ring of the first seal ring is destroyed, the first seal ring is disposed independently of the outer seal ring, so that moisture and contamination are introduced into the chip region. Intrusion of the substance can be prevented by the first seal ring.

  When the seal ring surrounds the chip region twice or more, the protective film has an opening only on the outermost seal ring of the double or more seal rings, and the outermost seal is in the opening. A cap layer connected to the ring may be formed, or each of the double or more seal rings may have two or more branch structures in at least one of the plurality of interlayer insulating films. Good.

  In the semiconductor device of the present invention, it is preferable that a plurality of protrusions are provided on the side of the seal ring.

  In this way, the impact and stress caused by the contact between the blade of the dicing device and the film such as the protective film during dicing of the wafer and the cracks of the wafer caused by the impact and stress are caused by the side surface (scribe region) of the seal ring. Can be prevented from proceeding along the surface).

  In the semiconductor device of the present invention, the seal ring preferably has irregularities when viewed from above the substrate.

  In this way, the impact and stress caused by the contact between the blade of the dicing device and the film such as the protective film at the time of dicing the wafer and the cracks or the like of the wafer caused by them are caused along the side surface of the seal ring. It can be prevented from progressing.

  In the semiconductor device of the present invention, the seal ring may be composed of at least one of W, Al, and Cu.

  In the semiconductor device of the present invention, when the cap layer is made of Al, corrosion of the seal ring (especially a seal ring made of Cu) can be reliably prevented.

  A manufacturing method of a semiconductor device according to the present invention includes at least one of an element formed in a chip region of a substrate, a stacked structure of a plurality of interlayer insulating films formed on the substrate, and a plurality of interlayer insulating films in the chip region. A wiring formed in one, a plug formed in at least one of the plurality of interlayer insulating films in the chip region and connecting the element and the wiring or connecting the wirings, and a peripheral portion of the chip region A method for manufacturing a semiconductor device, comprising: a plurality of interlayer insulating film stacked structures; and a seal ring formed so as to penetrate the stacked structure and continuously surround a chip region. A first recess for embedding the plug and a second recess for embedding a part of the seal ring are formed in one insulating film of the interlayer insulating film so as to penetrate the one insulating film. Forming a third recess for connecting to the first recess and embedding the wiring on the upper portion of the one insulating film, and forming the first recess, the second recess, and the third recess on the first recess. A process of forming a part of a dual damascene wiring having a structure in which a plug and a wiring are integrated by embedding a conductive film and a seal ring, and a plurality of interlayer insulating films provided with the wiring, the plug, and the seal ring A step of forming a protective film on the laminated structure; and a step of forming an opening in a region of the protective film on the seal ring and forming a cap layer connected to the seal ring in the opening.

  That is, since the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device according to the present invention, the same effects as those of the semiconductor device according to the present invention can be obtained.

  In the method for manufacturing a semiconductor device of the present invention, when the aspect ratio of the second recess is 3 or more, the number of “joints” between parts in the entire seal ring can be reliably reduced.

  In the method of manufacturing a semiconductor device according to the present invention, a fourth recess for embedding another part of the seal ring in another insulating film laminated with one insulating film among the plurality of interlayer insulating films is provided in the second. The method may further include a step of forming so as to be connected to the recess.

  As described above, according to the present invention, in a semiconductor device including a chip region and a seal ring that is provided at a peripheral portion of the chip region and surrounds the periphery of the elements, wiring layers, and the like in the chip region, A seal ring with few “joints” is provided, a protective film on the seal ring is opened, and a cap layer is provided in the opening. In addition, the seal ring having such a structure may have a partially branched structure (at least two conductors that bridge the seal ring halfway) or surround the chip region more than twice. It may have a structure (a structure comprising a first seal ring formed at the peripheral edge of the chip region and at least one seal ring formed so as to surround the periphery of the first seal ring). .

  With the above-described features of the present invention, it is possible to prevent the chipping or cracking of the wafer caused by dicing when taking out individual chips (semiconductor devices) from the wafer from reaching the chip region, and thereby the moisture resistance of the semiconductor device. In addition, it is possible to prevent a decrease in reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The first feature of the present invention is that the seal ring is formed in the same process as the formation of the wiring structure and the dual damascene method is also used in the process of forming the seal ring. As a result, it is possible to form a seal ring with few “joints” between parts compared to the case of using the single damascene method. In the present application, a structure in which wirings and plugs (wirings or wirings and elements are connected) is referred to as a wiring structure.

  The second feature of the present invention is that a passivation film (for example, SiN film) covering the uppermost portion of the seal ring is partially opened and a cap is provided at the opening. This can prevent the impact received by the passivation film during dicing from propagating into the chip region (see the first embodiment).

  The third feature of the present invention is that a seal ring structure is provided with a structure partially branched into two or more, and the seal ring is formed by integrating the partially branched structure into two or more. It is. As a result, the mechanical strength of the seal ring itself is increased, whereby the impact from the scribe line during dicing can be prevented from being transmitted into the chip region.

  The fourth feature of the present invention is that the seal ring has a structure of at least two layers surrounding the chip region. Thereby, a stronger seal ring can be realized as compared with the case where the seal ring surrounds the chip region in a single layer (see the second embodiment).

  Other embodiments of the present invention will be described in detail in the following embodiments.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a plan view showing a part of a wafer provided with a semiconductor device according to the first embodiment of the present invention (a semiconductor device having a seal ring that surrounds a chip region in a single layer).

  As shown in FIG. 1, a plurality of chip regions 102 each serving as a semiconductor device are arranged on a wafer 101 serving as a semiconductor substrate typified by, for example, a silicon substrate. Each chip region 102 is provided with an IC (integrated circuit) circuit composed of a plurality of elements and having a predetermined function. Each chip region 102 is partitioned by a scribe region 103 provided in a lattice shape.

  Here, one semiconductor device (that is, one semiconductor chip) includes a chip region 102 in which an IC circuit composed of a plurality of elements and having a predetermined function is arranged, and the chip at the periphery of the chip region 102. The seal ring 104 is provided so as to surround the region 102. The wafer 101 on which a plurality of semiconductor devices are formed in this way is diced along the scribe region 103 after the completion of each chip, whereby the individual semiconductor devices are separated.

  2A, 2B, and 3A are cross-sectional views taken along the line AA 'of FIG. FIG. 3B schematically shows a planar configuration of one via in the structure shown in FIG. 2A or 2B and a seal via provided in the same layer as the via. FIG.

  2A, 2B, and 3A show the cross-sectional structures of the wiring structure of the chip region 102 and the seal ring.

  As shown in FIGS. 1, 2A, 2B, and 3A, the semiconductor device before dicing includes a chip region 102 and a scribe region 103, and the scribe region 103 in the chip region 102 is formed. A seal ring 104 is formed in the vicinity of the boundary.

  Here, the individual features of the structures shown in FIGS. 2A, 2B, and 3A are as follows.

  First, a feature of the structure shown in FIG. 2A is that seal vias constituting the seal ring 104 are continuously formed over at least two layers.

  Further, the feature of the structure shown in FIG. 2B is that seal vias and seal wirings constituting the seal ring 104 are alternately provided.

  Also, the structure shown in FIG. 3A is characterized in that the seal via constituting the seal ring 104 has a structure branched into at least two in the same interlayer insulating film.

  On the other hand, a feature common to each of the structures shown in FIGS. 2A, 2B, and 3A is that the seal ring 104 has a seal ring cap (cap layer 125) at the top. That is.

  Hereinafter, with reference to FIGS. 4A to 4D, FIGS. 5A to 5C, and FIGS. 6A to 6C for the method of manufacturing the semiconductor device having the structure shown in FIG. While explaining.

  First, as shown in FIG. 4A, an active layer 110 constituting an element such as a transistor is formed in a chip region 102 of a wafer 101 (hereinafter referred to as a substrate 101), and the chip region 102 of the substrate 101 is formed. A conductive layer 120 having the same configuration as that of the active layer 110 is formed at the peripheral edge (the seal ring forming region in the vicinity of the scribe region 103).

  Next, after the first interlayer insulating film 105 is deposited on the substrate 101, the first via 111 (FIG. 4) is formed in the first interlayer insulating film 105 in the chip region 102 by using a lithography method and a dry etching method. A via hole 105a for forming (b) is formed, and a groove for forming the first seal via 121 (see FIG. 4B) in the first interlayer insulating film 105 in the seal ring formation region. A concave portion 105b is formed. Here, the seal via is a part constituting the seal ring and is formed by embedding a conductive material in the groove-like recess. That is, the seal via has a line-like structure having the same width as the via in the chip region (see FIG. 3B).

  In the present embodiment, the aspect ratio of the seal via (that is, the ratio of the width to the depth in the recess in which the seal via is embedded) is preferably 1 or more.

  In the present embodiment, when forming the via hole 105a in the first interlayer insulating film 105 in the chip region 102, the groove-like recess 105b for forming the first seal via 121 is formed at the same time. Needless to say, the groove-shaped recess 105b may be formed separately.

  Next, as shown in FIG. 4B, a conductive film made of, for example, W (tungsten) is formed in the via hole 105a and the groove-like recess 105b formed in the first interlayer insulating film 105, for example, by CVD (chemical vapor deposition). After that, the conductive film protruding from each of the via hole 105a and the groove-like recess 105b is removed by using, for example, CMP (Chemical Mechanical Polishing), and thereby the first conductive layer 110 connected to the active layer 110 is removed. A first seal via 121 connected to the via 111 and the conductive layer 120 is formed.

  Thereafter, a second interlayer insulating film 106 is deposited on the first interlayer insulating film 105, and then the first wiring is formed on the second interlayer insulating film 106 in the chip region 102 by using a lithography method and a dry etching method. 112 (see FIG. 4C) is formed, and the first seal wiring 122 (see FIG. 4C) is formed in the second interlayer insulating film 106 in the seal ring formation region. Wiring trenches 106b for forming are formed.

  Subsequently, as shown in FIG. 4C, a conductive film made of, for example, Cu (copper) is formed on the wiring groove 106a and the wiring groove 106b formed in the second interlayer insulating film 106 by using, for example, an electroplating method. Embed. Thereafter, the conductive film protruding from the wiring trenches 106a and 106b is removed by, for example, the CMP method, whereby the first wiring 112 connected to the first via 111 and the first seal via 121 connected to the first seal via 121 are removed. Seal wiring 122 is formed.

  Next, as shown in FIG. 4D, after the third interlayer insulating film 107 is deposited on the second interlayer insulating film 106, the second interlayer insulating film 107 in the chip region 102 is formed on the second interlayer insulating film 107. A via hole 107a for forming the via 113 (see FIG. 5C) is formed, and a second seal via 123 (see FIG. 5C) is formed in the third interlayer insulating film 107 in the seal ring formation region. A groove-like recess 107b for forming is formed. In the present embodiment, with emphasis on efficiency, a via hole 107a for forming the second via 113 serving as an inter-wiring plug and a second seal via 123 serving as a part of the seal ring 104 are formed. Although the groove-shaped recess 107b is formed in the same process, the via hole 107a and the groove-shaped recess 107b can be formed in separate processes.

  Subsequently, as shown in FIG. 5A, a wiring trench for embedding the second wiring 114 (see FIG. 5C) is formed on the third interlayer insulating film 107 using a lithography method. A resist film 130 is formed. At this time, the resist film 130 has an opening in a wiring formation region including the via hole 107a. The resist film 130 is also embedded in the groove-like recess 107b.

  Thereafter, as shown in FIG. 5B, the resist film 130 is used as a mask to connect the via hole 107a and the second wiring on the third interlayer insulating film 107 in the chip region 102 by using a dry etching method. After forming the wiring groove 107c for forming 114, the remaining resist film 130 is removed by ashing.

  Next, as shown in FIG. 5C, a conductive film made of Cu, for example, is buried in the via hole 107a, the wiring groove 107c, and the groove-shaped recess 107b formed in the third interlayer insulating film 107. Next, as shown in FIG. Thereafter, the conductive film protruding from the wiring groove 107c and the groove-like recess 107b (the conductive film existing above the third interlayer insulating film 107) is removed by, for example, CMP. Accordingly, the second via 113 connected to the first wiring 112 and the second wiring 114 connected to the second via 113 (that is, the second via) are formed in the third interlayer insulating film 107 of the chip region 102. And a second seal via 123 connected to the first seal wiring 122 is formed in the third interlayer insulating film 107 in the seal ring formation region. Is done. A method of forming vias and wirings at the same time by embedding a conductive film in the recesses as described above is generally called a dual damascene method.

  By the way, when the second via 113 and the second wiring 114 are formed by a single damascene method, a via hole 107a for forming the second via 113 and a wiring for forming the second wiring 114 are formed. Since the conductive film is separately embedded in the groove 107c, the second seal via 123 is formed in accordance with the formation of the wiring structure. The film is embedded. In that case, a “joint” is generated due to the conductive film being embedded twice in the second seal via 123.

  However, in this embodiment, since the second seal via 123 is formed by embedding the conductive film once in accordance with the wiring formation process of the dual damascene structure, a joint of the conductive film is generated inside the second seal via 123. There is nothing.

  Further, when a dual damascene structure wiring is formed in one interlayer insulating film of the chip region 102 and a seal via constituting the seal ring 104 is formed in the interlayer insulating film as in this embodiment, the aspect ratio A seal via with 3 or more can be formed. Therefore, since the joints between the parts constituting the seal ring 104 can be reduced, it is possible to realize a seal ring that can further prevent contamination of the chip region 102 from the outside.

  Subsequently, as shown in FIG. 6A, after depositing a fourth interlayer insulating film 108 on the third interlayer insulating film 107, the same steps as shown in FIGS. 4D to 5C are performed. Then, a dual damascene structure is used to form a wiring structure having a dual damascene structure and a seal ring in the fourth interlayer insulating film 108.

  Specifically, as shown in FIG. 6A, a third via 115 (see FIG. 6B) is formed in the fourth interlayer insulating film 108 in the chip region 102 by using a lithography method and a dry etching method. ) Is formed, and a groove-like recess 108b for forming the third seal via 124 is formed in the fourth interlayer insulating film 108 in the seal ring formation region. Thereafter, a resist film (not shown) for forming a wiring trench for embedding the third wiring 116 (see FIG. 6B) is formed on the fourth interlayer insulating film 108 by lithography. Here, the resist film has an opening in a wiring formation region including the via hole 108a. The resist film is also embedded in the groove-like recess 108b. Thereafter, by using a dry etching method with the resist film as a mask, a wiring groove 108c for connecting to the via hole 108a and forming the third wiring 116 is formed on the fourth interlayer insulating film 108 in the chip region 102. After the formation, the remaining resist film is removed by ashing. As a result, a recess (via hole 108a and wiring groove 108c) for forming the dual damascene wiring and a groove-shaped recess 108b for forming the third seal via 124 are formed in the fourth interlayer insulating film 108. .

  Subsequently, as shown in FIG. 6B, the via hole 108a for forming the third via 115 and the wiring groove 108c for forming the third wiring 116 provided in the fourth interlayer insulating film 108 are integrated. A conductive film made of Cu, for example, is buried in the recessed portion of the dual damascene structure and the groove-like recess portion 108b for forming the third seal via 124. Thereafter, the conductive film that protrudes from the wiring groove 108c and the groove-like recess 108b (the conductive film existing above the fourth interlayer insulating film 108) is removed by, for example, CMP. Accordingly, the third via 115 connected to the second wiring 114 and the third wiring 116 connected to the third via 115 (that is, the third via) are formed in the fourth interlayer insulating film 108 in the chip region 102. 115 and the third wiring 116 are formed, and a third seal via 124 connected to the second seal via 123 is formed in the fourth interlayer insulating film 108 in the seal ring formation region. The

  Thereafter, as shown in FIG. 6B, a passivation film 109 serving as a protective film for the wiring layer is deposited on the fourth interlayer insulating film 108 serving as the uppermost wiring layer. Subsequently, the passivation film 109 on each of the third wiring 116 and the third seal via 124 is partially opened by using a lithography method and a dry etching method. Here, the opening of the passivation film 109 on the third seal via 124 has a groove shape that continuously surrounds the chip region 102.

  Thereafter, as shown in FIG. 6C, over the entire surface of the passivation film 109 including the openings on the third wiring 116 and the third seal via 124, for example, Al (for example) by sputtering. (Aluminum) film is deposited, and then the Al film is patterned into a predetermined shape by lithography and dry etching. Specifically, unnecessary Al films formed in the regions other than the openings and the vicinity thereof are removed. As a result, a pad electrode 117 connected to the third wiring 116 is formed in the opening of the passivation film 109 on the third wiring 116, and at the opening of the passivation film 109 on the third seal via 124. A cap layer 125 connected to the third seal via 124, that is, the seal ring 104 is formed. That is, in the chip region 101, a wiring structure and a bonding pad (pad electrode 117) for connecting it to an external electrode are formed, and the seal ring forming region, that is, the peripheral portion of the chip region 102 is at the uppermost part. A seal ring 104 having a cap layer 125 is formed.

  As described above, in the present embodiment, the wiring structure is formed by using the dual damascene method in which the hole in which the via is formed and the groove in which the wiring is formed are simultaneously filled with the conductive film. Seal vias constituting the seal ring are formed in the same process as the formation. That is, when embedding a dual damascene wiring groove in which a concave portion in which a via is formed and a wiring groove in which a wiring is formed is embedded, the concave portion in which the seal via is formed is buried, A certain seal via, for example, a seal via having an aspect ratio of depth (height) to width of 1 or more (preferably 3 or more) can be formed by one embedding process.

  Therefore, according to the present embodiment, it is possible to form a seal ring in which “joints” due to embedding are reduced as compared with the case where wiring is formed using a single damascene method. Specifically, as a merit that the conductive film is embedded less, the number of connection interfaces between the conductive films constituting the seal ring is reduced. That is, the probability of discontinuity between seal ring parts is reduced due to poor conductive film embedding performance, and as a result, reliability is higher than that of seal rings with a structure with a large number of embeddings. High sealing ring can be formed.

  In the present embodiment, the cap layer 125 connected to the uppermost portion of the seal ring 104 is a pad for supplying power to the wiring layer in the chip region 102 from the outside or for taking out a signal from the wiring layer to the outside. It is formed at the same time in the step of forming (pad electrode 117). As a result, the seal ring 104 having the cap layer 125 at the uppermost portion can be formed without adding a new cap layer forming step.

  Hereinafter, the seal ring structure of the present embodiment shown in FIG.

  As shown in FIG. 2A (or FIG. 6C), the seal ring of this embodiment is formed near the boundary between the chip region 102 and the scribe region 103. Here, elements such as transistors (not shown) are formed on the substrate 101 in the chip region 102, and a plurality of wiring layers are formed on the elements such as transistors.

  Further, as shown in FIG. 2A, a seal ring 104 formed by combining the conductor layer 120, the seal vias 121, 123, and 124, and the seal wiring 122 is provided at the peripheral portion of the chip region 102. It is formed so as to surround the inside of the chip region 102, that is, the above-described elements and wiring layers and penetrate the laminated structure of a plurality of interlayer insulating films 105 to 108. That is, in the laminated insulating film structure at the peripheral edge of the chip region 102 (near the boundary with the scribe region 103 in the chip region 102), there is no interruption from the lowermost interlayer insulating film to the uppermost interlayer insulating film (no gap). The seal ring 104 which is a conductor (for example, copper) embedded in a continuous manner functions as a barricade that blocks an intrusion path of impurities and the like from the outside into the chip region 102.

  In the present embodiment, at least one of the conductors (parts) stacked to form the seal ring 104 is formed in a wiring forming process having a dual damascene structure as described above. Since it is formed, the conductor becomes a seal via that penetrates through at least one interlayer insulating film without a “joint”. That is, the “ring” of the seal ring 104 is reduced by forming the seal ring 104 in the process of forming the dual damascene wiring in the entire chip region 102 where the elements such as the seal ring and the transistor and the wiring layer are formed. be able to. Here, if there is a “joint” in the seal ring, that is, a connection interface between conductive films as parts, the impact generated when the substrate (wafer) 101 is cut along the scribe region 103 or moisture entering from the outside , It becomes easy to propagate into the chip region 102 through the “joint”. Therefore, as in the present embodiment, by reducing the “joint” between the parts constituting the seal ring 104, it is possible to prevent the impact at the time of wafer cutting and moisture from the outside from entering the chip region 102. it can.

  In the present embodiment, since the seal ring 104 is formed at the peripheral edge of the chip region 102 (near the boundary between the chip region 102 and the scribe region 103), a plurality of seal rings 104 are formed on the substrate (wafer) 101. When individual semiconductor devices are taken out as individual chips by dicing along the scribe region 103 of the wafer, mechanical shock and stress that the scribe region 103 receives during dicing propagates into the chip region 102. Can be prevented.

  Further, in the seal ring structure shown in FIG. 2A, a cap layer made of, for example, Al on the third seal via 124 formed in the uppermost interlayer insulating film (fourth interlayer insulating film 108). Reference numeral 125 denotes a passivation film (passivation film 109) formed in a portion on the third seal via 124, specifically, a passivation film so as to continuously surround a wiring layer or the like formed in the chip region 102. 109 is formed in a groove provided. That is, the cap layer 125 connected to the uppermost portion of the seal ring 104 is formed so as to protrude from the surface of the passivation film 109, whereby the passivation film 109 is partially opened and becomes discontinuous.

  Therefore, in the present embodiment, the passivation film 109 in the chip region 102 and the passivation film 109 outside the seal ring formation region (including the scribe region 103) are discontinuous, so that the passivation in the vicinity of the scribe region 103 during dicing is performed. The mechanical shock received by the film 109 is not easily transmitted to the film such as the passivation film 109 deposited on the chip region 102. In other words, since there is a discontinuous part in the passivation film 109 in the vicinity of the boundary between the chip region 102 and the scribe region 103, it is possible to prevent the impact during wafer dicing from reaching the chip region 102.

  For this reason, it is possible to avoid a situation in which a crack or the like occurs in the passivation film 109 in the scribe region 103 due to an impact at the time of dicing and a film peeling occurs in the passivation film 109 or the like in the chip region 102 due to the impact. It is possible to prevent cracks from occurring. As a result, contaminants such as moisture and mobile ions can be prevented from entering the chip from the chip surface, so that the reliability of the semiconductor device can be improved.

  Further, a cap layer 125 is embedded in the opening of the passivation film 109 on the seal ring 104, and a continuous structure of the cap layer 125 and the main body of the seal ring 104 is formed. Therefore, compared to the case where the cap layer 125 is not provided, moisture and impurities that have entered from the scribe region 103 during dicing are caused by the peripheral portion of the chip region 102, that is, the opening of the passivation film 109 in the vicinity of the scribe region 103. It is possible to prevent the chip area 103 from entering via the.

  Further, in the seal ring structure of this embodiment shown in FIG. 2A, the width of a part of the seal ring 104 (specifically, the seal vias 121, 123, and 124) is narrow, and specifically, the aspect of the part. The ratio (the ratio of height to width) is preferably 1 or more. In particular, the aspect ratio of the seal via formed so as to extend from the upper end to the lower end of the interlayer insulating film in which the dual damascene wiring is formed is preferably 3 or more. Alternatively, when the seal vias (for example, the seal vias 123 and 124) formed in each of the interlayer insulating films which are overlapped over two or more layers are laminated, the aspect ratio of the laminated structure of the seal vias is preferably 3 or more. . As described above, when a seal via is used as a conductor constituting a part constituting the seal ring 104, the seal ring is used in accordance with the wiring layout in each interlayer insulating film by utilizing the fact that the via width is narrower than the wiring width. The margin for placement can be adjusted to some extent. That is, it is preferable to use a seal via as a part of the seal ring 104 in an interlayer insulating film that requires the chip region 102 to be widely used for arranging a wiring layer or the like.

  On the other hand, when considering the wiring layout of the chip region 102 and the like, if there is a certain margin in the space where the seal ring in the target interlayer insulating film is to be formed, a seal wiring having a width comparable to the wiring is used. be able to. That is, the seal ring can be formed using a mask provided with a seal wiring pattern having a width comparable to the wiring pattern.

  As described above, in the present embodiment, the width of each part constituting the seal ring can be selected for each insulating layer while considering the wiring layout of the chip region 102. Therefore, the width (thickness) of each insulating layer of the seal ring can be controlled as necessary.

  In this embodiment, instead of the seal ring structure shown in FIG. 2A, that is, the seal ring structure in which at least two or more seal vias are continuously laminated, the seal ring shown in FIG. Similar to the structure, that is, the wiring structure in which the vias and the wirings in the chip region 102 where the elements and the like are formed are alternately stacked, the seal ring 104 having the structure in which the seal vias and the sealing wirings are alternately stacked. It may be used.

  Hereinafter, the seal ring structure shown in FIG. 2B will be described in detail. In FIG. 2B, the same components as those in FIG. 2A are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 2B, the seal ring 104 is formed at the same time as the wiring structure forming process in the chip region 102. Specifically, the first seal via 121 is formed in the first interlayer insulating film 105 on the conductor layer 120, and the second interlayer insulating film 106 on the first interlayer insulating film 105 is A first seal wiring 122 connected to one seal via 121 is formed. Further, a second seal via 126 connected to the first seal wiring 122 and a second seal connected to the second seal via 126 are formed on the third interlayer insulating film 107 deposited on the second interlayer insulating film 106. A wiring (seal portion) having a dual damascene structure integrated with the wiring 127 is formed. Further, the fourth interlayer insulating film 208 on the third interlayer insulating film 207 includes a third seal via 128 connected to the second seal wiring 127 and a third seal wiring 129 connected to the third seal via 128. Is formed as a dual damascene seal part. Further, the upper side of the third seal wiring 129 in the passivation film 109 on the fourth interlayer insulating film 108 is partially opened, and the cap layer 125 connected to the third seal wiring 129 is formed in the opening. Is formed.

  As described above, in the semiconductor device of this embodiment shown in FIG. 2B, the seal ring 104 having the same structure as the wiring structure formed in the chip region 102 is formed, so that the wiring is formed. The seal ring 104 can be formed together in the process.

  Further, in the semiconductor device of this embodiment shown in FIG. 2B, the seal ring 104 is configured in accordance with the wiring structure, for example, the second via 113 and the second wiring 114 are formed by the dual damascene method. For example, the second seal via 126 and the second seal wiring 127 are formed by a dual damascene method. As a result, since the concave portion where the second seal via 126 is formed and the groove where the second seal wiring 127 is formed can be formed integrally, both can be buried simultaneously with the conductive film. The “seam” between the two seal vias 126 and the second seal wiring 127 can be eliminated. That is, as in the present embodiment, by forming the wiring structure and the seal ring 104 using the dual damascene method, it is possible to reduce “joints” in the seal ring 104, thereby reducing the scribe region 103 and the like. A seal ring 104 that can prevent moisture and impurities from entering the chip region 102 from the outside can be formed. Therefore, the moisture resistance of the semiconductor chip (semiconductor device) can be improved, and the yield at the time of manufacturing the semiconductor chip can be improved.

  The seal ring structure shown in FIG. 2B is formed using a photomask in which the mask pattern for the wiring structure in the chip region 102 and the mask pattern for the seal ring correspond to the same interlayer insulating film. For example, when a dual damascene wiring in which vias (plugs) and wiring are integrated is formed in the interlayer insulating film 107 in the chip region 102, dual parts are similarly used for forming the seal ring 104 in the interlayer insulating film 107. The damascene method is applied. That is, the portion of the seal ring 104 formed in the interlayer insulating film 107 has a second seal via 126 having the same width as the second via 113 and a second width having the same width as the second wiring 114. 2 seal wires 127. Further, in the interlayer insulating film 107, the laminated structure of the second seal via 126 and the second seal wiring 127 penetrates the interlayer insulating film 107 in the vertical direction and continuously surrounds the chip region 102 (without interruption). It is formed as follows.

  Further, the seal ring 104 shown in FIG. 2B is formed by alternately stacking seal wirings and seal vias, and the width of the seal wiring is larger than the width of the seal vias. For this reason, the strength of the seal ring can be further improved as compared with the case where only the seal vias or mainly the seal vias are stacked to form the seal ring.

  Further, the manufacturing method of the semiconductor device having the structure shown in FIG. 2B is different from the manufacturing method of the semiconductor device having the structure shown in FIG. Only the mask pattern. That is, for example, when forming the seal ring 104 shown in FIG. 2A, for the seal ring in the mask (plural sheets) set so that the third seal via 124 is formed on the second seal via 123. The mask pattern is partially changed in forming the seal ring 104 shown in FIG. Specifically, the mask pattern for the seal ring in each mask is formed such that the second seal wiring 127 is formed on the second seal via 126 and the third seal wiring 129 is formed on the third seal via 128. In other words, the setting is made so that the seal via and the seal wiring are alternately formed.

  Hereinafter, the seal ring structure shown in FIG. 3A, that is, the seal ring 104 having a structure in which the seal via branches into at least two or more in the same interlayer insulating film will be described in detail. In FIG. 3A, the same components as those in FIG. 2A are denoted by the same reference numerals, and the description thereof is omitted.

  The seal ring structure shown in FIG. 3A is different from the seal ring structure shown in FIG. 2A in that the first interlayer insulating film 105 is replaced with the conductive layer 120 instead of the first seal via 121. Seal vias 121a and 121b to be connected are provided, and seal vias 123a and 123b to be connected to the first seal wiring 122 are provided in the third interlayer insulating film 107 instead of the second seal via 123, respectively. And that the fourth interlayer insulating film 108 is provided with seal vias 124a and 124b connected to the seal vias 123a and 123b, respectively, instead of the third seal via 124. The upper portions of the seal vias 121a and 121b are connected to the first seal wiring 122, and the upper portions of the seal vias 124a and 124b are connected to the cap layer 125.

  That is, the method for manufacturing the semiconductor device having the structure shown in FIG. 3A is different from the method for manufacturing the semiconductor device having the structure shown in FIG. A photomask is provided with a mask pattern capable of forming two seal vias, and a conductive film is embedded in a pair of parallel groove-like recesses formed thereby.

  According to the seal ring structure shown in FIG. 3A, in addition to the effects obtained by the seal ring structure shown in FIG. That is, since the width of the seal via is narrower than that of the seal wiring, the strength of the seal via is slightly lower than that of the seal wiring. On the other hand, as in the seal ring structure shown in FIG. 3 (a), the branch seal via is provided by using a seal via that is branched into two or more instead of one seal via as a part constituting the seal ring. In the interlayer insulating layer, a multiple seal ring structure (a structure surrounding the chip region 102 in multiple layers) can be realized. Therefore, the strength of the seal ring structure shown in FIG. 3A having a multiple structure portion is improved as compared with a seal ring having one (that is, a single structure) seal via in an interlayer insulating film. In terms of processing, the seal ring structure shown in FIG. 2A can be realized more easily than the seal ring structure shown in FIG.

  Further, according to the seal ring structure shown in FIG. 3A, when the wafer (substrate 101) is cut along the scribe region 103 and divided into individual chips, the seal ring 104 is partly affected by the impact of this dicing. Even if the seal ring 104 of the damaged portion has a double structure or a multiple structure more than that, the chip area 102 inside the scribe area 103 is affected by the impact described above. Can be prevented. Specifically, it is possible to suppress moisture from entering the chip region 102 from the scribe region 103 and propagation of an impact generated when the wafer is cut along the scribe region 103 into the chip region 102.

  In addition, in the seal ring 104 shown in FIG. 3A, a structure in which two seal vias are branched from one seal wiring is used. Instead, three or more from one seal wiring are used. A structure in which the seal via is branched may be used. Further, in the seal ring 104 shown in FIG. 3A, a structure in which the seal vias of each layer are all branched into a plurality of branches is used. However, the layout margin required for the wiring layer formed in the chip region 102 is used. Alternatively, a branch structure of seal vias may be selectively used in each layer depending on the strength of the film (interlayer insulating film).

  Further, in this embodiment, the wiring structure is formed in the interlayer insulating film stacked in four layers, but the number of layers of the interlayer insulating film is not limited to four layers, and may be less than four layers depending on the chip structure. It goes without saying that there may be many.

  In this embodiment, Cu is used as the conductive material constituting the seal ring 104. However, the present invention is not limited to this, and the seal ring 104 may be formed using at least one of W, Al, and Cu. . Thus, the seal ring 104 can be formed from the same material as the wiring and via formed in the chip region 102 of the semiconductor device.

  In the present embodiment, the conductive material constituting the cap layer 125 is not particularly limited. However, when the material is Al, corrosion of the seal ring 104 (especially, a seal ring made of Cu) can be reliably prevented. Can do.

  Further, in the present embodiment, when a plurality of seal vias are continuously laminated as in the seal ring structure shown in FIG. 2A or FIG. 3A, for example, one of the upper layer seal vias or the lower layer seal vias. It is preferable to make this contact surface larger than the other contact surface. In this way, the contact margin can be improved.

(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 is a plan view showing a part of a wafer provided with a semiconductor device (semiconductor device having a seal ring that doublely surrounds a chip region) according to the second embodiment of the present invention. In the present application, a seal ring structure that surrounds the chip region twice or more is called a multi-seal ring.

  As shown in FIG. 7, for example, a plurality of chip regions 202 each serving as a semiconductor device are arranged on a wafer 201 serving as a semiconductor substrate typified by a silicon substrate or the like. Each chip region 202 is provided with an IC circuit composed of a plurality of elements and having a predetermined function. Each chip area 202 is partitioned by a scribe area 203 provided in a lattice shape.

  Here, one semiconductor device (that is, one semiconductor chip) includes an IC circuit (disposed in the chip region 202) having a predetermined function and a peripheral portion of the chip region 202. The seal ring 204a and the seal ring 204b are provided so as to surround the chip region 202. In the present embodiment, a double structure multi-seal ring is used. However, a triple structure, a quadruple structure, or a multiple structure multi-seal ring may be used depending on the layout margin. .

  The wafer 201 on which a plurality of semiconductor devices in which the chip region 202 is surrounded by the multi-seal ring 204 is formed is diced along the scribe region 203 after each chip is completed. To be separated.

  According to the present embodiment, since the seal ring 204 is formed at least in the vicinity of the scribe region 203 in the chip region 202, one seal ring (outer seal ring) was broken when the wafer 201 was diced. However, it is possible to prevent the elements, the active region, and the like in the chip region 202 from being damaged by another seal ring inside the seal ring. Therefore, in the process of dividing the wafer 201 into chips, it is possible to prevent the chip region 202, that is, the element, the active region, and the like from being damaged and the performance of the semiconductor chip from being deteriorated.

  FIGS. 8A and 8B show variations of the cross-sectional structure taken along the line BB ′ of FIG. 7 (the cross-sectional structure of the end portion of the semiconductor device including the seal ring portion located at the periphery of the chip region 202). Yes.

  As shown in FIG. 7, FIG. 8A and FIG. 8B, the semiconductor device before dicing is composed of a chip region 202 and a scribe region 203, and in the vicinity of the boundary between the chip region 202 and the scribe region 203. Seal rings 204a and 204b are formed.

  Here, the individual features of the structures shown in FIGS. 8A and 8B are as follows.

  First, the feature of the structure shown in FIG. 8A is that the seal vias constituting the seal rings 204a and 204b are continuously formed over at least two layers.

  Also, the structure shown in FIG. 8B is characterized in that the seal vias constituting the seal rings 204a and 204b are continuously formed over at least two layers and the seal vias are formed in the same interlayer insulating film. It is formed as two or more seal vias adjacent to each other, and the two or more adjacent seal vias are formed on the same one seal wiring formed in another insulating film above or below the insulating film in which they are formed. Is connected. That is, the seal via constituting the seal ring 204 shown in FIG. 8B has a structure branched into at least two or more in the same interlayer insulating film.

  On the other hand, the features common to the structures shown in FIGS. 8 (a) and 8 (b) are that at least two seal rings 204 are present, and that seal ring caps are provided at the top of each seal ring 204a and 204b. (Cap layers 225a and 225b).

  A method for manufacturing a semiconductor device having the structure shown in FIG. 8A will be described below with reference to FIGS. 9A to 9D and FIGS. 10A to 10C.

  First, as shown in FIG. 9A, an active layer 210 constituting an element such as a transistor is formed in a chip region 202 of a wafer 201 (hereinafter referred to as a substrate 201), and the chip region 202 of the substrate 201 is formed. Two conductive layers 220a and 220b that are adjacent to each other are formed at the peripheral edge (the seal ring formation region in the vicinity of the scribe region 203). Here, the configuration of the conductive layers 220 a and 220 b is the same as that of the active layer 210.

  Next, after depositing a first interlayer insulating film 205 on the substrate 201, a first via 211 (FIG. 9) is formed in the first interlayer insulating film 205 in the chip region 202 by using a lithography method and a dry etching method. (See (b)) is formed, and the first seal via 221a and the first seal via 221a disposed on the adjacent conductive layers 220a and 220b are formed in the first interlayer insulating film 205 in the seal ring formation region, respectively. Groove-shaped recesses 205b and 205c for forming 221b (see FIG. 9B) are formed. Here, the seal via is a part constituting the seal ring and is formed by embedding a conductive material in the groove-like recess. That is, the seal via has a line-like structure having the same width as the via in the chip region.

  In the present embodiment, the aspect ratio of the seal via (that is, the ratio of the width to the depth in the recess in which the seal via is embedded) is preferably 1 or more. In particular, when the seal via is formed in accordance with the wiring layer as in this embodiment, it is preferable to set the aspect ratio of the seal via to 3 or more according to the degree of miniaturization of the wiring.

  In the present embodiment, when forming the via hole 205a in the first interlayer insulating film 205 in the chip region 202, the groove-like recesses 205b and 205c for forming the first seal vias 221a and 221b are formed at the same time. Needless to say, the via hole 205a and the groove-like recesses 205b and 205c may be formed separately.

  Next, as shown in FIG. 9B, a conductive film made of, for example, W is embedded in the via hole 205a and the groove-like recesses 205b and 205c formed in the first interlayer insulating film 205 by, for example, the CVD method, and then For example, the excess conductive film protruding from each of the via hole 205a and the groove-like recesses 205b and 205c is removed using CMP, whereby the first via 211 connected to the active layer 210 and the conductive layers 220a and 220b, respectively. And first seal vias 221a and 221b that are adjacent to each other are formed.

  Thereafter, after depositing a second interlayer insulating film 206 on the first interlayer insulating film 205, the first wiring is formed on the second interlayer insulating film 206 in the chip region 202 by using a lithography method and a dry etching method. A wiring groove 206a for forming 212 (see FIG. 9C) is formed, and first seal wirings 222a and 222b (FIG. 9) adjacent to each other are formed in the second interlayer insulating film 206 in the seal ring formation region. Wiring grooves 206b and 206c for forming (see (c)) are formed.

  Subsequently, as shown in FIG. 9C, a conductive film made of, for example, Cu is embedded in the wiring grooves 206a, 206b, and 206c formed in the second interlayer insulating film 206 by using, for example, an electroplating method. Thereafter, the conductive film protruding from the wiring trenches 206a, 206b and 206c is removed by, for example, the CMP method, whereby the first wiring 212 connected to the first via 211, and the first seal vias 221a and 221b, respectively. First seal wirings 222a and 222b that are connected to each other and are adjacent to each other are formed.

  Subsequently, after a third interlayer insulating film 207 is deposited on the second interlayer insulating film 206, the second via 213 is formed on the third interlayer insulating film 207 in the chip region 202 (see FIG. 10A). And a groove for forming second seal vias 223a and 223b (see FIG. 10A) adjacent to each other in the third interlayer insulating film 207 in the seal ring formation region. The concave portions 207b and 207c are formed.

  Subsequently, as shown in FIG. 9D, a wiring trench for embedding the second wiring 214 (see FIG. 10A) is formed on the third interlayer insulating film 207 by using a lithography method. A resist film 230 is formed. At this time, the resist film 230 has an opening in a wiring formation region including the via hole 207a. In addition, the resist film 230 is also embedded in the groove-shaped recesses 207b and 207c formed previously.

  Thereafter, by using a dry etching method with the resist film 230 as a mask, a wiring trench for connecting to the via hole 207a and forming the second wiring 214 is formed on the third interlayer insulating film 207 in the chip region 202. After that, the remaining resist film 230 is removed by ashing. Thereafter, the via hole 207a formed in the previous step in the third interlayer insulating film 207, the wiring groove that is integrated with the via hole 207a to form the recess of the dual damascene structure, and the groove-like recesses 207b and 207c are made of Cu, for example. A conductive film is embedded. Thereafter, the conductive film protruding from the wiring grooves and the groove-shaped recesses 207b and 207c (conductive film existing above the third interlayer insulating film 207) is removed by, for example, CMP. Accordingly, as shown in FIG. 10A, the second via 213 connected to the first wiring 212 and the second via 213 connected to the first wiring 212 are formed in the third interlayer insulating film 207 in the chip region 202. Two wirings 214 (that is, a dual damascene wiring composed of the second via 213 and the second wiring 214) are formed, and the first seal wiring 222a is formed on the third interlayer insulating film 207 in the seal ring formation region. And second seal vias 223a and 223b that are connected to and adjacent to each other. A method of forming vias and wirings at the same time by embedding a conductive film in the recesses as described above is generally called a dual damascene method.

  When the second via 213 and the second wiring 214 are formed by a single damascene method, the via hole 207a for forming the second via 213 and the wiring for forming the second wiring 214 are formed. The conductive film is embedded separately into the trench. For this reason, since the second seal vias 223a and 223b are formed in accordance with the formation of the wiring structure, the conductive film is embedded in the groove-like recesses 207b and 207c in two steps. In that case, a “seam” is generated inside the second seal vias 223a and 223b due to filling the conductive film in two steps.

  However, in this embodiment, since the second seal vias 223a and 223b are formed by embedding the conductive film once in accordance with the wiring formation process of the dual damascene structure, a joint of the conductive film is generated inside each seal via. There is no.

  Further, when a dual damascene structure wiring is formed in one interlayer insulating film of the chip region 202 and a seal via constituting the seal ring 204 is formed in the interlayer insulating film as in this embodiment, the aspect ratio A seal via with 3 or more can be formed. Accordingly, since the joints between the parts constituting the seal ring 204 can be reduced, it is possible to realize a seal ring that can further prevent contamination of the chip region 202 from the outside.

  Subsequently, as shown in FIG. 10B, after depositing a fourth interlayer insulating film 208 on the third interlayer insulating film 207, the same steps as shown in FIGS. 9C to 10A are performed. In addition, a wiring structure having a dual damascene structure and a seal ring are formed in the fourth interlayer insulating film 208 by using a dual damascene method.

  Specifically, as shown in FIG. 10B, a via hole for forming the third via 215 is formed in the fourth interlayer insulating film 208 in the chip region 202 by using a lithography method and a dry etching method. In addition, two groove-like recesses for forming third seal vias 224a and 224b adjacent to each other are formed in the fourth interlayer insulating film 208 in the seal ring formation region. Thereafter, a resist film (not shown) for forming a wiring trench for embedding the third wiring 216 is formed on the fourth interlayer insulating film 208 by lithography. Here, the resist film has an opening in a wiring formation region including the via hole. The resist film is also embedded in the groove-shaped recesses. Thereafter, a wiring trench for connecting to the via hole and forming the third wiring 216 is formed on the fourth interlayer insulating film 208 in the chip region 202 by dry etching using the resist film as a mask. After the formation, the remaining resist film is removed by ashing. As a result, a recess for forming dual damascene wiring (the aforementioned via hole and wiring groove) and two groove-shaped recesses for forming the respective third seal vias 224a and 224b are formed in the fourth interlayer insulating film 208. And are formed.

  Subsequently, as shown in FIG. 10B, the via hole for forming the third via 215 and the wiring groove for forming the third wiring 216 provided in the fourth interlayer insulating film 208 are integrated. A conductive film made of Cu, for example, is embedded in the recesses of the dual damascene structure and the groove-like recesses for forming the third seal vias 224a and 224b. Thereafter, the conductive film protruding from the wiring groove and the groove-like recess (conductive film existing above the fourth interlayer insulating film 208) is removed by, for example, CMP. As a result, the third via 215 connected to the second wiring 214 and the third wiring 216 connected to the third via 215 (that is, the third via) are formed in the fourth interlayer insulating film 208 of the chip region 202. A third damascene wiring comprising 215 and a third wiring 216) and a third seal via connected to each of the second seal vias 223a and 223b on the fourth interlayer insulating film 208 in the seal ring formation region. 224a and 224b are formed.

  Thereafter, as shown in FIG. 10B, a passivation film 209 serving as a protective film for the wiring layer is deposited on the fourth interlayer insulating film 208 serving as the uppermost wiring layer. Subsequently, the passivation film 209 on each of the third wiring 216 and the adjacent third seal vias 224a and 224b is partially opened by using a lithography method and a dry etching method. Thus, the upper surfaces of the third wiring 216 and the third seal vias 224a and 224b are exposed.

  Thereafter, as shown in FIG. 10C, over the entire surface of the passivation film 209 including the openings on the third wiring 216 and the third seal vias 224a and 224b, for example, by sputtering, for example, An Al film is deposited, and then the Al film is patterned into a predetermined shape using a lithography method and a dry etching method. Specifically, unnecessary Al films formed in the regions other than the openings and the vicinity thereof are removed. As a result, the pad electrode 217 connected to the third wiring 216 is formed in the opening of the passivation film 209 on the third wiring 216, and each opening of the passivation film 209 on the third seal vias 224a and 224b is formed. The cap layers 225a and 225b connected to the third seal vias 224a and 224b, that is, the seal rings 204a and 204b, respectively, are formed in the portion.

  As a result, a wiring structure and a bonding pad (pad electrode 217) for connecting it to an external electrode are formed in the chip region 201, and a seal ring forming region, that is, a peripheral portion of the chip region 202 (the scribe region 203 and the scribe region 203). And the cap layers 225a and 225b connected to the seal rings 204a and 204b, respectively, through the seal rings 204a and 204b and a protective film (passivation film 209) deposited on the seal rings 204a and 204b. Is done.

  As described above, in the present embodiment, the wiring structure is formed by using the dual damascene method in which the hole in which the via is formed and the groove in which the wiring is formed are simultaneously filled with the conductive film. Seal vias constituting the seal ring are formed in the same process as the formation. That is, when embedding a dual damascene wiring groove in which a concave portion in which a via is formed and a wiring groove in which a wiring is formed is embedded, the concave portion in which the seal via is formed is buried, A recess for forming a certain seal via, for example, a recess for forming a seal via having an aspect ratio of depth to width of 1 or more (preferably 3 or more) can be embedded in one embedding process.

  Therefore, according to the present embodiment, it is possible to form a seal ring in which “joints” due to embedding are reduced as compared with the case where wiring is formed using a single damascene method. Specifically, as a merit that the conductive film is embedded less, the number of connection interfaces between the conductive films constituting the seal ring is reduced. That is, the probability of discontinuities between seal ring parts is reduced due to poor conductive film embedding performance, resulting in a seal ring having a structure with a large number of embeddings (ie, using a single damascene method). The seal ring can be formed with higher reliability than the seal ring formed in the above manner.

  In the present embodiment, the cap layers 225a and 225b connected to the uppermost portions of the seal rings 204a and 204b supply power from the outside to the IC circuit or the like in the chip region 202, or externally from the IC circuit or the like. Are simultaneously formed in the step of forming a pad (pad electrode 217) for taking out a signal. This makes it possible to form the seal rings 204a and 204b having the cap layers 225a and 225b on the uppermost parts without newly adding a cap layer forming step.

  Further, according to the present embodiment, in addition to the above-described effects obtained in the first embodiment, the following effects can be obtained.

  That is, in the second embodiment, the seal ring 204 that continuously surrounds the chip region 202 is formed on the periphery of the chip region 202 in a double manner. Therefore, when the semiconductor wafer (substrate) 201 is diced along the scribe region 203 and a completed individual semiconductor chip (semiconductor device) is taken out, the blade of the dicing device is in contact with the scribe line (scribe region) 203. It is possible to more reliably prevent the mechanical shock during dicing caused by the above from being applied to the chip region 202 or the chip region 202 from being damaged thereby.

  Furthermore, in the second embodiment, since the cap layers 225a and 225b are formed in the uppermost portions of the seal rings 204a and 204b, the following effects are obtained.

  11A shows the structure of the semiconductor device (semiconductor chip) shown in FIG. 10C (or FIG. 8A) on the upper side (passivation film (protective film) 209 formed on the uppermost wiring layer). 2 is a plan view seen from the upper side of FIG. 1 and shows one of a plurality of semiconductor chips 201A formed on a wafer (substrate) 201.

  As shown in FIG. 11A, a scribe region 203 is disposed so as to surround the chip region 202, and seal rings 204a and 204b (cap layers 225a and 225b) are provided at the boundary between the chip region 202 and the scribe region 203. Is not shown in the figure, so that it is doubled. The cap layers 225a and 225b formed on the uppermost portions of the seal rings 204a and 204b are formed by partially removing the opening of the passivation film 209 that continuously surrounds the chip region 202 (passivation film 209 is partially removed). Is provided). For this reason, the passivation film 209 formed in the chip region 202 and the passivation film 209 formed in the scribe region 203 are doubly divided by the cap layers 225a and 225b. That is, since the scribe region 203 and the chip region 202 are not connected via the passivation film 209, an impact received by the passivation film 209 in the scribe region 203 during dicing is propagated to the chip region 202 through the passivation film 209. There is hardly anything.

  FIG. 11B is a cross-sectional view of the chip surface portion taken along line C-C ′ of FIG.

  As shown in FIG. 11B, the cap layers 225a and 225b are formed in a double manner so as to penetrate through the passivation film 209 at the peripheral edge of the chip region 202. For this reason, it is possible to prevent the impact, stress, and the like received by the passivation film 209 in the scribe region 203 due to contact with the blade of the dicing apparatus during dicing from affecting the circuits, wiring structures, and the like in the chip region 202.

  Hereinafter, the seal ring structure shown in FIG. 8B, that is, a structure in which the seal vias constituting the seal rings 204a and 204b branch into at least two or more in the same interlayer insulating film will be described in detail. In FIG. 8B, the same components as those in FIG. 8A are denoted by the same reference numerals, and description thereof is omitted.

  The seal ring structure shown in FIG. 8B is different from the seal ring structure shown in FIG. 8A in that the seal vias constituting the seal rings 204a and 204b branch into at least two or more in the same interlayer insulating film. This is the point.

  Specifically, the inner first seal ring 204a of the double structure of the seal ring (first seal ring) 204a and the seal ring (second seal ring) 204b is formed on the first interlayer insulating film 205. In place of the first seal via 221a, seal vias 221a1 and 221a2 respectively connected to the conductive layer 220a are provided. In the third interlayer insulating film 207, the first seal via is replaced with the second seal via 223a. Seal vias 223a1 and 223a2 connected to the wiring 222a are provided, and seal vias 224a1 and 224a2 connected to the seal vias 223a1 and 223a2 instead of the third seal via 224a are provided in the fourth interlayer insulating film 208, respectively. Is provided. The upper portions of the seal vias 221a1 and 221a2 are connected to the first seal wiring 222a, and the upper portions of the seal vias 224a1 and 224a2 are connected to the cap layer (first cap layer) 225a.

  Further, for the second seal ring 204b adjacent to and outside the first seal ring 204a, the first interlayer insulating film 205 is connected to the conductive layer 220b instead of the first seal via 221b. 221b1 and 221b2 are provided, seal vias 223b1 and 223b2 connected to the first seal wiring 222b, respectively, are provided in the third interlayer insulating film 207 instead of the second seal via 223b, and The fourth interlayer insulating film 208 is provided with seal vias 224b1 and 224b2 connected to the seal vias 223b1 and 223b2, respectively, instead of the third seal via 224b. The upper portions of the seal vias 221b1 and 221b2 are connected to the first seal wiring 222b, and the upper portions of the seal vias 224b1 and 224b2 are connected to the cap layer (second cap layer) 225b.

  As described above, the seal rings 204a and 204b shown in FIG. 8B have a structure in which a plurality of seal vias (or a stacked structure thereof) are bundled by at least one seal wiring. For this reason, even if the width | variety (thickness) of each seal | sticker via is small, since they are bundled, the big intensity | strength can be given as the whole seal ring. Therefore, even when mechanical impact or stress is applied to the scribe region 203 during dicing, the seal ring 204a or 204b is broken or a part of the seal ring 204a or 204b (that is, one of the branched seal vias). ) Damage to the chip region 202 can be prevented.

  Further, in the seal ring structure shown in FIG. 8B, by selectively branching the seal vias constituting the seal rings 204a and 204b into two, three, four or more for each interlayer insulating film, a chip region is obtained. The protection function 202 can be further improved. That is, it is possible to more reliably prevent the impact and stress during dicing from propagating into the chip region 202.

  Further, according to the seal ring structure shown in FIG. 8 (b), even if the outer second seal ring 204b is broken, the second seal ring is the same as the seal ring structure shown in FIG. 8 (a). If the shape of the first seal ring 204a having a structure electrically insulated from 204b is maintained without being broken, contaminants such as moisture and mobile ions can enter the chip region 202. Thus, it is possible to prevent a decrease in reliability of the semiconductor device.

  Further, in the seal ring structure shown in FIG. 8B, a structure in which two seal vias are branched from one seal wiring is used. Instead, three or more seal vias are provided from one seal wiring. A branched structure may be used. That is, the number of seal vias to be branched may be appropriately selected according to the margin in the layout of the chip region 202 or the strength of the film (interlayer insulating film).

  Note that in the seal rings 204a and 204b shown in FIGS. 8A and 8B, a chip region in which elements are formed instead of a structure in which at least two or more seal vias are continuously stacked. Similar to the wiring structure in which the vias and the wirings are alternately stacked in 202, the same effect as that of the present embodiment can be obtained by using the structure in which the sealing vias and the sealing wirings are alternately stacked. However, if the seal ring is configured using the seal wiring, the width of the seal ring becomes thicker than when the seal via is used. Therefore, it is necessary to decide whether to use the seal wiring in consideration of the layout of each wiring layer. Is preferred.

  Further, in this embodiment, the wiring structure is formed in the interlayer insulating film stacked in four layers, but the number of layers of the interlayer insulating film is not limited to four layers, and may be less than four layers depending on the chip structure. It goes without saying that there may be many.

  In the present embodiment, Cu is used as the conductive material constituting the seal rings 204a and 204b. However, the present invention is not limited to this, and the seal rings 204a and 204b are configured using at least one of W, Al, and Cu. May be. In this way, the seal rings 204a and 204b can be formed from the same material as the wiring and via formed in the chip region 202 of the semiconductor device.

  In the present embodiment, the conductive material constituting the cap layers 225a and 225b is not particularly limited. However, when the material is Al, the seal rings 204a and 204b (especially seal rings made of Cu) are surely corroded. Can be prevented.

  Further, in the present embodiment, when a plurality of seal vias are continuously laminated, for example, as in the seal ring structure shown in FIG. 8A or FIG. 8B, one of the upper layer seal vias or the lower layer seal vias. It is preferable to make this contact surface larger than the other contact surface. In this way, the contact margin can be improved.

(First Modification of Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first modification of the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 12A is a cross-sectional view of a semiconductor device according to this modification (a view showing a cross-sectional structure taken along line BB ′ in FIG. 7).

  The seal ring structure of this modification shown in FIG. 12A is different from the seal ring structure of the second embodiment shown in FIG. 8A in that the inner seal ring (first seal ring) is different. The cap layer (first cap layer) 225a is not provided on 204a. In other words, the passivation film 209 on the first seal ring 204a is not opened.

  Specifically, as shown in FIG. 12A, the semiconductor device of the present modification has a double structure of a seal ring similar to that of the second embodiment, of which the outer second Similar to the seal ring structure of the first embodiment shown in FIG. 2A, the seal ring 204b has a cap layer (second cap layer) 225b at the top, while the inner first seal ring 204a. Does not have a cap layer on top.

  Further, similarly to the seal ring structure of the second embodiment shown in FIG. 8A, both the first seal ring 204a and the second seal ring 204b of this modification are formed of a plurality of interlayer insulating films 205 to 209. It is formed in a laminated structure. Specifically, first seal vias 221a and 221b are formed on the conductive layers 220a and 220b provided on the substrate 201, respectively, and the first seal wirings 222a and 221b are respectively formed on the first seal vias 221a and 221b. 222b is formed. Also, second seal vias 223a and 223b are formed on the first seal wirings 222a and 222b, respectively, and third seal vias 224a and 224b are formed on the second seal vias 223a and 223b, respectively. Yes. Further, a passivation film 209 is formed on the third seal via 224a, while the passivation film 209 on the third seal via 224b, which is the uppermost portion of the outer second seal ring 204b, is opened. A cap layer 225b connected to the third seal via 224b is provided in the opening.

  According to this modification, the seal rings 204a and 204b are formed in a double manner so as to continuously surround the chip region 202. Therefore, when the semiconductor wafer (substrate) 201 is diced along the scribe region 203 and the completed semiconductor chip (semiconductor device) is separated and taken out, the blade of the dicing device contacts the scribe line (scribe region) 203. Thus, it is possible to more reliably prevent the mechanical impact and stress during dicing caused by the above from being applied to the chip region 202 or the chip region 202 from being damaged thereby.

  Further, according to this modification, the cap layer 225b penetrating the passivation film 209 is disposed on the outer second seal ring 204b. Therefore, the passivation film 209 in the chip region 202 and the passivation film 209 in the scribe region 203 are completely divided by the cap layer 225b and become discontinuous, so that the impact received by the scribe region 203 during dicing propagates to the chip region 202. This can be prevented.

(Second modification of the second embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second modification of the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 12B is a cross-sectional view of the semiconductor device according to this modification (a view showing a cross-sectional structure taken along the line BB ′ of FIG. 7).

  The seal ring structure of this modification shown in FIG. 12B is different from the seal ring structure of the second embodiment shown in FIG. 8B in that the inner seal ring (first seal ring) The cap layer (first cap layer) 225a is not provided on 204a. In other words, the passivation film 209 on the first seal ring 204a is not opened. That is, the semiconductor device of this modification has a double structure of a seal ring similar to that of the second embodiment, and the second seal ring 204b on the outer side is the second structure shown in FIG. Similar to the seal ring structure of the first embodiment, the cap layer (second cap layer) 225b is provided at the uppermost portion, while the inner first seal ring 204a does not have the cap layer at the uppermost portion.

  Further, the seal ring structure of this modification shown in FIG. 12B is different from the seal ring structure of the first modification of the second embodiment shown in FIG. And the seal vias constituting 204b have a branching structure.

  Specifically, the first seal via 221a and the first seal via 221b in the first interlayer insulating film 205 are divided into two first seal vias 221a1 and 221a2 and two branched first seal vias, respectively. It is formed as 221b1 and 221b2. Similarly, the second seal via 223a and the second seal via 223b in the third interlayer insulating film 207 are divided into two second seal vias 223a1 and 223a2 and two branched second seal vias 223b1 and 223b1, respectively. The third seal via 224a and the third seal via 224b formed as 223b2 in the fourth interlayer insulating film 208 are divided into two third seal vias 224a1 and 224a2 and two branched third seal vias, respectively. 224b1 and 224b2 are formed. A passivation film 209 is formed on each of the third seal vias 224a1 and 224a2, while the passivation film 209 on the third seal vias 224b1 and 224b2 which are the uppermost parts of the outer second seal ring 204b. Is opened, and a cap layer 225b connected to the third seal vias 224b1 and 224b2 is provided in the opening.

  According to this modification, in addition to the effects obtained by the first modification of the second embodiment shown in FIG. 12A, the following effects can be obtained. That is, since the seal vias constituting the seal rings 204a and 204b have a branched structure, the strength of the seal rings 204a and 204b can be further improved, and impurities and moisture can enter the chip region 201 from the outside. Can be prevented by the respective seal rings 204a and 204b.

(Third Modification of Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a third modification of the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 13 is a cross-sectional view of a semiconductor device according to this modification (a view showing a cross-sectional structure taken along line BB ′ of FIG. 7).

  The semiconductor device of this modification shown in FIG. 13 is different from the semiconductor device of the second embodiment shown in FIG. 8B in that the top of the substrate 201 in the chip region 202 in the vicinity of the seal rings 204a and 204b. Is provided with a transistor. Specifically, the gate electrode 233 is formed on the region surrounded by the element isolation 231 in the substrate 201 with the gate insulating film 232 interposed therebetween. An insulating sidewall 234 is formed on the side surface of the gate electrode 233. Active layers 210 serving as source / drain regions are provided on both sides of the gate electrode 233 in the substrate 201.

  Further, the seal ring structure of this modification shown in FIG. 12B is different from the seal ring structure of the second embodiment shown in FIG. 8B in the formation layer of the transistor described above. The first seal via 221a and the first seal via 221b in one interlayer insulating film 205 are formed as two first seal vias 221a1 and 221a2 and two branched first seal vias 221b1 and 221b2, respectively. It is that. Note that, similarly to the seal ring structure of the first modification of the second embodiment shown in FIG. 12A, a cap layer (first cap) is formed on the inner seal ring (first seal ring) 204a. Layer) 225a is not provided. In other words, the passivation film 209 on the first seal ring 204a is not opened.

  By the way, in recent years, as the chip size has been reduced, the distance from the location where the wafer is diced (scribe region) to the transistor closest to the location (hereinafter referred to as the closest transistor) has become shorter. Yes. Specifically, conventionally, when no element is arranged below the pad, the distance from the seal ring to the closest transistor (corresponding to the distance L in FIG. 13) is about 100 μm. On the other hand, in recent years, a layout in which elements are arranged on the lower side of the pad has been used, and accordingly, the distance L from the seal ring to the nearest transistor has been reduced to about 10 μm. As a result, the impact during dicing tends to propagate to the transistor, and the transistor is more likely to be damaged. On the other hand, since the transistor has a fine structure including a thin gate oxide film and the like, it is vulnerable to impacts, and therefore, a countermeasure for preventing damage during dicing is required for the transistor.

  Therefore, in this modification, the strength of the seal ring structure of the transistor formation layer is improved by using the above-described “seal via structure branched into two or more”. Specifically, in particular, the first insulating film 205a and 204b forming the seal rings 204a and 204b in the lowermost insulating film on the substrate 201, that is, in the first interlayer insulating film 205 which is a transistor forming layer including the gate electrode 233 and the like. By branching each of the seal via 221a and the first seal via 221b into two, each of the branched seal vias 221a1, 221a2, 221b1, and 221b2 functions as a barrier against an impact applied to the lowermost layer of the chip region 202. This can prevent damage to the transistor during dicing, thereby improving the yield of semiconductor device manufacturing.

  In this modification, the “sealed via structure branched into two or more” is used in the layer in which the fine transistor is provided, but the “sealed via structure branched into two or more” in other fine or delicate layers. May be used.

(Third embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings. The present embodiment corresponds to each variation of the first and second embodiments.

  FIG. 14A is a diagram schematically showing a cross-sectional structure of the conventional semiconductor device shown in FIG. 19, and shows peripheral portions of two chip regions 2 sandwiching the scribe region 3. In FIG. 14A, some components are not shown, and the same components as those in FIG. As shown in FIG. 14A, accessory wiring 40 is provided in the interlayer insulating films 8 and 10 in the scribe region 3.

  FIG. 14B is a plan view corresponding to FIG. In FIG. 14B, the seal ring 4 on the lower side of the passivation film 11 is schematically shown by a thick broken line. As shown in FIG. 14B, in the conventional semiconductor device, the seal ring 4 is provided in a line along the scribe region 3.

  Next, FIG. 15A is a diagram schematically showing a cross-sectional structure of the semiconductor device according to the first embodiment shown in FIG. 2A, and shows two chip regions 102 sandwiching the scribe region 103. The periphery is shown. In FIG. 15A, some components are not shown, and the same components as those in FIG. As shown in FIG. 15A, accessory wiring 140 is provided in the interlayer insulating films 107 and 108 in the scribe region 103.

  FIG. 15B is a plan view corresponding to FIG. In FIG. 15B, the seal ring 104 having the cap layer 125 at the top is schematically shown by a thick solid line. As shown in FIG. 15B, in the semiconductor device of the first embodiment, the seal ring 104 is provided in a line along the scribe region 103.

  FIG. 16A to FIG. 16C show the plan configuration of the conventional semiconductor device shown in FIG. 14B and the plan configuration of the semiconductor device of the first embodiment shown in FIG. The plane structure of the variation of the semiconductor device which concerns on is shown. In FIGS. 16A to 16C, the seal ring 104 is schematically shown by a thick solid line.

  A feature of the planar configuration shown in FIG. 16A is that the seal ring 104 has rectangular irregularities when viewed from the upper side of the substrate 101 (that is, the passivation film 109).

  A feature of the planar configuration shown in FIG. 16B is that the seal ring 104 has triangular wave-shaped irregularities when viewed from above the substrate 101.

  A feature of the planar configuration shown in FIG. 16C is that a plurality of protrusions extending in the direction of the scribe region 103 are provided on the side of the seal ring 104. That is, the seal ring 104 has a plurality of protrusions in a direction perpendicular to the direction in which the scribe region 103 extends.

  Note that, in the cross-sectional configuration of the semiconductor device corresponding to each of FIGS. 16A to 16C, the formation position of the seal ring 104 changes in the horizontal direction or the formation width of the seal ring 104 varies depending on the location where the cross-section is observed. Except for the change, it is the same as the first embodiment shown in FIG. 15A or FIG.

  In addition, the semiconductor device manufacturing method corresponding to each of FIGS. 16A to 16C except that the mask pattern for forming the seal ring is changed according to each of FIGS. 16A to 16C. This is the same as in the first embodiment (see FIGS. 4A to 4D, FIGS. 5A to 5C, and FIGS. 6A to 6C).

  In the semiconductor device having the seal ring structure of this embodiment shown in any of FIGS. 16A to 16C, the barrier of the seal ring 104 that protects the chip region 102 is in the direction in which the scribe region 103 extends. It is provided not only in the parallel direction but also in the vertical direction and the oblique direction. For this reason, when the wafer is diced, the impact and stress caused by the contact between the blade of the dicing device and the film such as the passivation film 109 and the cracks of the wafer (substrate 101) caused by the impact and stress are caused by the seal ring 104. Proceeding along the side surface (the surface facing the scribe region 103) can be prevented.

  Next, FIG. 17A is a diagram schematically showing a cross-sectional structure of the semiconductor device according to the second embodiment shown in FIG. 8A, and shows two chip regions 202 sandwiching the scribe region 203. The periphery is shown. In FIG. 17A, some components are not shown, and the same components as those in FIG. As shown in FIG. 17A, accessory wiring 240 is provided in the interlayer insulating films 207 and 208 in the scribe region 203.

  FIG. 17B is a plan view corresponding to FIG. In FIG. 17B, the seal rings 204a and 204b provided with the cap layers 225a and 225b at the top are schematically shown by thick solid lines. As shown in FIG. 17B, in the semiconductor device of the second embodiment, the seal rings 204a and 204b are provided in double lines along the scribe region 203, respectively.

  In contrast to the planar configuration of the semiconductor device of the second embodiment shown in FIG. 17B, FIGS. 18A to 18C show the planar configurations of variations of the semiconductor device according to the present embodiment. 18A to 18C, the seal rings 204a and 204b are schematically shown by thick solid lines.

  A feature of the planar configuration shown in FIG. 18A is that the seal ring 204b on the scribe region 203 side has rectangular unevenness when viewed from the upper side of the substrate 201 (that is, the passivation film 209).

  A feature of the planar configuration shown in FIG. 18B is that the seal ring 204 b on the scribe region 203 side has triangular wave-shaped irregularities when viewed from above the substrate 201.

  A feature of the planar configuration shown in FIG. 18C is that a plurality of protrusions extending in the direction of the scribe region 203 are provided on the side of the seal ring 204b on the scribe region 203 side. In other words, the seal ring 204 b has a plurality of protrusions in a direction perpendicular to the direction in which the scribe region 203 extends.

  Note that the cross-sectional configuration of the semiconductor device corresponding to each of FIGS. 18A to 18C is such that the formation position of the seal ring 204b changes in the horizontal direction or the formation width of the seal ring 204b varies depending on where the cross-section is observed. Except for the change point, the second embodiment is the same as the second embodiment shown in FIG. 17 (a) or FIG. 8 (a).

  In addition, the semiconductor device manufacturing method corresponding to each of FIGS. 18A to 18C except that the mask pattern for forming the seal ring is changed according to each of FIGS. 18A to 18C. This is the same as in the second embodiment (FIGS. 9A to 9D and FIGS. 10A to 10C).

  According to the semiconductor device having the seal ring structure of this embodiment shown in any of FIGS. 18A to 18C, the same effect as that of the second embodiment due to the double seal ring structure is obtained. In addition, the following effects can be obtained. That is, the seal ring 204b on the scribe region 203 side of the seal rings 204a and 204b protecting the chip region 202 is not only in a direction parallel to the direction in which the scribe region 203 extends, but also in a vertical direction or an oblique direction. Is also provided. For this reason, when the wafer is diced, the impact and stress caused by the contact between the blade of the dicing device and the film such as the passivation film 209 and the cracks of the wafer (substrate 201) caused by them are caused by the seal ring 204b. Proceeding along the side surface (surface facing the scribe region 203) can be prevented.

  In addition, in the seal ring structure (double structure) of this embodiment shown in each of FIGS. 18A to 18C, the seal ring 204a having a line-like plane shape and other plane shapes other than the line shape are provided. The combination with the seal ring 204b having the above has been described. However, each of the seal rings 204a and 204b may have a planar shape other than a line shape (which may be the same or different). Alternatively, a triple or more seal ring structure in which at least the outermost seal ring has a planar shape other than a line shape may be used. However, when a plurality of seal rings having a planar shape other than a line shape are used, or when a triple or more seal ring structure is used, the width of the seal ring portion occupying the width of the semiconductor device (semiconductor chip) May become disadvantageous for downsizing of the semiconductor device. Accordingly, as in the seal ring structure of the present embodiment shown in each of FIGS. 18A to 18C, a seal ring having a line-like planar shape, and a seal ring having a plane shape other than the line shape, It is preferable to use a double seal ring structure in combination.

  As described above, according to each embodiment of the present invention, the seal via constituting the seal ring is integrally formed in the same interlayer insulating film as the wiring layer in accordance with the dual damascene wiring structure in the chip region. Therefore, the seal via is provided so as to penetrate through one interlayer insulating film without “seam”. Therefore, the number of “joints” can be reduced as a whole of the seal ring. Therefore, intrusion of impurities and the like from the “joint” can be further prevented as compared with a seal ring structure having many “joints”, and thus a stronger seal ring structure can be realized. That is, it is possible to suppress the propagation of impacts into the chip area during dicing and to prevent impurities and the like from entering the chip area from the outside.

  In each embodiment of the present invention, a cap layer is provided on the top of the seal ring, seal vias constituting the seal ring are branched, seal vias are formed in accordance with a dual damascene structure in the chip region, or a plurality of seal vias are formed. When the wafer is diced along the scribe area to take out individual chips, the chip area may be damaged or a part of the chip area may be damaged. Can be prevented more reliably. As a result, the impact received by the scribe area during dicing can be prevented from propagating into the chip area, thereby preventing damage to the IC circuit, wiring layer, etc. in the chip area, so that the yield of the semiconductor device (chip) can be reduced. Can be improved, and a highly accurate chip can be provided.

  In each embodiment of the present invention, the seal ring is provided at the peripheral portion of the chip region (near the boundary with the scribe region in the chip region), but the end portion of the semiconductor device (semiconductor chip) after dicing in the scribe region A seal ring may be provided in the remaining portion (that is, in the vicinity of the boundary with the chip region in the scribe region).

  As described above, the present invention relates to a semiconductor device having a seal ring formed so as to surround a chip region, and a method for manufacturing the semiconductor device. By applying the present invention, dicing is performed when a wafer is divided into individual chips. This is very useful because it is possible to prevent the chip (semiconductor device) side face from being cracked, cracked, etc. from propagating into the chip region.

It is a top view which shows a part of wafer with which the semiconductor device which concerns on the 1st Embodiment of this invention is provided. (A) And (b) is a figure which shows the variation of the cross-sectional structure of the AA 'line of FIG. 1 (cross-sectional structure of the semiconductor device edge part containing the seal ring part located in the peripheral part of a chip | tip area | region). (A) is a figure which shows the variation of the cross-section of AA 'line of FIG. 1 (cross-section of the semiconductor device end part containing the seal ring part located in the peripheral part of a chip | tip area | region), (b) is a figure. FIG. 3 is a diagram schematically illustrating a planar configuration of one via and a seal via provided in the same layer as the via in the structure illustrated in 2 (a) or 2 (b). (A)-(d) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view which shows a part of wafer with which the semiconductor device which concerns on the 2nd Embodiment of this invention is provided. (A) And (b) is a figure which shows the variation of the cross-section of the BB 'line | wire of FIG. 7 (cross-section of the semiconductor device edge part containing the seal ring part located in the peripheral part of a chip | tip area | region). (A)-(d) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A) is the top view which looked at the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention from the upper side, (b) is sectional drawing of the chip | tip surface part in CC 'line of (a). is there. (A) is sectional drawing of the semiconductor device which concerns on the 1st modification of the 2nd Embodiment of this invention, (b) is a semiconductor device which concerns on the 2nd modification of the 2nd Embodiment of this invention. FIG. It is sectional drawing of the semiconductor device which concerns on the 3rd modification of the 2nd Embodiment of this invention. (A) is the figure which showed typically the cross-section of the conventional semiconductor device shown in FIG. 19, (b) is a top view corresponding to (a). (A) is the figure which showed typically the cross-section of the semiconductor device which concerns on the 1st Embodiment of this invention shown to Fig.2 (a), (b) is a top view corresponding to (a). is there. (A)-(c) is a top view which shows the variation of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A) is the figure which showed typically the cross-section of the semiconductor device which concerns on the 2nd Embodiment of this invention shown to Fig.8 (a), (b) is a top view corresponding to (a). is there. (A)-(c) is a top view which shows the variation of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the conventional semiconductor device.

Explanation of symbols

101 Wafer (substrate)
102 Chip region 103 Scribe region 104 Seal ring 105 First interlayer insulating film 105a Via hole 105b Groove-shaped recess 106 Second interlayer insulating film 106a, 106b Wiring groove 107 Third interlayer insulating film 107a Via hole 107b Groove-shaped recess 107c Wiring groove 108 fourth interlayer insulating film 109 passivation film 110 active layer 111 first via 112 first wiring 113 second via 114 second wiring 115 third via 116 third wiring 117 pad electrode 120 conductive layer 121 First seal via 121a Branched first seal via 121b Branched first seal via 122 First seal wiring 123 Second seal via 123a Branched second seal via 123b Branched second seal via 124 First Third seal via 124a Branched third seal via 124b Branched third seal via 125 Cap layer 126 Second seal via 127 Second seal wiring 128 Third seal via 129 Third seal wiring 130 Resist film 140 Accessory wiring 201 Wafer (substrate)
201A Semiconductor chip 202 Chip area 203 Scribe area 204a, 204b Seal ring 205 First interlayer insulating film 205a Via hole 205b, 205c Groove-shaped recess 206 Second interlayer insulating film 206a, 206b, 206c Wiring groove 207 Third interlayer insulating film 207a Via hole 207b, 207c Groove-shaped recess 208 Fourth interlayer insulation film 209 Passivation film 210 Active layer 211 First via 212 First wiring 213 Second via 214 Second wiring 215 Third via 216 Third Wiring 217 Pad electrode 220a, 220b Conductive layer 221a, 221b First seal via 221a1, 221a2, 221b1, 221b2 Branched first seal via 222a, 222b First seal wiring 223a, 223b First Sealed vias 223a1, 223a2, 223b1, 223b2 Branched second seal vias 224a, 224b Third seal vias 224a1, 224a2, 224b1, 224b2 Branched third seal vias 225a, 225b Cap layer 230 Resist film 231 Element isolation 232 Gate insulating film 233 Gate electrode 234 Insulating side wall 240 Accessory wiring

Claims (6)

An element formed in a chip region of the substrate;
A laminated structure of a plurality of interlayer insulating films formed on the substrate;
Wiring formed in at least one of the plurality of interlayer insulating films in the chip region;
A plug formed in at least one of the plurality of interlayer insulating films in the chip region and connecting the element and the wiring, or connecting the wirings;
A seal ring formed so as to penetrate the laminated structure and continuously surround the chip area in the laminated structure of the plurality of interlayer insulating films in the peripheral portion of the chip area;
A protective film formed on a laminated structure of the plurality of interlayer insulating films provided with the wiring, the plug, and the seal ring;
At least one of the plurality of interlayer insulating films in the chip region is formed with a dual damascene wiring having a structure in which the wiring and the plug connected to the wiring are integrated.
The portion formed in the interlayer insulating film in which the dual damascene wiring is provided in the seal ring is configured integrally.
The seal ring surrounds the tip region more than twice,
The protective film has a first opening only on the outermost seal ring of the double or more seal rings, and a cap layer in contact with the outermost seal ring is formed in the first opening. A semiconductor device which is characterized by being made. At least a portion of the seal ring is embedded in a recess provided across one interlayer insulating film of the plurality of interlayer insulating films or at least two or more interlayer insulating films stacked on each other,
The semiconductor device according to claim 1, wherein an aspect ratio of the recess is 3 or more. 2. The semiconductor device according to claim 1 , wherein each of the two or more seal rings has two or more branch structures in at least one of the plurality of interlayer insulating films.   The semiconductor device according to claim 1, wherein the seal ring is made of at least one of W, Al, and Cu.   The semiconductor device according to claim 1, wherein the cap layer is made of Al.   The semiconductor device according to claim 1, wherein the protective film has a second opening on the wiring, and a pad electrode in contact with the wiring is formed in the second opening.

Images