CN101615579A - A kind of semiconductor plasma etching technology - Google Patents
A kind of semiconductor plasma etching technology Download PDFInfo
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- CN101615579A CN101615579A CN200910090173A CN200910090173A CN101615579A CN 101615579 A CN101615579 A CN 101615579A CN 200910090173 A CN200910090173 A CN 200910090173A CN 200910090173 A CN200910090173 A CN 200910090173A CN 101615579 A CN101615579 A CN 101615579A
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Abstract
The invention provides a kind of plasma etching industrial, comprising: dielectric layer runs through the etching step, and the process gas that described dielectric layer runs through the etching step comprises fluorine-based etching gas, first photoresistance protective gas and the diluent gas; In the silicon main etching step, the process gas in described silicon main etching step comprises main etching gas, carbon back accessory substance removal gas and the second photoresistance protective gas.In the preferred embodiment, described fluorine-based etching gas is CF
4Perhaps SF
6, the described first photoresistance protective gas is CH
2F
2Perhaps CHF
3Perhaps HBr, described diluent gas is He, Ar or N
2Described main etching gas is Cl
2, it is O that described carbon back accessory substance is removed gas
2, the described second photoresistance protective gas is HBr.The present invention can be in the semiconductor plasma etching, improves the sidewall steepness of pattern etching and avoids that fillet appears in the lower edge on the lines.
Description
Technical field
The present invention relates to the semiconductor fabrication process technical field, particularly relate to a kind of improved semiconductor plasma etching technology.
Background technology
Plasma etching (also claiming dry etching) is one of critical process during integrated circuit is made, and its objective is intactly mask pattern to be copied to silicon chip (wafer) surface.
The principle of plasma etching may be summarized to be following step: (1) under low pressure, reacting gas is under the exciting of radio-frequency power, produce ionization and form plasma (plasma is made up of charged electronics and ion), gas in the reaction cavity is under the bump of electronics, except being transformed into ion, can also absorbing energy and form a large amount of active group (Radicals); (2) active reactive group and the material surface that is etched form chemical reaction and form volatile reaction product; (3) reaction product breaks away from the material surface that is etched, and is extracted out cavity by vacuum system.
In present stage ICP commonly used (inductance coupling high, Inductive Coupled Plasma promptly reach the effect that strengthens plasma density by inductance coupling high) plasma etching machine, adopt pure CF4 usually as etching gas.For example, a typical etching process (recipe) can comprise that medium runs through etching step (BT) and silicon main etching step (ME) layer by layer, and wherein the BT etching step selects for use pure CF4 gas to carry out etching usually, and the ME etching step is adopted Cl usually
2And O
2Mist carry out etching.
With reference to Fig. 1, show the section Electronic Speculum result that the silicon chip section scanning after utilizing ESEM to the ICP plasma etching obtains, digital 156um among Fig. 1 and 158.4um represent the height of lines sidewall.Section wherein is to remove after the photoresistance, comprises the etching section of dielectric layer (silicon oxide layer) and silicon layer, and two one side of something are represented the sidewall profile of two ends of whole lines respectively about Fig. 1.Concrete, with reference to Fig. 2, show the etching result schematic diagram of certain lines, because whole lines can't occur in ESEM simultaneously, therefore, chosen the part of two frame of broken lines respectively and taken, two frame of broken lines are with regard to two and half figure about in the corresponding diagram 1, the section situation of two sidewalls about clearly showing respectively.From the electromicroscopic photograph of Fig. 1 as can be seen, the lines Sidewall angles after the prior art etching is straight inadequately, and also there is fillet in the upper edge of lines sidewall.
Need to prove that the hard between photoresistance broad covered area (being that open area is less) and photoresist layer and silicon layer is covered in the thin pattern etching of layer, above-mentioned etching defect then can be more obvious.Because the photoresistance broad covered area then in the etching process accessory substance of carbon containing more; be unfavorable for etching the steep section of angle; and hard is covered the thin top that is unfavorable for protecting the silicon lines of layer, thereby makes the lines edge occur fillet easily, brings difficulty thereby obtain desired result to etching.
Further, when the figure conduct as a result of aforesaid etching is used for zero layer sign (zeromark) of interlayer etching calibration, if its section is steep inadequately and have an edge fillet, then not only influence this etching result, and can further influence lithography calibration effect, the i.e. relative position relation of the figure (pattern) between influence layer and the layer.For example, under existing a lot of situations, need the integrated nearly high density transistor more than ten layers on the wafer, need to indicate the zone between layer and the layer and carry out lithography calibration by zero layer.With reference to Fig. 3, show the graphic structure that a kind of typical zero layer indicates the zone, it is made of four groups of mutually perpendicular lines, this zone usually symmetry be distributed in wafer edge (for example, apart from about edge 5mm).
In a word, need the urgent technical problem that solves of those skilled in the art to be exactly at present: how can be in the semiconductor plasma etching, the sidewall steepness of raising pattern etching and avoid that fillet appears in the lower edge on the lines.
Summary of the invention
Technical problem to be solved by this invention provides a kind of improved semiconductor plasma etching technology, and, lines edge steep to obtain do not have the pattern etching result of fillet.
In order to address the above problem, the invention discloses a kind of plasma etching industrial, comprising:
Dielectric layer runs through the etching step, and the process gas that described dielectric layer runs through the etching step comprises fluorine-based etching gas, first photoresistance protective gas and the diluent gas;
In the silicon main etching step, the process gas in described silicon main etching step comprises main etching gas, carbon back accessory substance removal gas and the second photoresistance protective gas.
Preferably, to run through the fluorine-based etching gas in etching step be CF to described dielectric layer
4Perhaps SF
6, the described first photoresistance protective gas is CH
2F
2Perhaps CHF
3Perhaps HBr, described diluent gas is He, Ar or N
2
Preferably, the main etching gas in described silicon main etching step is Cl
2, it is O that described carbon back accessory substance is removed gas
2, the described second photoresistance protective gas is HBr.
Preferably, the flow of described diluent gas is greater than the flow of fluorine-based etching gas, and the flow of described fluorine-based etching gas is greater than the flow of the first photoresistance protective gas; The flow of the described second photoresistance protective gas is greater than the flow of main etching gas, and the flow of described main etching gas is removed the flow of gas greater than the carbon back accessory substance.
Preferably; described dielectric layer is a silica; the technological parameter that then runs through the etching step is: chamber pressure is 7～15mT; last radio-frequency power is 300～400W; following radio-frequency power is 50～150W, and the processing time is 10～20s, and fluorine-based etching gas CF4 flow is 50～100sccm; the first photoresistance protective gas CH2F2 flow is 10～20sccm, and diluent gas He flow is 100～200sccm.
Preferably; the technological parameter in described silicon main etching step is: chamber pressure is 20～30mT; last radio-frequency power is 300～500W; following radio-frequency power is 30～100W; processing time is 30～40s; main etching gas Cl2 flow is 50～100sccm, and the second photoresistance protective gas HBr flow is 100～200sccm, and it is 3～10sccm that the carbon back accessory substance is removed gas O2 flow.
Preferably; described dielectric layer is a silica; the technological parameter that then runs through the etching step is: chamber pressure is 8mT; last radio-frequency power is 350W; following radio-frequency power is 120W, and the processing time is 15s, and fluorine-based etching gas CF4 flow is 60sccm; the first photoresistance protective gas CH2F2 flow is 20sccm, and diluent gas He flow is 100sccm.
Preferably; the technological parameter in described silicon main etching step is: chamber pressure is 20mT; last radio-frequency power is 400W; following radio-frequency power is 45W; processing time is 40s; main etching gas Cl2 flow is 50sccm, and the second photoresistance protective gas HBr flow is 200sccm, and it is 5sccm that the carbon back accessory substance is removed gas O2 flow.
Preferably, described plasma etching industrial is applied in the photoresistance coverage rate and surpasses entire wafer 90%, and in the pattern etching of hard thickness of dielectric layers smaller or equal to 0.05um between photoresist layer and silicon layer.
Preferably, described plasma etching industrial is applied in the etching in wafer zero layer sign zone.
Compared with prior art, the present invention has the following advantages:
In the plasma etching industrial of the present invention existing two step etchings are improved, in the BT etching gas in step, increased photoresistance protective gas and diluent gas, and also increased the photoresistance protective gas in the step at ME; At first, owing to this two step all passes through to increase the photoresistance protective gas, and increased selection ratio to photoresistance; reduce the lateral etching of photoresistance, thereby can help obtaining steep etching section, and the top of protection lines; avoid over etching, make the lines edge not be prone to fillet.
In addition, owing to can take away the carbon back accessory substance that in BT step etching, produces at the diluent gas that BT increased in the step, and then can prevent the carbon back accessory substance in side wall deposition, further guarantee to obtain steep etching section; Secondly, also can react the deposition that generates other gases and weaken the carbon back accessory substance, help obtaining steep etching section with the carbon back accessory substance at the oxygen of ME in the step.
Because above-mentioned improvement of the present invention, can guarantee to obtain the steep and edge of lines does not have the graphic result of fillet, therefore, and when the present invention is used for etching to zero layer expression zone, can improve the lithography calibration degree of each layer pattern greatly, reduce the lithography calibration deviation.
Description of drawings
Fig. 1 is section scanning obtains to the silicon chip behind the prior art ICP plasma etching a profile scanning Electronic Speculum photo as a result;
Fig. 2 is the etching result schematic diagram of certain lines;
Fig. 3 is the graphic structure schematic diagram that a kind of typical zero layer indicates the zone;
Fig. 4 is the object lesson flow chart of a kind of plasma etching industrial of the present invention;
Fig. 5 is that a kind of typical zero layer indicates regional film layer structure schematic diagram;
Fig. 6 carries out the resulting etching section of etching process of the present invention electromicroscopic photograph;
Fig. 7 is that the lithography calibration result behind employing prior art and the etching technics of the present invention contrasts situation map.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
With reference to Fig. 4, show the object lesson of a kind of plasma etching industrial of the present invention, it can comprise following two step etching processes:
Dielectric layer runs through the etching step 401, and the process gas that described dielectric layer runs through the etching step comprises fluorine-based etching gas, first photoresistance protective gas and the diluent gas;
In the silicon main etching step 402, the process gas in described silicon main etching step comprises main etching gas, carbon back accessory substance removal gas and the second photoresistance protective gas.
Because wafer also covers one deck hard dielectric layer on the base material silicon layer usually, for example, common hard dielectric layer can be SiO
2Perhaps SiN; Therefore, when carrying out plasma etching, need carry out dielectric layer earlier and run through the etching step 401, carry out the silicon main etching step 402 at the base material silicon layer then, obtain required figure.
Usually dielectric layer being run through etching step 401 also is referred to as the BT step, and the fluorine-based etching gas in its process gas can adopt CF
4(perhaps SF
6Deng), the first photoresistance protective gas among the present invention can adopt CH
2F
2, also can adopt CHF
3(perhaps HBr etc.), diluent gas can be He, Ar or N
2In one or more combinations.
The first photoresistance protective gas in the step 401, its main purpose are in order to protect photoresistance, to reduce the vertical and horizontal etching of photoresistance; The selected CH of the present invention
2F
2Perhaps CHF
3, be deposition property gas, can reduce the lateral etching of photoresistance preferably, for the present invention, help obtaining the fillet at preferable steep section and elimination lines edge.Need to prove that the selection of the first photoresistance protective gas is relevant with fluorine-based etching gas, fluorine-based etching gas difference, the first selected photoresistance protective gas also may be different.In a preferred embodiment of the invention, the flow of the first photoresistance protective gas is less than the flow of fluorine-based etching gas.
Diluent gas in the step 401, its main purpose are in order to dilute and take away the carbon back accessory substance that produces in the chamber under etching reaction, because if more being deposited on the sidewall of carbon back accessory substance then is unfavorable for obtaining preferable steep section.The introducing of diluent gas can increase the total gas couette of reaction chamber, promptly under same chamber pressure, increased the flow velocity of gas in the chamber, can take away the carbon back accessory substance that is generated fast, prevent the lines side wall deposition of accessory substance, thereby help obtaining steep section at the Si base.Generally, chemical reaction can not take place in diluent gas in chamber, is good with inert gas, for example, and He, Ar or N
2Or the like.Preferably, in order to improve dilution effect, better the carbon back accessory substance is taken away, the flow of the diluent gas in the step 401 can be greater than the flow of fluorine-based etching gas.
Usually the silicon main etching step 402 also is referred to as the ME step, the main etching gas in its process gas can adopt Cl
2, the second photoresistance protective gas among the present invention can adopt HBr, and the carbon back accessory substance is removed gas and is selected O for use
2
The second photoresistance protective gas in the step 402, its main purpose are in order to protect photoresistance, to reduce the vertical and horizontal etching of photoresistance; The selected HBr of the present invention is with respect to etching gas Cl
2, as deposition property gas, can reduce the lateral etching of photoresistance preferably, for the present invention, help obtaining the fillet at preferable steep section and elimination lines edge.In a preferred embodiment of the invention, the flow of the second photoresistance protective gas is greater than the flow of main etching gas.
Carbon back accessory substance in the step 402 is removed gas O
2, its main purpose is to be used for generating gas with the carbon back byproduct reaction, and flows out from chamber, can reduce the carbon back accessory substance in the chamber like this, weakens the deposition of carbon back accessory substance on sidewall, helps obtaining steep section.Need to prove that the carbon back accessory substance is removed gas O
2Flow with respect to main etching gas Cl
2Flow to lack because the O in the process gas
2Flow when big, can increase the etch rate of process gas to photoresistance, be unfavorable for obtaining desirable etching section.Preferably, the carbon back accessory substance is removed gas O
2Flow less than the flow of the second photoresistance protective gas, and less than main etching gas.
Provide the process parameters range that is adopted when the specific embodiment of the invention is carried out etching below:
The technological parameter that dielectric layer runs through the etching step 401 is: chamber pressure is 7～15mT, and last radio-frequency power is 300～400W, and following radio-frequency power is 50～150W, and the processing time is 10～20s, fluorine-based etching gas CF
4Flow is 50～100sccm, the first photoresistance protective gas CH
2F
2Flow is 10～30sccm, and diluent gas He flow is 100～200sccm.
The technological parameter in silicon main etching step 402 is: chamber pressure is 20～30mT; last radio-frequency power is 300～500W; following radio-frequency power is 30～100W; processing time is 30～40s; main etching gas Cl2 flow is 50～100sccm; the second photoresistance protective gas HBr flow is 100～250sccm, and it is 3～10sccm that the carbon back accessory substance is removed gas O2 flow.
The first photoresistance protective gas wherein is with CH
2F
2For example describes, the second photoresistance protective gas is that example describes with HBr.Need to prove, in the description in front, roughly provided in each processing step the flow-rate ratio between the different process gas component, but for concrete component ratio, because need be according to the difference on the different chamber hardware designs, to choose best process gas composition ratio, can't provide accurate control ratio by Theoretical Calculation or actual tests at this.
Also need to prove; because the present invention has increased by first photoresistance protective gas and the diluent gas at BT in the step; increased by the second photoresistance protective gas at ME in step, therefore, the process gas total flow in the etching of the present invention may be greater than the process gas flow of prior art.Industrialized plasma etch chamber pressure can be regulated by the pendulum valve between chamber and molecular pump (the pendulum valve can be determined an aperture position at standard-sized sheet and full cut-off), because the rotating speed of molecular pump is generally fixing, so when leading to the interior gas flow of chamber not simultaneously, thereby can control the gas outlet flow by the aperture of pendulum valve and control to the pressure that sets, though process gas flow promptly of the present invention has increased, the present invention program's chamber pressure remains in the gas flow scope that provides can stablize control.
In fact, in common wafer figure plasma etching process, prior art also can guarantee steep lines and no fillet basically, though the present invention's effect can be better than prior art, difference is not very big.But in the etching of some special circumstances, prior art just can't guarantee steep lines, and fillet can appear in the lines edge, for example, at photoresistance coverage rate wide (surpassing entire wafer 90%), and the hard between photoresist layer and silicon layer is covered layer thickness and is approached in the pattern etching of (smaller or equal to 0.05um), and improvement degree of the present invention will be very obvious.A typical case of above-mentioned etching situation uses and is exactly zero layer of regional etching of sign, and is concrete: the film layer structure after the regional graph exposure of zero layer sign develops usually is: photoresistance thickness
The silica medium layer
(smaller or equal to 0.05um), and most of area is all covered (surpassing entire wafer 90%) on the entire wafer by photoresistance
Provide an object lesson of the present invention below, it is applied in zero layer and indicates in the etching in zone, hard dielectric layer on the base material silicon layer is that silicon oxide layer is (with reference to Fig. 5, show a kind of typical zero layer and indicate regional film layer structure schematic diagram, comprise photoresist layer, silicon oxide layer and silicon layer), then in the etching technics:
The technological parameter that silica runs through etching step BT is: chamber pressure is 8mT; last radio-frequency power is 350W; following radio-frequency power is 120W; processing time is 15s; fluorine-based etching gas CF4 flow is 60sccm; the first photoresistance protective gas CH2F2 flow is 20sccm, and diluent gas He flow is 100sccm.
The silicon main etching step technological parameter of ME is: chamber pressure is 20mT; last radio-frequency power is 400W; following radio-frequency power is 45W; processing time is 40s; main etching gas Cl2 flow is 50sccm; the second photoresistance protective gas HBr flow is 200sccm, and it is 5sccm that the carbon back accessory substance is removed gas O2 flow.
With reference to Fig. 6, show and adopt above-mentioned technological parameter to carry out the resulting etching section of etching process of the present invention electromicroscopic photograph, from Fig. 6 and Fig. 1 relatively be easy to find out, use the section that obtains after the etching of the present invention, lines angle steep (Sidewall angles is greater than 85 degree), and the lower edge does not all have fillet on the lines; Therefore, zero layer that adopts etching of the present invention to obtain indicates, and can improve the lithography calibration rate between multilayer.
Next because fluoro-gas can produce fluorine-containing active group after the ionization in plasma cavity, thereby corrodes the parts in the chamber especially quartz member, thereby has shortened the useful life of these parts.From top specific embodiment as can be seen, though in process gas of the present invention, also adopted fluoro-gas, but for the diluent gas that has increased big flow in the process gas of BT in the step, so can reduce the damage ability of fluoro-gas to the chamber interior part, and the time in BT step is shorter, can further reduce the infringement of fluoro-gas to the chamber interior part.
Moreover from top example as can be seen, the processing time of ME in this routine silicon main etching step is 40 seconds, and the preferable processing time scope of the present invention is: 30～40s, the processing time of the ME under the common etch technological condition: 50～70s.Obviously, reduction in processing time can be enhanced productivity greatly.Just because of the interpolation of the present invention by photoresistance protective gas and adaptation ratio; make the pattern and the etching depth of etching section can obtain preferable control; therefore; under the situation that guarantees etching section quality; tend to adopt short etch period by regulating power, to enhance productivity.
With reference to Fig. 7, provide the lithography calibration result who adopts behind prior art and the etching technics of the present invention and contrasted situation, wherein, prior art and the present invention have all got 6 repeated sample.In Fig. 7, ordinate is a deviate, and unit is um, and wherein 0um is an optimal value.In Fig. 7, the polygon on the left side is represented the deviation profile scope of each repeated sample under the prior art, the deviation profile scope of each repeated sample after the etching of the present invention is used in the right expression, as can be seen, the prior art lower deviation distribute be roughly+0.01um is to-0.02um, and uses deviation profile after the etching of the present invention basically near 0um.From the comparison of Fig. 7, be easy to find out that the present invention reduces deviation and has significant effect for the lithography calibration effect that improves interlayer, deviate is generally at ± 0.03um.
More than to a kind of semiconductor plasma etching technology provided by the present invention, be described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1, a kind of plasma etching industrial is characterized in that, comprising:
Dielectric layer runs through the etching step, and the process gas that described dielectric layer runs through the etching step comprises fluorine-based etching gas, first photoresistance protective gas and the diluent gas;
In the silicon main etching step, the process gas in described silicon main etching step comprises main etching gas, carbon back accessory substance removal gas and the second photoresistance protective gas.
2, etching technics as claimed in claim 1 is characterized in that,
Described fluorine-based etching gas is CF
4Perhaps SF
6, the described first photoresistance protective gas is CH
2F
2Perhaps CHF
3Perhaps HBr, described diluent gas is He, Ar or N
2
3, etching technics as claimed in claim 1 is characterized in that,
Described main etching gas is Cl
2, it is O that described carbon back accessory substance is removed gas
2, the described second photoresistance protective gas is HBr.
4, etching technics as claimed in claim 1 is characterized in that,
The flow of described diluent gas is greater than the flow of fluorine-based etching gas, and the flow of described fluorine-based etching gas is greater than the flow of the first photoresistance protective gas;
The flow of the described second photoresistance protective gas is greater than the flow of main etching gas, and the flow of described main etching gas is removed the flow of gas greater than the carbon back accessory substance.
5, etching technics as claimed in claim 2 is characterized in that,
Described dielectric layer is a silica; the technological parameter that then runs through the etching step is: chamber pressure is 7～15mT; last radio-frequency power is 300～400W; following radio-frequency power is 50～150W; processing time is 10～20s; fluorine-based etching gas CF4 flow is 50～100sccm, and the first photoresistance protective gas CH2F2 flow is 10～20sccm, and diluent gas He flow is 100～200sccm.
6, etching technics as claimed in claim 3 is characterized in that,
The technological parameter in described silicon main etching step is: chamber pressure is 20～30mT; last radio-frequency power is 300～500W; following radio-frequency power is 30～100W; processing time is 30～40s; main etching gas Cl2 flow is 50～100sccm; the second photoresistance protective gas HBr flow is 100～200sccm, and it is 3～10sccm that the carbon back accessory substance is removed gas O2 flow.
7, etching technics as claimed in claim 2 is characterized in that,
Described dielectric layer is a silica; the technological parameter that then runs through the etching step is: chamber pressure is 8mT; last radio-frequency power is 350W; following radio-frequency power is 120W; processing time is 15s; fluorine-based etching gas CF4 flow is 60sccm, and the first photoresistance protective gas CH2F2 flow is 20sccm, and diluent gas He flow is 100sccm.
8, etching technics as claimed in claim 3 is characterized in that,
The technological parameter in described silicon main etching step is: chamber pressure is 20mT; last radio-frequency power is 400W; following radio-frequency power is 45W; processing time is 40s; main etching gas Cl2 flow is 50sccm; the second photoresistance protective gas HBr flow is 200sccm, and it is 5sccm that the carbon back accessory substance is removed gas O2 flow.
9, etching technics as claimed in claim 1 is characterized in that,
Described plasma etching industrial is applied in the photoresistance coverage rate and surpasses entire wafer 90%, and in the pattern etching of hard thickness of dielectric layers smaller or equal to 0.05um between photoresist layer and silicon layer.
10, etching technics as claimed in claim 1 is characterized in that,
Described plasma etching industrial is applied in wafer zero layer and indicates in the etching in zone.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015021932A1 (en) * | 2013-08-16 | 2015-02-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Substrate etching method |
| TWI503889B (en) * | 2012-01-31 | 2015-10-11 | ||
| CN106504986A (en) * | 2015-09-07 | 2017-03-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of lithographic method of substrate |
| CN110211866A (en) * | 2019-05-20 | 2019-09-06 | 深圳市华星光电半导体显示技术有限公司 | A kind of method for etching plasma |
| CN111009472A (en) * | 2019-12-27 | 2020-04-14 | 华虹半导体(无锡)有限公司 | Method for manufacturing MOSFET device |
-
2009
- 2009-07-29 CN CN2009100901736A patent/CN101615579B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI503889B (en) * | 2012-01-31 | 2015-10-11 | ||
| WO2015021932A1 (en) * | 2013-08-16 | 2015-02-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Substrate etching method |
| CN106504986A (en) * | 2015-09-07 | 2017-03-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of lithographic method of substrate |
| CN110211866A (en) * | 2019-05-20 | 2019-09-06 | 深圳市华星光电半导体显示技术有限公司 | A kind of method for etching plasma |
| CN111009472A (en) * | 2019-12-27 | 2020-04-14 | 华虹半导体(无锡)有限公司 | Method for manufacturing MOSFET device |
| CN111009472B (en) * | 2019-12-27 | 2023-03-10 | 华虹半导体(无锡)有限公司 | Method for manufacturing MOSFET device |
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| CN101615579B (en) | 2012-04-25 |
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Address after: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016, building 2, block M5, East Jiuxianqiao Road, Chaoyang District, Beijing Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |
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