CN101588124B - Wave-chasing current-limiting control method of diode mid-point clamping multilevel converter - Google Patents
Wave-chasing current-limiting control method of diode mid-point clamping multilevel converter Download PDFInfo
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Abstract
The invention discloses a wave-chasing current-limiting control method of a diode mid-point clamping multilevel converter. The wave-chasing current-limiting control method of the diode mid-point clamping multilevel converter is characterized in that a wave-chasing current-limiting circuit provides a time sequence control signal when a wave-chasing current-limiting enabling signal is valid so that two outer-side main power switch tubes of a multilevel converter brachium pontis are firstly forcefully switched off; and then, two inner-side main power switch tubes of the multilevel converter brachium pontis are forcefully switched off; the two inner-side main power switch tubes of the multilevel converter brachium pontis are firstly forcefully switched on for a first delay time, and one of the two inner-side main power switch tubes is forcefully switched off for a second delay time when the wave-chasing current-limiting enabling signal loses; and then, the two inner-side main power switch tubes and the two outer-side main power switch tubes normally output PWN driving signals. No matter whether the wave-chasing current-limiting enabling signal is valid or invalid, i.e., the inner-side main power switch tubes and the outer-side main power switch tubes are blocked or unblocked. The wave-chasing current-limiting control method of the diode mid-point clamping multilevel converter can ensure the stress balance of the main power switch tubes, improves the reliability of the circuit, decreases the device cost and enhances the product competitive strength.
Description
Technical field
The present invention relates to wave limiting, especially relate to a kind of diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method.
Background technology
In order to improve the input power factor of Switching Power Supply; Rectifier generally all is provided with circuit of power factor correction, causes busbar voltage than higher, and in order to reduce the voltage stress of switching tube; Normally adopt a plurality of master power switch pipe series connection and combine the suitably multi-level converter of control; With the voltage withstand class of effective reduction device, reduce output voltage or current harmonics composition, save the cost of filter.In view of multi-level converter particular performances advantage, multi-level converter obtains application more and more widely in a plurality of fields such as medium voltage frequency converter, UPS, DC/DC converting power source.
Wave limiting is the measure of Switching Power Supply a kind of protection switch pipe commonly used; To be applied as example in the inverter; System's testing circuit detects the electric current that flows through main power inverting switching tube in real time, at shock load or generation output short-circuit, when detecting electric current greater than setting threshold; The comparison circuit that is used for comparison produces wave limiting and enables (protection) signal, and system blocks main power inverting switching tube driving pulse immediately and protects the inverse switch pipe; When the electric current that flows through main power inverting switching tube drops to setting threshold when following, main power inverting switching tube driving pulse is blocked in cancellation again, main power inverting switching tube by controller by concrete control method control.Said wave limiting function realizes that by the wave limiting circuit position of wave limiting circuit in application system is as shown in Figure 1 usually.
Adopt the multi-level converter of a plurality of master power switch pipe series systems, require each master power switch pipe all to press, solution commonly used comprises diode neutral point clamp method, striding capacitance clamp method, and most widely used is diode neutral point clamp type method.Control method of the present invention is relevant with this neutral point clamp type multi-level converter.
The main circuit schematic diagram of the single-phase three-level converter of diode neutral point clamp type is as shown in Figure 2.Fig. 3 is the drive signal waveform figure of a kind of drive scheme commonly used of Fig. 2 main circuit.Controller has two kinds to drive a wave mode; Said ripple is meant that controller sends the PWM drive signal according to drive scheme; Through the following two kinds combinations of sending out wave modes, make among Fig. 2 the controlled output of B point have three kinds of current potential :+E/2, N ,-E/2, the i.e. origin of so-called " three level " title.
First kind is sent out wave mode is outside master power switch pipe Q1 and inboard master power switch pipe Q3 complementary modulation; Inboard main power inverting switching tube Q3 signal is generated by outside master power switch pipe Q1 anti-phase; The two has the dead band; Inboard master power switch pipe Q2 is in normal open state, and outside master power switch pipe Q4 is in normal off status.When the master power switch pipe Q1 conducting of the outside, since also conducting of inboard master power switch pipe Q2, B point output potential+E/2 among Fig. 2; When outside master power switch pipe Q1 turn-offs, since inboard master power switch pipe Q3 and Q2 conducting, B point output potential N.
Second kind is sent out wave mode is inboard master power switch pipe Q2 and outside master power switch pipe Q4 complementary modulation, and inboard master power switch pipe Q3 pipe is in normal open state, and outside master power switch pipe Q1 is in normal off status.When the master power switch pipe Q4 conducting of the outside, and since also conducting of inboard master power switch pipe Q3, B point output potential-E/2 among Fig. 2, when outside master power switch pipe Q4 turn-offs, since inboard master power switch pipe Q3 and Q2 conducting, B point output potential N.
Yet this most widely used diode neutral point clamp type three-level converter is when wave limiting is protected, and each master power switch tube voltage stress can occur is the off state voltage imbalance problem.The applicant's the CN101051794A of patent formerly disclosed " a kind of control device of converter and driving method " has proposed a kind of protection control method; It is characterized in that: said protective circuit is connected on the prime of a delay circuit, is used to block the control signal of delay circuit prime.But, still have each main power inverting switch tube voltage unequal power distribution problem.
Fig. 4 is the single-phase three-level inverter main circuit of a kind of practicality of Fig. 2.Inboard main power inverting switching tube Q2, the main power inverting switching tube of the Q3 and outside Q1, Q4 exist intrinsic junction capacitance C2, C3, C1, C4 respectively in actual the use; Clamping diode D5, D6 are parallel with by absorption resistance R5 respectively, absorb capacitor C 5 and absorption resistance R6, absorb the RC absorption circuit that capacitor C 6 is composed in series, and absorb capacitor C 5, C6 numerical value usually much larger than junction capacitance C1, C2, C3, C4.In the electric current positive direction shown in Fig. 4 arrow, when the wave limiting enable signal finishes, in during main power inverting switching tube Q2 conducting, B point current potential rises to the N current potential from monolateral bus current potential-E/2 rapidly.Junction capacitance C3, C4 are recharged a period of time, if subsequently by former scheme conducting be the outside main power inverting switching tube Q1, B point current potential can rise to monolateral bus current potential+E/2 rapidly again.Absorption capacitor C 6, junction capacitance C3, C4 are recharged together like this; Owing to absorb capacitor C 6 numerical value much larger than junction capacitance C3, C4; The voltage of junction capacitance C4 charging is very low, and junction capacitance C3, C4 dividing potential drop are very unequal, causes junction capacitance C3 voltage at this moment will be far longer than monolateral bus current potential E/2; Be that the voltage stress that inboard main power inverting switching tube Q3 bears is far longer than monolateral bus current potential E/2, so just lost the advantage of three-level converter.Monolateral bus current potential E/2=405V in experiment, i.e. positive and negative busbar current potential E:810V is C6 when being taken as 2200pf at the absorption electric capacity of D6, the voltage stress on the inboard main power inverting switching tube Q3 reaches 659V, obvious voltage stress imbalance problem occurs.
Summary of the invention
Technical problem to be solved by this invention is to remedy the defective that above-mentioned prior art exists; The CN101051794A of patent formerly to the applicant makes improvement; A kind of diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method is proposed; The wave limiting enable signal effectively with invalid promptly block and cancel block in outside during the master power switch pipe, can both guarantee that each master power switch tube voltage stress is the off state voltage balance.
Technical problem of the present invention solves through following technical scheme.
This diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method detects the electric current that flows through the master power switch pipe in real time by system's testing circuit, and realizes the wave limiting function by the wave limiting circuit.
The characteristics of this diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method are:
When shock load or generation output short-circuit; And master power switch tube current detected value is greater than the current protection threshold value of the wave limiting of setting; The comparison circuit that is used for comparison produces the wave limiting enable signal when effective; The wave limiting circuit provides timing control signal to force earlier two outside master power switch pipes of multi-level converter brachium pontis are turn-offed; Force two inboard master power switch pipes of multi-level converter brachium pontis are turn-offed, the time interval that interior outside master power switch pipe is forced to turn-off guarantees that inboard master power switch Guan Buhui takes place than the situation that outside master power switch pipe turn-offs earlier because of the drive signal transmission delay again.If inboard main power tube turn-offs earlier, can cause each master power switch tube voltage unequal power distribution.Time interval design load is relevant with physical circuit drive signal transmission delay, circuit elements device and master power switch tube device dispersiveness etc.
The wave limiting enable signal disappear be saltus step be the wave limiting enable signal invalid after; The wave limiting circuit provides timing control signal to force first time of delay of two inboard master power switch pipes conducting with the multi-level converter brachium pontis earlier; Force again one of two inboard master power switch pipes were turn-offed for second time of delay, normally export the PWM drive signal to two inboard master power switch pipes and two outside master power switch pipes subsequently.
Adopt said method of the present invention can avoid the reason of main power inverting switching tube Q1, Q2, Q3 and Q4 voltage stress imbalance problem among Fig. 4 to be: when inductive current is the positive direction shown in Fig. 4 arrow; And when the multi-level converter controller is in first kind wave mode; In first time of delay with two inboard master power switch pipe Q2 and Q3 conducting simultaneously; The intrinsic junction capacitance C4 of outside master power switch pipe Q4 will be charged to E/2; During outside master power switch pipe Q1 conducting subsequently, the intrinsic junction capacitance C3 of inboard master power switch pipe Q3 also is charged to E/2, and the voltage of intrinsic like this junction capacitance C4 is just by clamp; The voltage of inboard master power switch pipe Q3 and outside master power switch pipe Q4 all is E/2, and voltage stress distributes equalization promptly to realize the off state voltage balance.Send out under other operating modes of wave mode and inductive current direction combination effective too in difference.
Technical problem of the present invention solves through following further technical scheme.
The current protection threshold value of said wave limiting is less than the maximum current of switching tube tolerance, with the protection switch pipe.
Whether the wave limiting enable signal that said comparison circuit produces effectively need be confirmed, to avoid the wave limiting enable signal because outside electromagnetic interference starts the wave limiting function by error.Only under the wave limiting enable signal can not receive the prerequisite of outside electromagnetic interference, just can cancel and whether effectively confirming.
The conducting of said two inboard master power switch pipes is preferably 2 μ s first time of delay.
One of said two inboard master power switch pipes turn-off and are preferably 1 μ s second time of delay.
The wave limiting circuit that said wave limiting circuit comprises the wave limiting circuit be made up of discrete component, realized by microcontroller, the wave limiting circuit of forming by programming device.
Said microcontroller comprises single-chip microcomputer, digital signal processor (Digital Signal Processor is called for short DSP).
Said programming device comprises CPLD (Complex ProgrammableLogic Device is called for short CPLD), field programmable gate array (Field Programmable GateArray is called for short FPGA).
The input signal of said wave limiting circuit comprises the wave limiting enable signal and the drive signal of each master power switch pipe of being produced by the multi-level converter controller, and single phase system is four drive signals, and three-phase system is 12 drive signals.
The input signal of said wave limiting circuit also comprises the wave limiting function auxiliary signal that is produced by the multi-level converter controller; Which in two inboard master power switch pipes concrete pressure turn-off in said second time of delay, and be relevant with said wave limiting function auxiliary signal.
The beneficial effect of the present invention and prior art contrast is:
The wave limiting enable signal effectively with invalid promptly block and cancel block in outside during the master power switch pipe; Control method of the present invention can both guarantee that each master power switch tube voltage stress is the off state voltage balance; Thereby improve the reliability of circuit, reduce device cost, improve product competitiveness.
Description of drawings
Fig. 1 is the position view of wave limiting circuit in application system;
Fig. 2 is the main circuit schematic diagram of the single-phase three-level converter of diode neutral point clamp type;
Fig. 3 is the drive signal waveform figure of a kind of drive scheme commonly used of Fig. 2 main circuit;
Fig. 4 is a kind of single-phase three-level inverter main circuit diagram of practicality;
Fig. 5 is the system block diagram of the specific embodiment of the invention;
Fig. 6 is the system sequence figure of the specific embodiment of the invention.
Embodiment
The contrast accompanying drawing combines embodiment that the present invention is further described below.
A kind of single-phase diode neutral point clamp type three-level inverter Wave-chasing current-limiting control method of this embodiment is like Fig. 5, shown in 6.
Fig. 5 is the system block diagram of the specific embodiment of the invention; The input signal of the wave limiting control circuit among Fig. 5 comprises that the OC wave limiting enables (protection) signal, the drive signal of four master power switch pipes being produced by the multi-level converter controller, and wave limiting function auxiliary signal DIR.
The output signal of wave limiting control circuit through after the power tube gate drive circuit of level deliver to the gate pole of each master power switch pipe of main circuit of multi-level converter.
But the wave limiting function of this embodiment generates through coding and downloads to CPLD behind the programming file and realize that system sequence figure is as shown in Figure 6.The CPLD program comprises following 5 steps:
Step 1: if OC wave limiting enable signal significant level keeps 1 μ s; Confirm that promptly the wave limiting enable signal is effective, then wave limiting begins action, blocks the main power inverting switching tube in the outside and drives and the 0.5 μ s that delays time; Otherwise the master power switch pipe drives keeps original state;
Step 2: if time-delay 0.5 μ s finishes in the step 1, then block inboard main power inverting switching tube and drive, otherwise the master power switch pipe drives keeps original state;
Step 3:, and not in step 1 and step 2 are carried out the time, force the inboard main power inverting switching tube of conducting to drive 2 μ s, otherwise the master power switch pipe drives keeps original state if the saltus step of OC wave limiting enable signal is invalid;
Step 4: finish if force the inboard main power inverting switching tube of conducting to drive 2 μ s in the step 3; Then force to turn-off a certain inboard master power switch pipe according to wave limiting function auxiliary signal DIR and drive 1 μ s, other master power switch pipes drive keeps original state;
Step 5: drive 1 μ s end if force to turn-off a certain inboard master power switch pipe in the step 4; Wave limiting function stop then, the drive signal of the master power switch pipe that the multi-level converter controller produces directly send the back level main power inverting switching tube gate drive circuit.
Following map 6 further specifies the course of work of the wave limiting of this embodiment:
The time interval of t1-t2 is 1 μ s among Fig. 6, depends on that system design is to avoid OC wave limiting enable signal because outside electromagnetic interference starts the wave limiting function by error.Only can not receive under the prerequisite of outside electromagnetic interference at OC wave limiting enable signal, this time interval just can be cancelled, and whether the wave limiting enable signal generally need effectively be confirmed in the time interval of t1-t2; The time interval of t2-t3 is 0.5 μ s, also depends on system design, requires to guarantee that inboard master power switch pipe Q2 and Q3 can not take place than the situation of outside master power switch pipe Q1 and Q4 shutoff earlier because of the drive signal transmission delay; The time interval of t4-t5 is 2 μ s; Relevant with selected power tube type with power tube gate leve drive circuit, should be able to guarantee under the above-mentioned said problem operating mode the last voltage that can set up E/2 of intrinsic junction capacitance C1, C4 that main power inverting switching tube Q1 in the outside and Q4 exist respectively in this blanking time; The time interval of t5-t6 is 1 μ s, is artificial " dead band " time period of setting, and to prevent main power inverting switching tube Q1, Q2 and Q3 conducting simultaneously or main power inverting switching tube Q2, Q3 and Q4 conducting simultaneously, causes busbar short-circuit.
T1 constantly before, promptly under the normal condition during no wave limiting enable signal, CPLD directly sees the drive signal of four master power switch pipes of multi-level converter controller generation off.
At t1 constantly; Shock load or generation output short-circuit; And master power switch tube current detected value is greater than the current protection threshold value of the wave limiting of setting; The comparison circuit generation saltus step that is used for comparison is that the wave limiting enable signal of high level keeps 1 μ s, confirms that promptly the wave limiting enable signal is effective, to avoid OC wave limiting enable signal because outside electromagnetic interference starts the wave limiting function by error.
Through affirmation the wave limiting enable signal whether effectively the people be time of delay 1 during μ s to t2, the wave limiting circuit is forced earlier two outside master power switch pipe Q1 of multi-level converter brachium pontis and Q4 shutoff.
Be time of delay during to t3 through the people again, the wave limiting circuit is forced two inboard master power switch pipe Q2 of brachium pontis and Q3 shutoff again.
T3-t4 is in the time period, and OC wave limiting enable signal remains effective high level, and four main power inverting switching tube Q1, Q2, Q3 and Q4 all keep off state.
Rise during t4 the wave limiting enable signal disappear saltus step be the wave limiting enable signal invalid after; The saltus step of OC wave limiting enable signal is a low level, and the wave limiting circuit is forced earlier two inboard master power switch pipe Q2 of multi-level converter brachium pontis and Q3 conducting t4-t5 first time of delay.
At t5 constantly; If wave limiting function auxiliary signal DIR is a low level; Show the outside main power inverting switching tube Q1 and inboard main power inverting switching tube Q3 just in complementary modulation, the wave limiting circuit force again with two inboard master power switch pipe Q3 turn-off second time of delay t5-t6; If wave limiting function auxiliary signal DIR is a high level; Show inboard main power inverting switching tube Q2 and the outside main power inverting switching tube Q4 just in complementary modulation, the wave limiting circuit force again with two inboard master power switch pipe Q2 turn-off second time of delay t5-t6.
Wave limiting function stop after during t6; The drive signal of the master power switch pipe that the wave limiting circuit will be produced by the multi-level converter controller directly send the back level main power inverting switching tube gate drive circuit, and master power switch pipe Q1 and Q4 normally export the PWM drive signal outside two inboard master power switch pipe Q2 and Q3 and two.
Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (8)
1. a diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method detects the electric current that flows through the master power switch pipe in real time by system's testing circuit, and realizes the wave limiting function by the wave limiting circuit, it is characterized in that:
When shock load or generation output short-circuit; And master power switch tube current detected value is greater than the current protection threshold value of the wave limiting of setting; The comparison circuit that is used for comparison produces the wave limiting enable signal when effective; The wave limiting circuit provides timing control signal to force earlier two outside master power switch pipes of multi-level converter brachium pontis are turn-offed; Force two inboard master power switch pipes of multi-level converter brachium pontis are turn-offed, the time interval that interior outside master power switch pipe is forced to turn-off guarantees that inboard master power switch Guan Buhui takes place than the situation that outside master power switch pipe turn-offs earlier because of the drive signal transmission delay again;
The wave limiting enable signal disappear be saltus step be the wave limiting enable signal invalid after; The wave limiting circuit provides timing control signal to force first time of delay of two inboard master power switch pipes conducting with the multi-level converter brachium pontis earlier; Force again one of two inboard master power switch pipes were turn-offed for second time of delay, normally export the PWM drive signal to two inboard master power switch pipes and two outside master power switch pipes subsequently.
2. diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method as claimed in claim 1 is characterized in that:
The current protection threshold value of said wave limiting is less than the lowest high-current value of switching tube tolerance.
3. according to claim 1 or claim 2 diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method is characterized in that:
Whether the wave limiting enable signal that said comparison circuit produces effectively need be confirmed.
4. according to claim 1 or claim 2 diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method is characterized in that:
First time of delay of said two inboard master power switch pipes conducting is 2 μ s.
5. according to claim 1 or claim 2 diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method is characterized in that:
It is 1 μ s that one of said two inboard master power switch pipes turn-offed for second time of delay.
6. according to claim 1 or claim 2 diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method is characterized in that:
The wave limiting circuit that said wave limiting circuit is made up of programming device, said programming device is CPLD.
7. diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method as claimed in claim 6 is characterized in that:
The input signal of said wave limiting circuit comprises the wave limiting enable signal and the drive signal of each master power switch pipe of being produced by the multi-level converter controller.
8. diode neutral point clamp type multi-level converter Wave-chasing current-limiting control method as claimed in claim 7 is characterized in that:
The input signal of said wave limiting circuit also comprises the wave limiting function auxiliary signal that is produced by the multi-level converter controller; Which in two inboard master power switch pipes concrete pressure turn-off in said second time of delay, and be relevant with said wave limiting function auxiliary signal.
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| CN200810107870A CN101588124B (en) | 2008-05-23 | 2008-05-23 | Wave-chasing current-limiting control method of diode mid-point clamping multilevel converter |
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| CN200810107870A CN101588124B (en) | 2008-05-23 | 2008-05-23 | Wave-chasing current-limiting control method of diode mid-point clamping multilevel converter |
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| CN101588124B true CN101588124B (en) | 2012-10-10 |
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