CN109586243B - Three-level current limiting circuit of uninterrupted power supply and control method thereof - Google Patents
Three-level current limiting circuit of uninterrupted power supply and control method thereof Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
- H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
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Abstract
The invention discloses a three-level current limiting circuit of an uninterruptible power supply and a control method thereof, belonging to the technical field of power circuits, and comprising a first IGBT module, a second IGBT module, a third IGBT module, a fourth IGBT module, a fifth IGBT module and a sixth IGBT module, wherein the first IGBT module, the second IGBT module, the third IGBT module and the fourth IGBT module are connected in series to form a loop, one side of the loop is connected with a first BUS capacitor and a second BUS capacitor, the other side of the loop is connected with an output inductor and an output capacitor, the fifth IGBT module is connected in parallel to the outside of the first IGBT module and the second IGBT module, and the sixth IGBT module is connected in parallel to the outside of the third IGBT module and the fourth IGBT module.
Description
Technical Field
The invention relates to a three-level current limiting circuit of an uninterruptible power supply and a control method thereof, belonging to the technical field of power supply circuits.
Background
As shown in fig. 1, the on-line ups three-level current limiting refers to a situation where the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3, and the fourth IGBT module Q4 are turned off together after the current I passing through the output inductor L exceeds the preset current value Iset; in practical three-level applications, the first absorption capacitor C1 and the second absorption capacitor C2 are connected in parallel to improve peak voltages of the first IGBT module Q1 and the fourth IGBT module Q4, so that the second IGBT module Q2 and the third IGBT module Q3 have peak voltages of double BUS voltages, Vbus voltage refers to the voltage of the first BUS capacitor C3 or the second BUS capacitor C4, and when the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are applied, the types are selected according to single Vbus voltage due to efficiency and the like, so that the risk of damage to the second IGBT module Q2 or the third IGBT module Q3 of the uninterruptible power supply device is caused.
The double Vbus peak voltage is formed for the following reasons: if the current limiting occurs in the positive half cycle of the sine wave, the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are all turned off, the point C is that the first absorption capacitor C1 and the parasitic capacitor of the first diode D1 act as positive Vbus voltage, the output inductor L freewheels through the diodes of the third IGBT module Q3 and the fourth IGBT module Q4, and the point M on the left side of the output inductor L is negative Vbus voltage, so that the second IGBT module Q2 bears double Vbus voltage; if the current limiting occurs at the negative half cycle of the sine wave, double the Vbus voltage is sustained for the third IGBT module Q3.
Disclosure of Invention
The invention aims to provide a three-level current limiting circuit of an uninterruptible power supply and a control method thereof, which can reduce the damage risk of devices, reduce the requirement on the impact limitation of output loads, improve the reliability of products and solve the problems in the prior art.
The uninterrupted power supply three-level current limiting circuit comprises a first BUS capacitor, a second BUS capacitor, an output inductor and an output capacitor, wherein the first BUS capacitor and the second BUS capacitor are connected in series and then are connected with the output inductor and the output capacitor, the circuit further comprises a first IGBT module, a second IGBT module, a third IGBT module, a fourth IGBT module, a fifth IGBT module and a sixth IGBT module, the first IGBT module, the second IGBT module, the third IGBT module and the fourth IGBT module are connected in series to form a loop, one side of the loop is connected with the first BUS capacitor and the second BUS capacitor, the other side of the loop is connected with the output inductor and the output capacitor, the fifth IGBT module is connected in parallel with the outside of the first IGBT module and the second IGBT module, the sixth IGBT module is connected in parallel with the outside of the third IGBT module and the fourth IGBT module, and the fifth IGBT module is connected with the sixth TGBT module.
The positive pole of the first BUS capacitor is connected with the C level of the first IGBT module, the E pole of the first IGBT module, the C pole of the second IGBT module and the C pole of the fifth IGBT module are connected, the E pole of the fifth IGBT module is connected with the negative pole of the first BUS capacitor, the C pole of the sixth IGBT module and the positive pole of the second BUS capacitor at the N point, the E pole of the fourth IGBT module is connected with the negative pole of the second BUS capacitor, the E pole of the third IGBT module and the C pole of the fourth IGBT module are connected with the E pole of the sixth TGBT module, the E pole of the second IGBT module is connected with the C pole of the third IGBT module and one side of the output inductor at the M point, the other side of the output inductor is connected with one side of the output capacitor, and the other side of the output capacitor is connected with the N point.
The circuit further comprises a first absorption capacitor and a second absorption capacitor, wherein the first absorption capacitor is connected to the outside of the fifth IGBT module in parallel, and the second absorption capacitor is connected to the outside of the sixth IGBT module in parallel.
The invention relates to a control method of an uninterruptible power supply three-level current limiting circuit, which comprises the following steps:
(1) when the absolute value of the real-time current sampling value I of the output inductor (L) is greater than Iset, and the Iset is a preset current value, triggering the current-limiting logic to enter a hardware interrupt program;
(2) when the real-time current sampling value I of the output inductor is a positive value, triggering current limiting occurs in a positive half cycle of a sine wave, the first IGBT module, the second IGBT module, the third IGBT module and the fourth IGBT module are turned off completely, the fifth IGBT module is turned on, the sixth IGBT module is kept turned off, current continues flowing through diodes in the third IGBT module and the fourth IGBT module, and the first absorption capacitor releases energy through the fifth IGBT module;
(3) the fifth IGBT module is turned off after 1us of timing, and the fifth IGBT module is turned off after the first absorption capacitor releases energy, so that the reliability is ensured;
(4) after timing (T-3) us, the first IGBT module and the second IGBT module recover the switch and turn on a sixth IGBT module, current continues flowing through diodes of the first IGBT module and the second IGBT module, and the second absorption capacitor releases energy through the sixth IGBT module, wherein T is the minimum time when the current limiting point drops to zero;
(5) and after timing for 1us, the sixth IGBT module is turned off, and at the moment, the fifth IGBT module and the sixth IGBT module are simultaneously turned off and are restored to normal logic.
The method further comprises the following steps:
(11) (11) when the real-time current sampling value I of the output inductor is a negative value, namely (-I) > Iset, triggering current limiting occurs in the sine wave negative half cycle, -I is positive, and Iset is a positive value, triggering current limiting occurs in the sine wave negative half cycle, so that the first IGBT module, the second IGBT module, the third IGBT module and the fourth IGBT module are all turned off, the sixth IGBT module is turned on, and the fifth IGBT module is kept turned off;
(12) the sixth IGBT module is turned off after 1us of timing, and the sixth IGBT module is turned off after the second absorption capacitor releases energy, so that the reliability is ensured;
(13) after the time (T-3) us, the third IGBT module and the fourth IGBT module recover the switch and turn on the fifth IGBT module;
(14) and after timing for 1us, the fifth IGBT module is turned off, and at the moment, the fifth IGBT module and the sixth IGBT module are simultaneously turned off and are restored to normal logic.
In the step (1), except for triggering the current limiting logic, namely the absolute value of the real-time current sampling value I of the output inductor is smaller than Iset, the fifth IGBT module does not act, the sixth IGBT module does not act, at this time, the body diode of the fifth IGBT module plays a role, and the body diode of the sixth IGBT module plays a role.
Compared with the prior art, the invention has the following beneficial effects:
according to the uninterruptible power supply three-level current limiting circuit and the control method thereof, after the fifth IGBT module and the sixth IGBT module are introduced into the circuit, the discharging process of the first absorption capacitor and the second absorption capacitor can be realized by controlling the on-off of the fifth IGBT module and the sixth IGBT module, the situation that the second IGBT module and the third IGBT module have double Vbus peak voltage is avoided, the damage risk of devices can be effectively reduced, the requirement on the impact limitation of output loads is lowered, the reliability of products is improved, and the problems in the prior art are solved.
Drawings
FIG. 1 is a prior art three-level current limiting circuit diagram of a power supply;
FIG. 2 is a circuit diagram of a three-level current limiting circuit of the power supply of the present invention;
FIG. 3 is a schematic diagram of a sine wave positive half cycle current limiting and turn-off current loop in the power supply three-level current limiting control method of the present invention;
FIG. 4 is a schematic diagram of a sine wave positive half cycle current limiting recovery turn-on current loop in the power supply three-level current limiting control method of the present invention;
FIG. 5 is a model of time T calculation in the power supply three-level current-limiting control method of the present invention;
FIG. 6 is a flow chart of a three-level current limiting control method of the power supply of the present invention;
in the figure: q1, a first IGBT module; q2, a second IGBT module; q3, a third IGBT module; q4, a fourth IGBT module; q5, a fifth IGBT module; c1, a first absorption capacitor; c2, a second absorption capacitance; c3, first BUS capacitance; c4, first BUS capacitance; c5, output capacitance; d1, a first diode; d2, a second diode; l, output inductance.
Detailed Description
The invention is further illustrated by the following figures and examples:
example 1:
as shown in fig. 2, the three-level current limiting circuit of the ups of the present invention includes a first BUS capacitor C3, a second BUS capacitor C4, an output inductor L, and an output capacitor C5, wherein the first BUS capacitor C3 and the second BUS capacitor C4 are connected in series and then connected to the output inductor L and the output capacitor C5, and is characterized in that: the circuit further comprises a first IGBT module Q1, a second IGBT module Q2, a third IGBT module Q3, a fourth IGBT module Q4, a fifth IGBT module Q5 and a sixth IGBT module Q6, wherein the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are connected in series to form a loop, one side of the loop is connected with a first BUS capacitor C3 and a second BUS capacitor C4, the other side of the loop is connected with an output inductor L and an output capacitor C5, the outer portions of the first IGBT module Q1 and the second IGBT module Q2 are connected with the fifth IGBT module Q5 in parallel, the outer portions of the third IGBT module Q3 and the fourth IGBT module Q4 are connected with the sixth IGBT module Q6 in parallel, and the fifth IGBT module Q5 is connected with the sixth IGBT module Q6.
To further illustrate the above embodiment, the positive pole of the first BUS capacitor C3 is connected to the C-stage of the first IGBT module Q1, the E-pole of the first IGBT module Q1, the C-pole of the second IGBT module Q2 and the C-pole of the fifth IGBT module Q5 are connected, the E-pole of the fifth IGBT module Q5 is connected to the negative pole of the first BUS capacitor C3, the C-pole of the sixth IGBT module Q6 and the positive pole of the second BUS capacitor C4 at N-point, the E-pole of the fourth IGBT module Q4 is connected to the negative pole of the second BUS capacitor C4, the E-pole of the third IGBT module Q3, the C-pole of the fourth IGBT module Q4 are connected to the E-pole of the sixth IGBT module Q6, the E-pole of the second IGBT module Q2 is connected to the C-pole of the third IGBT module Q3 and one side of the output inductor L at M-point, the other side of the output inductor Q5 is connected to one side of the output capacitor C5.
To further illustrate the above embodiments, the circuit further includes a first sinking capacitor C1 and a second sinking capacitor C2, wherein the first sinking capacitor C1 is connected in parallel to the outside of the fifth IGBT module Q5, and the second sinking capacitor C2 is connected in parallel to the outside of the sixth IGBT module Q6.
In the prior art, the first diode D1 and the second diode D2 cannot discharge the first absorption capacitor C1 and the second absorption capacitor C2 under the current limiting condition, after the fifth IGBT module Q5 and the sixth IGBT module Q6 are introduced into the circuit, the discharge process of the first absorption capacitor C1 and the second absorption capacitor C2 can be realized by controlling the switching of the fifth IGBT module Q5 and the sixth IGBT module Q6, the voltage on the first BUS capacitor C3 and the second BUS capacitor C4 is defined as Vbus, and the situation that the second IGBT module Q2 and the third IGBT module Q3 have double Vbus stress is avoided by emptying the first absorption capacitor C1 and the second absorption capacitor C2.
Example 2:
the control method of the three-level current limiting circuit of the uninterrupted power supply, as shown in fig. 2-6, comprises the following steps:
(1) when the absolute value of the real-time current sampling value I of the output inductor L is greater than Iset, and the Iset is a preset current value, triggering the current-limiting logic to enter a hardware interrupt program;
(2) when the real-time current sampling value I of the output inductor (L) is a positive value, triggering current limiting occurs in the positive half cycle of the sine wave,
the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3, and the fourth IGBT module Q4 are all turned off, the fifth IGBT module Q5 is turned on, the sixth IGBT module Q6 remains turned off, current freewheels through diodes in the third IGBT module Q3 and the fourth IGBT module Q4, and the first absorption capacitor C1 releases energy through the fifth IGBT module Q5;
(3) the fifth IGBT module Q5 is turned off after 1us of timing, and the fifth IGBT module Q5 is turned off after the first absorption capacitor releases energy, so that the reliability is ensured;
(4) after the time (T-3) us, the first IGBT module Q1 and the second IGBT module Q2 are switched back on and the sixth IGBT module Q6 is switched on, the current continues to flow through the diodes of the first IGBT module Q1 and the second IGBT module Q2, the second absorption capacitor C2 releases energy through the sixth IGBT module Q6, wherein T is the minimum time when the current limiting point drops to zero;
(5) after the timing is 1us, the sixth IGBT module Q6 is turned off, and at this time, the fifth IGBT module Q5 and the sixth IGBT module Q6 are turned off at the same time, and normal logic is restored.
Iset is a preset current value of the output inductor, namely 300% of rated output current of the uninterruptible power supply (ensuring output loading capacity), and is a positive value.
The real-time current sampling value I of the output inductor L can be positive or negative, if the trigger current limiting occurs in the positive half cycle of the sine wave, I is positive, I is greater than Iset, and if the trigger current limiting occurs in the negative half cycle of the sine wave, I is negative, I is greater than Iset. With reference to fig. 1: in the prior art, the voltage on the first BUS capacitor C3 and the second BUS capacitor C4 is defined as Vbus, and the reason for the double Vbus voltage stress is as follows: if the current limiting occurs in the positive half cycle of the sine wave, the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are all turned off, the point C is that Vbus voltage is acted by the first absorption capacitor C1 and the parasitic capacitor of the first diode D1, the output inductor L freewheels through the diodes of the third IGBT module Q3 and the fourth IGBT module Q4, and the point M on the left side of the output inductor L is-Vbus voltage, so that the second IGBT module Q2 bears double Vbus voltage; if the current limit occurs at the sine wave negative half cycle, the third IGBT module Q3 is subjected to double Vbus voltage; the implementation of the present embodiment solves the problem that the second IGBT module Q2 is subjected to double Vbus voltage, and avoids the second IGBT module Q2 from being damaged.
The reason why the release time of the first absorption capacitor C1 or the second absorption capacitor C2 is defined as 1 us:
since the first absorption capacitor C1 or the second absorption capacitor C2 is a spike absorption capacitor, the capacitance thereof is extremely small, and the capacitances are all below 100nF, and if the impedances of the first absorption capacitor C1, the fifth IGBT module Q5 path, the second absorption capacitor C2, and the sixth IGBT module Q6 path are 1 ohm, the time constant τ R × C becomes 100ns, and the time for emptying the first absorption capacitor C1 or the second absorption capacitor C2 becomes 5 times the time constant, and the spike absorption capacitor can be emptied completely within 500ns, and the margin of 100% is increased, so that the time for the first absorption capacitor C1 to be released through the fifth IGBT module Q5 or the time for the second absorption capacitor C2 to be released through the sixth IGBT module Q6 is set to 1 us.
T is calculated as follows: calculating the minimum time from the current limiting point to zero, simplifying the model of fig. 5, charging the output capacitor C5 by the output inductor L, and approximately considering that the output capacitor C5 is short-circuited, and when the load is fully loaded, the resistance value is small and the output capacitor C5 is short-circuited, if the inductance value is measured as Lp, defining the voltage on the first BUS capacitor C3 and the second BUS capacitor C4 as Vbus, the capacitor voltage in fig. 6 is-Vbus, the current of the output inductor L drops to zero Tp ═ Lp Iset/Vbus, and the margin is left, T is 60% of Tp, and T ═ 0.6 × Lp Iset/Vbus.
Example 3:
on the basis of embodiment 2, as shown in fig. 6, the method for controlling a three-level current limiting circuit of an uninterruptible power supply according to the present invention further includes the following steps:
(12) when the real-time current sampling value I of the output inductor L is a negative value, namely-I > Iset, triggering current limiting occurs in a sine wave negative half cycle, wherein-I is positive, and Iset is a positive value, the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are turned off completely, the sixth IGBT module Q6 is turned on, and the fifth IGBT module Q5 is kept turned off;
(13) after timing for 1us, the sixth IGBT module Q6 is turned off, and after the energy released by the second absorption capacitor C2 is finished, the sixth IGBT module Q6 is turned off, so that the reliability is ensured;
(14) after the time T-3us, the third IGBT module Q3 and the fourth IGBT module Q4 are switched on and off, and the fifth IGBT module Q5 is switched on;
(15) after the timing is 1us, the fifth IGBT module Q5 is turned off, and at this time, the fifth IGBT module Q5 and the sixth IGBT module Q6 are turned off at the same time, and normal logic is restored.
The problem that the third IGBT module Q3 bears double Vbus voltage is solved through the embodiment, and the damage of the third IGBT module Q3 is avoided.
To further illustrate the above embodiment, in step (1), except for triggering the current limiting logic, that is, the absolute value of the real-time current sampling value I of the output inductor L is smaller than Iset, the fifth IGBT module Q5 does not operate, the sixth IGBT module Q6 does not operate, the body diode of the fifth IGBT module Q5 functions, and the body diode of the sixth IGBT module Q6 functions.
By adopting the uninterruptible power supply three-level current limiting circuit and the control method thereof, which are described in the embodiment of the invention in combination with the drawings, the device damage risk can be reduced, the requirement on the impact limitation of the output load is reduced, the reliability of the product is improved, and the problems in the prior art are solved. The present invention is not limited to the embodiments described, but rather, variations, modifications, substitutions and alterations are possible without departing from the spirit and scope of the present invention.
Claims (3)
1. A control method of three-level current-limiting circuit of uninterrupted power supply is characterized in that: the uninterruptible power supply three-level current limiting circuit comprises a first BUS capacitor (C3), a second BUS capacitor (C4), an output inductor (L) and an output capacitor (C5), wherein the first BUS capacitor (C3) and the second BUS capacitor (C4) are connected in series and then are connected with the output inductor (L) and the output capacitor (C5), the circuit further comprises a first IGBT module (Q1), a second IGBT module (Q2), a third IGBT module (Q3), a fourth IGBT module (Q4), a fifth IGBT module (Q5) and a sixth IGBT module (Q6), the first IGBT module (Q1), the second IGBT module (Q2), the third IGBT module (Q3) and the fourth IGBT module (Q4) are connected in series to form a loop, one side of the loop is connected with the first BUS capacitor (C3) and the second BUS capacitor (C4), the output inductor (L) and the second IGBT module (Q3748) are connected with the output capacitor (C5), and the first IGBT module (Q2) are connected in parallel with the second IGBT module (Q6), the outer parts of the third IGBT module (Q3) and the fourth IGBT module (Q4) are connected with a sixth IGBT module (Q6) in parallel, and the fifth IGBT module (Q5) is connected with the sixth TGBT module (Q6);
the positive pole of the first BUS capacitor (C3) is connected with the C pole of the first IGBT module (Q1), the E pole of the first IGBT module (Q1), the C pole of the second IGBT module (Q2) and the C pole of the fifth IGBT module (Q5) are connected, the E pole of the fifth IGBT module (Q5) is connected with the negative pole of the first BUS capacitor (C3) and the C pole of the sixth IGBT module (Q6), the positive electrode of the second BUS capacitor (C4) is connected to the point N, the E electrode of the fourth IGBT module (Q4) is connected with the negative electrode of the second BUS capacitor (C4), the E electrode of the third IGBT module (Q3) and the C electrode of the fourth IGBT module (Q4) are connected with the E electrode of the sixth TGBT module (Q6), the E electrode of the second IGBT module (Q2) is connected with the C electrode of the third IGBT module (Q3) and one side of an output inductor (L) to the point M, the other side of the output inductor (L) is connected with one side of the output capacitor (C5), and the other side of the output capacitor (C5) is connected to the point N;
the circuit further comprises a first sinking capacitor (C1) and a second sinking capacitor (C2), wherein the first sinking capacitor (C1) is connected in parallel outside the fifth IGBT module (Q5), and the second sinking capacitor (C2) is connected in parallel outside the sixth IGBT module (Q6);
the control method comprises the following steps:
(1) when the absolute value of the real-time current sampling value I of the output inductor (L) is greater than Iset, and the Iset is a preset current value, triggering the current-limiting logic to enter a hardware interrupt program;
(2) when the real-time current sampling value I of the output inductor (L) is a positive value, triggering current limiting occurs in a sine wave positive half cycle, the first IGBT module (Q1), the second IGBT module (Q2), the third IGBT module (Q3) and the fourth IGBT module (Q4) are turned off completely, the fifth IGBT module (Q5) is turned on, the sixth IGBT module (Q6) is kept turned off, current continues to flow through diodes in the third IGBT module (Q3) and the fourth IGBT module (Q4), and the first absorption capacitor (C1) releases energy through the fifth IGBT module (Q5);
(3) the fifth IGBT module (Q5) is turned off after 1us of timing, and the fifth IGBT module (Q5) is turned off after the energy released by the first absorption capacitor (C1) is finished, so that the reliability is ensured;
(4) after the time (T-3) us, the first IGBT module (Q1) and the second IGBT module (Q2) are switched back on and the sixth IGBT module (Q6) is switched on, current continues to flow through diodes of the first IGBT module (Q1) and the second IGBT module (Q2), and the second absorption capacitor (C2) releases energy through the sixth IGBT module (Q6), wherein T is the minimum time when the current limiting point drops to zero;
(5) after the timing is 1us, the sixth IGBT module (Q6) is turned off, and at the moment, the fifth IGBT module (Q5) and the sixth IGBT module (Q6) are simultaneously turned off and return to normal logic.
2. The method of claim 1, wherein the method further comprises: the control method further comprises the following steps:
(11) when a real-time current sampling value I of an output inductor (L) is a negative value, namely (-I) > Iset, triggering current limiting occurs in a sine wave negative half cycle, wherein the-I is positive, and the Iset is a positive value, a first IGBT module (Q1), a second IGBT module (Q2), a third IGBT module (Q3) and a fourth IGBT module (Q4) are turned off completely, a sixth IGBT module (Q6) is turned on, and a fifth IGBT module (Q5) is kept turned off;
(12) after timing for 1us, the sixth IGBT module (Q6) is turned off, and after the second absorption capacitor (C2) releases energy, the sixth IGBT module (Q6) is turned off, so that the reliability is ensured;
(13) after the time (T-3) us, the third IGBT module (Q3) and the fourth IGBT module (Q4) resume switching and turn on the fifth IGBT module (Q5);
(14) after the timing is 1us, the fifth IGBT module (Q5) is turned off, and at the moment, the fifth IGBT module (Q5) and the sixth IGBT module (Q6) are simultaneously turned off and return to normal logic.
3. The method of claim 1, wherein the method further comprises: in the step (1), except for triggering the current limiting logic, namely the absolute value of the real-time current sampling value I of the output inductor (L) is smaller than Iset, the fifth IGBT module (Q5) does not act, the sixth IGBT module (Q6) does not act, at this time, the body diode of the fifth IGBT module (Q5) plays a role, and the body diode of the sixth IGBT module (Q6) plays a role.
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| JP2009232621A (en) * | 2008-03-24 | 2009-10-08 | Toshiba Mitsubishi-Electric Industrial System Corp | Power converter |
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