CN109586243B - Three-level current limiting circuit of uninterrupted power supply and control method thereof - Google Patents

Abstract

The invention discloses an uninterruptible power supply three-level current limiting circuit and a control method thereof, belonging to the technical field of power supply circuits, comprising a first IGBT module, a second IGBT module, a third IGBT module, a fourth IGBT module and a fifth IGBT module and the sixth IGBT module, wherein the first IGBT module, the second IGBT module, the third IGBT module and the fourth IGBT module are connected in series to form a loop, and one side of the loop is connected to the first BUS capacitor and the second BUS capacitor, and the other side Connecting the output inductor and the output capacitor, the first IGBT module and the second IGBT module are connected in parallel with the fifth IGBT module, and the third IGBT module and the fourth IGBT module are connected in parallel with the sixth IGBT module, which can reduce the risk of device damage and reduce the risk of damage to the output load. The impact limit requirement is reduced, the reliability of the product is improved, and the problems occurring in the prior art are solved.

Description

Three-level current limiting circuit of uninterruptible power supply and control method thereof

technical field

The invention relates to a three-level current limiting circuit of an uninterruptible power supply and a control method thereof, belonging to the technical field of power supply circuits.

Background technique

As shown in Figure 1, the three-level current limiting of the online uninterruptible power supply refers to the first IGBT module Q1, the second IGBT module Q2, and the third IGBT module Q3 after the current I through the output inductor L exceeds the preset current value Iset and the fourth IGBT module Q4 are turned off together; in the three-level practical application, in order to improve the peak voltage of the first IGBT module Q1 and the fourth IGBT module Q4, the first absorption capacitor C1 and the second absorption capacitor C2 are connected in parallel, so that It will cause the second IGBT module Q2 and the third IGBT module Q3 to have a peak voltage that doubles the BUS voltage. The Vbus voltage refers to the voltage of the first BUS capacitor C3 or the second BUS capacitor C4. The first IGBT module Q1 and the second IGBT module Q2, the third IGBT module Q3, and the fourth IGBT module Q4 are selected according to the single Vbus voltage due to efficiency and other reasons, which will cause the risk of damage to the second IGBT module Q2 or the third IGBT module Q3 of the uninterruptible power supply device.

The reasons for the double Vbus peak voltage are as follows: if the current limit occurs in the positive half cycle of the sine wave, the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3, and the fourth IGBT module Q4 are all turned off. The function of a absorbing capacitor C1 and the parasitic capacitance of the first diode D1 is the positive Vbus voltage, the output inductor L is freewheeling through the diodes of the third IGBT module Q3 and the fourth IGBT module Q4, and the M point on the left side of the output inductor L is the negative Vbus voltage , so the second IGBT module Q2 bears double the Vbus voltage; if the current limiting occurs in the negative half cycle of the sine wave, the third IGBT module Q3 bears double the Vbus voltage.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a three-level current limiting circuit of an uninterruptible power supply and a control method thereof, which can reduce the risk of device damage, reduce the requirement for output load impact limitation, improve the reliability of products, and solve the problems in the prior art. question.

The three-level current limiting circuit of the uninterruptible power supply of the present invention includes a first BUS capacitor, a second BUS capacitor, an output inductor and an output capacitor, wherein the first BUS capacitor and the second BUS capacitor are connected in series to connect the output inductor and the output capacitor. capacitor, the circuit further includes a first IGBT module, a second IGBT module, a third IGBT module, a fourth IGBT module, a fifth IGBT module and a sixth IGBT module, wherein the first IGBT module, the second IGBT module and the third IGBT module It is connected in series with the fourth IGBT module to form a loop, and one side of the loop is connected to the first BUS capacitor and the second BUS capacitor, and the other side is connected to the output inductor and the output capacitor. The IGBT module, the third IGBT module and the fourth IGBT module are connected in parallel with the outside of the sixth IGBT module, and the fifth IGBT module is connected with the sixth IGBT module.

The positive pole of the first BUS capacitor is connected to the C level of the first IGBT module, the E pole of the first IGBT module, the C pole of the second IGBT module are connected to the C pole of the fifth IGBT module, and the E pole of the fifth IGBT module is connected. The pole is connected to the negative pole of the first BUS capacitor, the C pole of the sixth IGBT module, and the positive pole of the second BUS capacitor at point N, the E pole of the fourth IGBT module is connected to the negative pole of the second BUS capacitor, and the E pole of the third IGBT module is connected to the negative pole of the second BUS capacitor. pole, the C pole of the fourth IGBT module is connected to the E pole of the sixth IGBT module, the E pole of the second IGBT module is connected to the C pole of the third IGBT module and one side of the output inductor is connected to point M, and the other side of the output inductor is connected to One side of the output capacitor is connected, and the other side of the output capacitor is connected to point N.

The circuit further includes a first absorption capacitor and a second absorption capacitor, wherein the first absorption capacitor is connected in parallel with the outside of the fifth IGBT module, and the second absorption capacitor is connected in parallel with the outside of the sixth IGBT module.

The control method of the three-level current limiting circuit of the uninterruptible power supply according to the present invention comprises the following steps:

(1) When the absolute value of the real-time current sampling value I of the output inductance (L) >Iset, Iset is the preset current value, and the current limiting logic is triggered to enter the hardware interrupt program;

(2) When the real-time current sampling value I of the output inductance is a positive value, the trigger current limit occurs in the positive half cycle of the sine wave, and the first IGBT module, the second IGBT module, the third IGBT module and the fourth IGBT module are all turned off , the fifth IGBT module is turned on, the sixth IGBT module is kept off, the current is freewheeling through the diodes in the third IGBT module and the fourth IGBT module, and the first absorption capacitor releases energy through the fifth IGBT module;

(3) Turn off the fifth IGBT module after timing 1us, and turn off the fifth IGBT module after the first absorption capacitor releases energy to ensure reliability;

(4) After timing (T-3)us, the first IGBT module and the second IGBT module resume the switch and turn on the sixth IGBT module, the current continues to flow through the diodes of the first IGBT module and the second IGBT module, and the second absorption capacitor passes through the first IGBT module and the second IGBT module. Six IGBT modules release energy, where T is the minimum time for the current limiting point to drop to zero;

(5) Turn off the sixth IGBT module after timing for 1us. At this time, the fifth IGBT module and the sixth IGBT module are turned off at the same time, returning to normal logic.

The method also includes the following steps:

(11) (11) When the real-time current sampling value I of the output inductor is a negative value, that is (-I)>Iset, the trigger current limit occurs in the negative half cycle of the sine wave, -I is positive, and Iset is a positive value, then the trigger is triggered When the current is limited in the negative half cycle of the sine wave, the first IGBT module, the second IGBT module, the third IGBT module and the fourth IGBT module are all turned off, the sixth IGBT module is turned on, and the fifth IGBT module is kept off;

(12) Turn off the sixth IGBT module after timing 1us, and turn off the sixth IGBT module after the second absorption capacitor releases energy to ensure reliability;

(13) After timing (T-3) us, the third IGBT module and the fourth IGBT module resume switching and turn on the fifth IGBT module;

(14) Turn off the fifth IGBT module after timing for 1us. At this time, the fifth IGBT module and the sixth IGBT module are turned off at the same time, returning to normal logic.

In the step (1), in addition to triggering the current limiting logic, that is, the absolute value of the real-time current sampling value I of the output inductance is less than Iset, then the fifth IGBT module does not operate, the sixth IGBT module does not operate, and then the fifth IGBT module does not operate. The body diode of the sixth IGBT module functions, and the body diode of the sixth IGBT module functions.

Compared with the prior art, the present invention has the following beneficial effects:

In the three-level current limiting circuit of the uninterruptible power supply and the control method thereof of the present invention, after the fifth IGBT module and the sixth IGBT module are introduced into the circuit, the switching of the fifth IGBT module and the sixth IGBT module can be controlled to realize the The discharge process of the first absorption capacitor and the second absorption capacitor avoids the situation that the peak voltage of the second IGBT module and the third IGBT module has double Vbus, which can effectively reduce the risk of device damage and reduce the impact limit on the output load. The reliability of the product is improved, and the problems in the prior art are solved.

Description of drawings

Fig. 1 is a three-level current limiting circuit diagram of a power supply in the prior art;

2 is a three-level current limiting circuit diagram of a power supply in the present invention;

3 is a schematic diagram of a sine wave positive half-cycle current-limiting shutdown current loop in the three-level current-limiting control method of the power supply of the present invention;

4 is a schematic diagram of a sine wave positive half-cycle current-limiting recovery turn-on current loop in the three-level current-limiting control method of the power supply of the present invention;

Fig. 5 is the calculation model of time T in the three-level current limiting control method of the power supply of the present invention;

6 is a flowchart of a three-level current limiting control method for a power supply in the present invention;

In the figure: Q1, the first IGBT module; Q2, the second IGBT module; Q3, the third IGBT module; Q4, the fourth IGBT module; Q5, the fifth IGBT module; C1, the first absorption capacitor; C2, the second absorption capacitor; C3, the first BUS capacitor; C4, the first BUS capacitor; C5, the output capacitor; D1, the first diode; D2, the second diode; L, the output inductor.

Detailed ways

Below in conjunction with accompanying drawing and embodiment, the present invention will be further described:

Example 1:

As shown in FIG. 2, the three-level current limiting circuit of the uninterruptible power supply of the present invention includes a first BUS capacitor C3, a second BUS capacitor C4, an output inductor L and an output capacitor C5, wherein the first BUS capacitor C3 and the third The two BUS capacitors C4 are connected in series to the output inductor L and the output capacitor C5. It is characterized in that: the circuit further includes a first IGBT module Q1, a second IGBT module Q2, a third IGBT module Q3, a fourth IGBT module Q4, The fifth IGBT module Q5 and the sixth IGBT module Q6, wherein the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are connected in series to form a loop, and one side of the loop is connected to the first BUS The capacitor C3 and the second BUS capacitor C4 are connected to the output inductor L and the output capacitor C5 on the other side. The external connection of the first IGBT module Q1 and the second IGBT module Q2 is connected in parallel with the fifth IGBT module Q5, the third IGBT module Q3 and the fourth IGBT A sixth IGBT module Q6 is connected in parallel outside the module Q4, and the fifth IGBT module Q5 is connected to the sixth IGBT module Q6.

In order to further illustrate the above embodiment, the positive pole of the first BUS capacitor C3 is connected to the C stage of the first IGBT module Q1, the E pole of the first IGBT module Q1, the C pole of the second IGBT module Q2 and the C pole of the fifth IGBT module Q5 The E pole of the fifth IGBT module Q5 is connected to the negative pole of the first BUS capacitor C3, the C pole of the sixth IGBT module Q6, and the positive pole of the second BUS capacitor C4 are connected to point N, and the E pole of the fourth IGBT module Q4 is connected to the N point. The negative pole of the second BUS capacitor C4 is connected, the E pole of the third IGBT module Q3 and the C pole of the fourth IGBT module Q4 are connected to the E pole of the sixth IGBT module Q6, and the E pole of the second IGBT module Q2 is connected to the third IGBT module The C pole of Q3 and one side of the output inductor L are connected to point M, the other side of the output inductor L is connected to one side of the output capacitor C5, and the other side of the output capacitor C5 is connected to point N.

In order to further illustrate the above embodiment, the circuit further includes a first absorption capacitor C1 and a second absorption capacitor C2, wherein the first absorption capacitor C1 is connected in parallel with the outside of the fifth IGBT module Q5, and the second absorption capacitor C2 is connected in parallel with the sixth IGBT module Q6 the exterior.

In the prior art, the first diode D1 and the second diode D2 cannot discharge the first absorbing capacitor C1 and the second absorbing capacitor C2 when the current is limited, and the fifth IGBT module Q5 and the sixth IGBT are introduced into the circuit. After the module Q6, the discharge process of the first absorption capacitor C1 and the second absorption capacitor C2 can be realized by controlling the switches of the fifth IGBT module Q5 and the sixth IGBT module Q6, and the first BUS capacitor C3 and the second BUS capacitor C4 are defined. The upper voltage is Vbus. By venting the first absorbing capacitor C1 and the second absorbing capacitor C2, the situation of double Vbus stress on the second IGBT module Q2 and the third IGBT module Q3 is avoided.

Example 2:

The control method of the three-level current limiting circuit of the uninterruptible power supply according to the present invention, as shown in Figures 2-6, includes the following steps:

(1) When the absolute value of the real-time current sampling value I of the output inductor L>Iset, Iset is the preset current value, triggering the current limiting logic to enter the hardware interrupt program;

(2) When the real-time current sampling value I of the output inductor (L) is a positive value, the trigger current limit occurs in the positive half cycle of the sine wave,

Then the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are all turned off, the fifth IGBT module Q5 is turned on, the sixth IGBT module Q6 is kept off, and the current flows through the third IGBT module. The diodes in Q3 and the fourth IGBT module Q4 freewheel, and the first absorption capacitor C1 releases energy through the fifth IGBT module Q5;

(3) Turn off the fifth IGBT module Q5 after timing 1us, and turn off the fifth IGBT module Q5 after the first absorption capacitor releases energy to ensure reliability;

(4) After timing (T-3) us, the first IGBT module Q1 and the second IGBT module Q2 resume switching and turn on the sixth IGBT module Q6. The current flows through the diodes of the first IGBT module Q1 and the second IGBT module Q2. The second absorption capacitor C2 releases energy through the sixth IGBT module Q6, where T is the minimum time for the current limiting point to drop to zero;

(5) Turn off the sixth IGBT module Q6 after timing for 1us. At this time, the fifth IGBT module Q5 and the sixth IGBT module Q6 are turned off at the same time, returning to normal logic.

Iset is the preset current value of the output inductor, which is 300% of the rated output current of the uninterruptible power supply (guarantee the output load capacity), and Iset is a positive value.

The real-time current sampling value I of the output inductor L may be positive or negative. If the trigger current limit occurs in the positive half cycle of the sine wave, then I is a positive value, then I>Iset, if the trigger current limit occurs in the negative half cycle of the sine wave, then I is Negative value, -I>Iset. 1 : in the prior art, the voltage on the first BUS capacitor C3 and the second BUS capacitor C4 is defined as Vbus, and the double Vbus voltage stress is caused by the following reasons: if the current limit occurs in the positive half cycle of the sine wave, the first IGBT module Q1, the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are all turned off, the point C is the Vbus voltage due to the effect of the first absorption capacitor C1 and the parasitic capacitance of the first diode D1, and the output inductance L is The diodes of the third IGBT module Q3 and the fourth IGBT module Q4 are freewheeling, and the M point on the left side of the output inductor L is the -Vbus voltage, so the second IGBT module Q2 bears double the Vbus voltage; if the current limit occurs in the negative half cycle of the sine wave, then The third IGBT module Q3 bears double the Vbus voltage; through the implementation of this embodiment, the problem that the second IGBT module Q2 bears the double Vbus voltage is solved, and the damage of the second IGBT module Q2 is avoided.

The reason why the release time of the first absorption capacitor C1 or the second absorption capacitor C2 is defined as 1us:

Since the first absorbing capacitor C1 or the second absorbing capacitor C2 is a spike absorbing capacitor, its capacitance value is extremely small, and the capacitance value is all below 100nF. The impedance of the sixth IGBT module Q6 path is 1 ohm, then the time constant τ=R*C=100ns, the time to empty the first absorption capacitor C1 or the second absorption capacitor C2 is 5 times the time constant, and it can be completely empty within 500ns The spike absorption capacitor increases the margin by 100%, so the release time of the first absorption capacitor C1 through the fifth IGBT module Q5 or the release time of the second absorption capacitor C2 through the sixth IGBT module Q6 is set to 1us.

The calculation method of T is as follows: Calculate the minimum time from the current limiting point to zero, and simplify the model in Figure 5. The output inductor L charges the output capacitor C5. It can be approximated that the output capacitor C5 is short-circuited, and the resistance value is very small when the load is fully loaded. Approximate short circuit, if the inductance value is measured as Lp, the voltage on the first BUS capacitor C3 and the second BUS capacitor C4 is defined as Vbus, then the capacitor voltage in Figure 6 is -Vbus, then the output inductor L current drops to zero Tp=Lp* Iset/Vbus, reserve the margin, T is 60% of Tp, T=0.6*Lp*Iset/Vbus.

Example 3:

On the basis of Embodiment 2, as shown in FIG. 6 , the control method of the three-level current limiting circuit of the uninterruptible power supply according to the present invention further includes the following steps:

(12) When the real-time current sampling value I of the output inductor L is a negative value, that is, -I>Iset, the trigger current limit occurs in the negative half cycle of the sine wave, -I is positive, and Iset is a positive value, then the first IGBT module Q1 , the second IGBT module Q2, the third IGBT module Q3 and the fourth IGBT module Q4 are all turned off, the sixth IGBT module Q6 is turned on, and the fifth IGBT module Q5 is kept off;

(13) Turn off the sixth IGBT module Q6 after timing 1us, and turn off the sixth IGBT module Q6 after the second absorption capacitor C2 releases energy to ensure reliability;

(14) After timing T-3us, the third IGBT module Q3 and the fourth IGBT module Q4 resume switching and turn on the fifth IGBT module Q5;

(15) Turn off the fifth IGBT module Q5 after timing for 1us. At this time, the fifth IGBT module Q5 and the sixth IGBT module Q6 are turned off at the same time, returning to normal logic.

This embodiment solves the problem that the third IGBT module Q3 bears double the Vbus voltage, and avoids damage to the third IGBT module Q3.

In order to further illustrate the above embodiment, in step (1), in addition to triggering the current limiting logic, that is, the absolute value of the real-time current sampling value I of the output inductor L is less than Iset, then the fifth IGBT module Q5 does not operate, and the sixth IGBT module Q6 does not operate , at this time, the body diode of the fifth IGBT module Q5 functions, and the body diode of the sixth IGBT module Q6 functions.

By adopting the three-level current limiting circuit of the uninterruptible power supply and the control method thereof according to the embodiments of the present invention described above in conjunction with the accompanying drawings, the risk of device damage can be reduced, the requirement for output load impact limitation is reduced, the reliability of the product is improved, and the current problem is solved. There are technical problems. However, the present invention is not limited to the described embodiments, and these changes, modifications, substitutions and deformations to the embodiments without departing from the principle and spirit of the present invention still fall within the protection scope of the present invention.

Claims (3)

1. A control method of three-level current-limiting circuit of uninterrupted power supply is characterized in that: the uninterruptible power supply three-level current limiting circuit comprises a first BUS capacitor (C3), a second BUS capacitor (C4), an output inductor (L) and an output capacitor (C5), wherein the first BUS capacitor (C3) and the second BUS capacitor (C4) are connected in series and then are connected with the output inductor (L) and the output capacitor (C5), the circuit further comprises a first IGBT module (Q1), a second IGBT module (Q2), a third IGBT module (Q3), a fourth IGBT module (Q4), a fifth IGBT module (Q5) and a sixth IGBT module (Q6), the first IGBT module (Q1), the second IGBT module (Q2), the third IGBT module (Q3) and the fourth IGBT module (Q4) are connected in series to form a loop, one side of the loop is connected with the first BUS capacitor (C3) and the second BUS capacitor (C4), the output inductor (L) and the second IGBT module (Q3748) are connected with the output capacitor (C5), and the first IGBT module (Q2) are connected in parallel with the second IGBT module (Q6), the outer parts of the third IGBT module (Q3) and the fourth IGBT module (Q4) are connected with a sixth IGBT module (Q6) in parallel, and the fifth IGBT module (Q5) is connected with the sixth TGBT module (Q6);

the positive pole of the first BUS capacitor (C3) is connected with the C pole of the first IGBT module (Q1), the E pole of the first IGBT module (Q1), the C pole of the second IGBT module (Q2) and the C pole of the fifth IGBT module (Q5) are connected, the E pole of the fifth IGBT module (Q5) is connected with the negative pole of the first BUS capacitor (C3) and the C pole of the sixth IGBT module (Q6), the positive electrode of the second BUS capacitor (C4) is connected to the point N, the E electrode of the fourth IGBT module (Q4) is connected with the negative electrode of the second BUS capacitor (C4), the E electrode of the third IGBT module (Q3) and the C electrode of the fourth IGBT module (Q4) are connected with the E electrode of the sixth TGBT module (Q6), the E electrode of the second IGBT module (Q2) is connected with the C electrode of the third IGBT module (Q3) and one side of an output inductor (L) to the point M, the other side of the output inductor (L) is connected with one side of the output capacitor (C5), and the other side of the output capacitor (C5) is connected to the point N;

the circuit further comprises a first sinking capacitor (C1) and a second sinking capacitor (C2), wherein the first sinking capacitor (C1) is connected in parallel outside the fifth IGBT module (Q5), and the second sinking capacitor (C2) is connected in parallel outside the sixth IGBT module (Q6);

the control method comprises the following steps:

(1) when the absolute value of the real-time current sampling value I of the output inductor (L) is greater than Iset, and the Iset is a preset current value, triggering the current-limiting logic to enter a hardware interrupt program;

(2) when the real-time current sampling value I of the output inductor (L) is a positive value, triggering current limiting occurs in a sine wave positive half cycle, the first IGBT module (Q1), the second IGBT module (Q2), the third IGBT module (Q3) and the fourth IGBT module (Q4) are turned off completely, the fifth IGBT module (Q5) is turned on, the sixth IGBT module (Q6) is kept turned off, current continues to flow through diodes in the third IGBT module (Q3) and the fourth IGBT module (Q4), and the first absorption capacitor (C1) releases energy through the fifth IGBT module (Q5);

(3) the fifth IGBT module (Q5) is turned off after 1us of timing, and the fifth IGBT module (Q5) is turned off after the energy released by the first absorption capacitor (C1) is finished, so that the reliability is ensured;

(4) after the time (T-3) us, the first IGBT module (Q1) and the second IGBT module (Q2) are switched back on and the sixth IGBT module (Q6) is switched on, current continues to flow through diodes of the first IGBT module (Q1) and the second IGBT module (Q2), and the second absorption capacitor (C2) releases energy through the sixth IGBT module (Q6), wherein T is the minimum time when the current limiting point drops to zero;

(5) after the timing is 1us, the sixth IGBT module (Q6) is turned off, and at the moment, the fifth IGBT module (Q5) and the sixth IGBT module (Q6) are simultaneously turned off and return to normal logic.

2. The method of claim 1, wherein the method further comprises: the control method further comprises the following steps:

(11) when a real-time current sampling value I of an output inductor (L) is a negative value, namely (-I) > Iset, triggering current limiting occurs in a sine wave negative half cycle, wherein the-I is positive, and the Iset is a positive value, a first IGBT module (Q1), a second IGBT module (Q2), a third IGBT module (Q3) and a fourth IGBT module (Q4) are turned off completely, a sixth IGBT module (Q6) is turned on, and a fifth IGBT module (Q5) is kept turned off;

(12) after timing for 1us, the sixth IGBT module (Q6) is turned off, and after the second absorption capacitor (C2) releases energy, the sixth IGBT module (Q6) is turned off, so that the reliability is ensured;

(13) after the time (T-3) us, the third IGBT module (Q3) and the fourth IGBT module (Q4) resume switching and turn on the fifth IGBT module (Q5);

(14) after the timing is 1us, the fifth IGBT module (Q5) is turned off, and at the moment, the fifth IGBT module (Q5) and the sixth IGBT module (Q6) are simultaneously turned off and return to normal logic.

3. The method of claim 1, wherein the method further comprises: in the step (1), except for triggering the current limiting logic, namely the absolute value of the real-time current sampling value I of the output inductor (L) is smaller than Iset, the fifth IGBT module (Q5) does not act, the sixth IGBT module (Q6) does not act, at this time, the body diode of the fifth IGBT module (Q5) plays a role, and the body diode of the sixth IGBT module (Q6) plays a role.

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