JP2009232621A - Power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive power converter which does not require a new semiconductor device, and suppresses a switching surge caused by an internal semiconductor device. <P>SOLUTION: The power converter includes a serial circuit which is composed of first to fourth IGBTs Q1, Q2, Q3, and Q4 sequentially connected in series and is connected between a dc positive terminal P and a dc negative terminal N. According to the power converter, the IGBT Q1 is connected to the dc positive terminal P while the IGBT Q4 is connected to the dc negative terminal N. Smoothing capacitors CP and CN are serially connected between the terminals P and N. Free wheel diodes D1, D2, D3, and D4 are connected in parallel with the IGBTs Q1, Q2, Q3, and Q4, respectively. A point of connection between the smoothing capacitors CP and CN is set as a neutral point C. A diode D5 is connected between the neutral point C and a point of contact between the IGBTs Q1 and Q2 while a diode D6 is connected between the neutral point C and a point of contact between the IGBTs Q3 and Q4. The resistance values of resistances RG2 and RG3 connected respectively to the gate of the IGBT Q2 and that of the IGBT Q3 are determined to be larger than the resistance values of resistances RG1 and RG4 connected respectively to the gate of the IGBT Q1 and that of the IGBT Q4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power converter that is used, for example, as a neutral-point clamp type three-level power converter, and in which a semiconductor device is composed of a high-speed switching element such as an IGBT (Insulated Bipolar Transistor).

  FIG. 8 is a diagram illustrating an example of a conventional three-level power converter.

  A series circuit in which first to fourth semiconductor devices, for example, IGBTs Q1, Q2, Q3, and Q4 are sequentially connected in series is connected between a DC positive terminal P and a DC negative terminal N, and IGBTQ1, Q2, Of Q3 and Q4, the first IGBT Q1 is connected to the DC positive terminal P, the fourth IGBT Q4 is connected to the DC negative terminal N, and the first and second terminals between the DC positive terminal P and the DC negative terminal N are connected. Smoothing capacitors CP and CN are connected in series, and free wheel diodes D1, D2, D3, and D4 are connected in parallel to the IGBTs Q1, Q2, Q3, and Q4, and the connection points of the first and second smoothing capacitors CP and CN are connected. The neutral point C is an intermediate potential, and the first clamp diode D5 is connected between the neutral point C and the connection point of the first and second IGBTs Q1 and Q2, and the neutral point C and the third and third points are connected. Of between the connection point of IGBT Q3, Q4 which are connected to the second clamping diode D6.

  Such a configuration has the following problems. That is, the inner commutation loop when the inner IGBTs Q2 and Q3 (not connected to the terminals P and N) are turned on and off is the outer IGBT Q1 and Q4 switch (connected to the terminals P and N). Compared to the commutation loop, the number of devices passing through and the wiring path are long, so that the wiring inductance increases. Therefore, the switching surge voltage when the IGBTs Q2 and Q3 are turned on and off is higher than the switching surge voltage of the IGBTs Q1 and Q4. Therefore, in the actual design of the three-level power converter, the surge voltage of the IGBTs Q2 and Q3 There will be restrictions. Therefore, it is conceivable to provide a snubber circuit for each of the IGBTs Q1, Q2, Q3, and Q4. However, the snubber capacitor capacity increases, and if the switching frequency is further increased, the loss of the snubber circuit increases, so the switching frequency must be lowered. Therefore, the features of the IGBT cannot be fully utilized.

Patent Documents 1 and 2 describe inventions that can improve such problems. FIG. 9 is a diagram for explaining this, in which the IGBT Q5 is connected in parallel to the clamp diode D5 of FIG. 8, and the IGBT Q6 is connected in reverse parallel (opposite to the IGBT Q5) to the clamp diode D6. With this configuration, when the IGBTs Q2 and Q3 are switched, the IGBTs Q5 and Q6 can be switched and the switching surges of the IGBTs Q2 and Q3 can be suppressed.
JP-A-6-165511 (FIG. 1) JP 2006-42427 (FIGS. 1, 2, 3, etc.)

  However, since the power converter of FIG. 9 uses a clamp switching circuit in which IGBTs Q5 and Q6 are connected to clamp diodes D5 and D6, the number of objects to be controlled increases, and furthermore, an arm short circuit between the clamp switch and IGBTs Q1 and Q4. There is a problem that the circuit becomes complicated, the device becomes large, and the cost is increased.

  The present invention has been made to solve such problems, and an object thereof is to provide an inexpensive power converter that does not require a new semiconductor device and can suppress a switching surge of an inner semiconductor device. .

  In order to achieve the above-mentioned object, the invention corresponding to claim 1 is that a series circuit in which first to fourth semiconductor devices are connected in series is connected between a DC positive terminal and a DC negative terminal. The first semiconductor device of the semiconductor devices is connected to the DC positive terminal, the fourth semiconductor device is connected to the DC negative terminal, and a free wheel is connected in parallel to the semiconductor devices. A diode is connected, first and second smoothing capacitors are connected in series between the DC positive terminal and the DC negative terminal, a connection point of the first and second smoothing capacitors is a neutral point, and the neutral A first clamp diode is connected between a connection point between the neutral point and the first and second semiconductor devices, and a second point is connected between the neutral point and the connection point between the third and fourth semiconductor devices. of In the power converter to which the lamp diode is connected, the switching speed of the second and third semiconductor devices is configured to be slower than the switching speed of the first and fourth semiconductor devices. .

  In order to achieve the above object, the present invention corresponding to claim 2 is configured such that a series circuit in which first to fourth semiconductor devices are sequentially connected in series is connected between a DC positive terminal and a DC negative terminal. The first semiconductor device of the semiconductor devices is connected to the DC positive terminal, the fourth semiconductor device is connected to the DC negative terminal, and a free wheel is connected in parallel to the semiconductor devices. A diode is connected, a first and second smoothing capacitor are connected in series between a DC positive terminal and a DC negative terminal, and the connection point of the first and second smoothing capacitors is a neutral point that is an intermediate potential. , Connecting a first clamp diode between the neutral point and the connection point of the first and second semiconductor devices, and connecting the neutral point and the connection point of the third and fourth semiconductor devices. In the power converter to which the second clamp diode is connected, the resistance value connected to the gate of each of the second and third semiconductor devices is changed to the resistance value connected to the gate of each of the first and fourth semiconductor devices. The power converter is characterized in that it is configured larger than the value of.

  In order to achieve the above object, the invention corresponding to claim 3 is the invention in which a series circuit in which the first to fourth semiconductor devices are connected in series is connected between the DC positive terminal and the DC negative terminal. The first semiconductor device of the semiconductor devices is connected to the DC positive terminal, the fourth semiconductor device is connected to the DC negative terminal, and a free wheel is connected in parallel to the semiconductor devices. A diode is connected, a first and second smoothing capacitor are connected in series between a DC positive terminal and a DC negative terminal, and the connection point of the first and second smoothing capacitors is a neutral point that is an intermediate potential. , Connecting a first clamp diode between the neutral point and the connection point of the first and second semiconductor devices, and connecting the neutral point and the connection point of the third and fourth semiconductor devices. The In 2 of the power converter connected clamping diodes, the second and third semiconductor devices of the gate to - a power converter, characterized in that each emitter is connected to Kodensa.

  In order to achieve the above object, the invention corresponding to claim 4 is a series circuit in which first to fourth semiconductor devices are sequentially connected in series between a DC positive terminal and a DC negative terminal. The first semiconductor device of the semiconductor devices is connected to the DC positive terminal, the fourth semiconductor device is connected to the DC negative terminal, and a free wheel is connected in parallel to the semiconductor devices. A diode is connected, a first and second smoothing capacitor are connected in series between a DC positive terminal and a DC negative terminal, and the connection point of the first and second smoothing capacitors is a neutral point that is an intermediate potential. , Connecting a first clamp diode between the neutral point and the connection point of the first and second semiconductor devices, and connecting the neutral point and the connection point of the third and fourth semiconductor devices. In the power converter to which the second clamp diode is connected, the switching characteristics of the second and third semiconductor devices are made slower than the switching characteristics of the first and fourth semiconductor devices. It is a power converter.

  According to the present invention, it is possible to provide an inexpensive power converter that does not require a new IGBT and can suppress a switching surge of an inner semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic configuration diagram for explaining a first embodiment of the present invention. The premise of the embodiment of the present invention is as follows. That is, a series circuit in which first to fourth semiconductor devices such as IGBTs Q1, Q2, Q3, and Q4 are sequentially connected in series is connected between a DC positive terminal P and a DC negative terminal N, and IGBTQ1, Among the Q2, Q3, and Q4, the first IGBT Q1 is connected to the DC positive terminal P, the fourth IGBT Q4 is connected to the DC negative terminal N, and the first and first DC terminals are connected between the DC positive terminal P and the DC negative terminal N. Two smoothing capacitors CP and CN are connected in series, and free wheel diodes D1, D2, D3, and D4 are connected in parallel to the IGBTs Q1, Q2, Q3, and Q4, and the first and second smoothing capacitors CP and CN are connected. The point is a neutral point C that is an intermediate potential, and a first clamp diode D5 is connected between the neutral point C and the connection point of the first and second IGBTs Q1 and Q2, and the neutral point C and Between the third and fourth IGBT Q3, Q4 at the connection point is obtained by connecting the second clamp diode D6. In the first embodiment, the switching speeds of the second and third IGBTs Q2 and Q3 are configured to be slower than the switching speeds of the IGBTs Q1 and Q4 based on the above assumption.

  In FIG. 1, in order to realize this, the values of the resistors RG2 and RG3 connected to the gates of the IGBTs Q2 and Q3, that is, the gate drivers GD1, GD2, GD3, and GD4, respectively, are connected to the gates of the IGBTs Q1 and Q4, respectively. , And larger than the value of RG4.

  With such a configuration, it is possible to provide an inexpensive power converter that does not require new IGBTs Q5 and Q6 as shown in FIG. 9 and can suppress switching surges of the inner IGBTs Q2 and Q3.

  FIG. 2 is a diagram showing a unipolar modulation type PWM used in a three-level power converter, comparing two carrier waves (triangular waves) with a PWM voltage command that is a voltage reference, and the PWM voltage command is higher than the upper carrier wave. When it is larger, the gate of the IGBT Q1 is turned on, and when larger than the lower carrier wave, the IGBT Q2 gate is turned on. The gate signals are input to the IGBTs Q3 and Q4 in reverse logic of the IGBTs Q1 and Q2, respectively. Next, the IGBT Q2 is always in an ON state during a half cycle period that is a positive voltage command, and performs PWM switching during a negative voltage command period.

  Here, as shown in FIG. 2, the switching loss occurs in the IGBT Q2 in the negative voltage period and the AC current in the positive period, but the ratio of the switching loss to the IGBT Q2 loss is the outer switching element. If the power factor is 1.0, which is very small compared to the above, no switching loss theoretically occurs. Therefore, even if the switching speed, which is one of the factors that determine the magnitude of the switching loss, is reduced, the total losses of the IGBTs Q2 and Q3 are only slightly increased.

The same applies to the IGBT Q3.

  In this way, the switching speed of the IGBTs Q2 and Q3 can be reduced. As a result, it becomes possible to suppress the switching surge at the time of switching of the IGBTs Q2 and Q3, and since the switching losses of the IGBTs Q2 and Q3 are small, the influence on the overall loss is small and an inexpensive power converter can be obtained. Become.

  Here, the problem of FIG. 8 will be described in detail with reference to FIGS. IGBTs have a faster switching speed than GTOs (Thyristor elements), so switching losses can be reduced. However, current change rates at turn-on and off are high, and large surge voltages are often generated due to circuit wiring inductance. Are known. In particular, in the case of a three-level power converter, it is known that there are largely two commutation loops, and the surge voltage when the IGBTs Q2 and Q3 are turned on and off is larger than that of the IGBTs Q1 and Q4.

  FIG. 3 is a diagram illustrating a commutation loop of the outer switch, and a path returning to the IGBT Q1 through the IGBT Q1, the smoothing capacitor CP, and the clamp diode D5 is illustrated as an outer commutation loop (P). This outer commutation loop (P) acts as a wiring inductance when the IGBT Q1 is turned off and commutated to the clamp diode D5, and acts as a wiring inductance when the IGBT Q1 is turned on and D5 is turned off (recovery).

  Similarly, a path returning to the IGBT Q4 through Q5, the smoothing capacitor CN, and the clamp diode D6 is shown as an outer commutation loop (N) in FIG. This outer commutation loop (N) acts as a wiring inductance when the IGBT Q4 is turned off and commutated to the clamp diode D6. The IGBT Q4 is turned on and the clamp diode D6 is turned on. It acts as a wiring inductance when it is turned off (recovery).

  Next, FIG. 4 is a diagram showing the inner commutation loop (N) when the IGBT Q2 is turned on and off. The IGBT Q2 passes through the IGBT Q2, the clamp diode D5, the smoothing capacitor CN, and the freewheel diodes D4 and D3 to the IGBT Q2. This is a return path, and when the IGBT Q2 is turned off, it acts as a wiring inductance when current flows from the IGBT Q2 to the diodes D4 and D3. Further, when Q2 is turned on, the diode D4 is turned off (recovery), and acts as an inductance when current flows from the diodes D4 and D3 to the neutral point C, the diode D5, and the IGBT Q2.

  Similarly, FIG. 5 is a diagram showing the inner commutation loop (P) when the IGBT Q3 is turned on and off, and passes through the IGBT Q3, the clamp diode D6, the smoothing capacitor CP, and the free wheel diodes D1 and D2. This is a path returning to the IGBT Q3, and when the IGBT Q3 is turned off, it acts as a wiring inductance when current flows from the IGBT Q3 to the diodes D2 and D1. Further, when the IGBT Q3 is turned on, the diode D1 is turned off (recovery), and acts as an inductance when current flows from the diodes D2 and D1 to the neutral point C, the diode D6, and the IGBT Q3.

  The inner commutation loop when the above-described IGBTs Q2 and Q3 are turned on and off has a larger number of passing IGBTs and a longer wiring path than the IGBT Q1 and Q4, and the wiring inductance is increased. For this reason, the switching surge voltage when the IGBTs Q2 and Q3 are turned on and off is higher than the switching surge voltage of the IGBTs Q1 and Q4. Therefore, in the actual design of the power converter, the surges of the IGBTs Q2 and Q3 are as described above. There will be voltage constraints. For example, if a snubber circuit is provided for each IGBT, the snubber capacitor capacity will increase, and if the switching frequency is increased further, the loss of the snubber circuit will increase. It was not fully utilized.

  FIG. 6 is a schematic configuration diagram for explaining a second embodiment of the present invention. In FIG. 6, capacitors CG2 and CG3 are added between the gates and emitters of the IGBTs Q2 and Q3 in the circuit shown in FIG. By adding capacitors CG2 and CG3 between the gate and emitter of the IGBT, switching of the IGBT becomes soft, so that it is possible to suppress a switching surge at the time of the inner element switch with an inexpensive circuit. Here, the gate resistors RG1, RG2, RG3, and RG4 may have the same resistance value, and the switching surge can be further suppressed by increasing the gate resistances of the IGBTs Q2 and Q3 as shown in the first embodiment. Become.

  Next, a third embodiment of the present invention will be described with reference to FIG. The difference from the embodiment shown in FIG. 1 is that IGBTs having low speed characteristics are used for the IGBTs Q2 and Q3, and the switching characteristics at the time of switching of the IGBTs Q2 and Q3 can be suppressed by the characteristics of the IGBTs. Therefore, it is possible to provide an inexpensive power converter without adding a new circuit.

  In addition, you may combine the 1st-3rd embodiment mentioned above arbitrarily.

The schematic block diagram for demonstrating the 1st Embodiment of this invention. The principle diagram of unipolar modulation PWM. FIG. 9 is a diagram for explaining the effects of FIG. 1 and for explaining the problem of FIG. 8. FIG. 9 is a diagram for explaining the effects of FIG. 1 and for explaining the problem of FIG. 8. FIG. 9 is a diagram for explaining the effects of FIG. 1 and for explaining the problem of FIG. 8. The schematic block diagram for demonstrating the 2nd Embodiment of this invention. The schematic block diagram for demonstrating the 3rd Embodiment of this invention. The schematic block diagram for demonstrating the problem of the conventional 3 level power converter. The schematic block diagram for demonstrating the problem of patent documents 1, 2. FIG.

Explanation of symbols

P: DC positive terminal, N: DC negative terminal, CP, CN: smoothing capacitor, D1, D2, D3, D4: freewheel diode, C: neutral point, D5: first clamp diode, D6: second Clamp diode, Q1, Q2, Q3, Q4 ... IGBT,
GD1, GD2, GD3, GD4 ... gate drivers, RG1, RG2, RG3, RG4 ... resistors, CG2, CG3 ... capacitors.

Claims (5)

A series circuit in which first to fourth semiconductor devices are sequentially connected in series is connected between a direct current positive electrode terminal and a direct current negative electrode terminal, and the first semiconductor device of the semiconductor devices is connected to the direct current. Connected to the positive terminal, connected the fourth semiconductor device to the DC negative terminal, connected a free wheel diode in parallel to each semiconductor device, the first and the DC negative terminal between the first and the DC negative terminal A second smoothing capacitor is connected in series, a connection point between the first and second smoothing capacitors is a neutral point, and a first point is formed between the neutral point and the connection point between the first and second semiconductor devices. A power converter in which a second clamp diode is connected between the neutral point and the connection point of the third and fourth semiconductor devices.
The power converter characterized in that the switching speed of the second and third semiconductor devices is slower than the switching speed of the first and fourth semiconductor devices. A series circuit in which first to fourth semiconductor devices are sequentially connected in series is connected between a direct current positive electrode terminal and a direct current negative electrode terminal, and the first semiconductor device of the semiconductor devices is connected to the direct current. Connected to the positive electrode terminal, connected the fourth semiconductor device to the DC negative electrode terminal, connected a free wheel diode in parallel to each of the semiconductor devices, the first and the first between the DC positive electrode terminal and the DC negative electrode terminal Two smoothing capacitors are connected in series, and the connection point of the first and second smoothing capacitors is a neutral point that is an intermediate potential, and between the neutral point and the connection point of the first and second semiconductor devices. A power converter in which a first clamp diode is connected to the second clamp diode, and a second clamp diode is connected between the neutral point and the connection point of the third and fourth semiconductor devices.
An electric power characterized in that a value of a resistor connected to each of the gates of the second and third semiconductor devices is set larger than a value of a resistor connected to each of the gates of the first and fourth semiconductor devices. converter. A series circuit in which first to fourth semiconductor devices are sequentially connected in series is connected between a direct current positive electrode terminal and a direct current negative electrode terminal, and the first semiconductor device of the semiconductor devices is connected to the direct current. Connected to the positive electrode terminal, connected the fourth semiconductor device to the DC negative electrode terminal, connected a free wheel diode in parallel to each of the semiconductor devices, the first and the first between the DC positive electrode terminal and the DC negative electrode terminal Two smoothing capacitors are connected in series, and the connection point of the first and second smoothing capacitors is a neutral point that is an intermediate potential, and between the neutral point and the connection point of the first and second semiconductor devices. A power converter in which a first clamp diode is connected to the second clamp diode, and a second clamp diode is connected between the neutral point and the connection point of the third and fourth semiconductor devices.
A power converter, wherein a capacitor is connected between the gate and emitter of each of the second and third semiconductor devices. A series circuit in which first to fourth semiconductor devices are sequentially connected in series is connected between a direct current positive electrode terminal and a direct current negative electrode terminal, and the first semiconductor device of the semiconductor devices is connected to the direct current. Connected to the positive electrode terminal, connected the fourth semiconductor device to the DC negative electrode terminal, connected a free wheel diode in parallel to each of the semiconductor devices, the first and the first between the DC positive electrode terminal and the DC negative electrode terminal Two smoothing capacitors are connected in series, and the connection point of the first and second smoothing capacitors is a neutral point that is an intermediate potential, and between the neutral point and the connection point of the first and second semiconductor devices. A power converter in which a first clamp diode is connected to the second clamp diode, and a second clamp diode is connected between the neutral point and the connection point of the third and fourth semiconductor devices.
A power converter characterized in that the switching characteristics of the second and third semiconductor devices are made slower than the switching characteristics of the first and fourth semiconductor devices.   The power converter according to any one of claims 1 to 4, wherein the semiconductor device is an IGBT (Insulated Bipolar Transistor).

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