CN101582426A - Capless DRAM unit and preparation method thereof - Google Patents
Capless DRAM unit and preparation method thereof Download PDFInfo
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- CN101582426A CN101582426A CNA2009100851313A CN200910085131A CN101582426A CN 101582426 A CN101582426 A CN 101582426A CN A2009100851313 A CNA2009100851313 A CN A2009100851313A CN 200910085131 A CN200910085131 A CN 200910085131A CN 101582426 A CN101582426 A CN 101582426A
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Abstract
The invention discloses a capless DRAM unit and a preparation method thereof, belonging to the technical field of the dynamic random access memory (DRAM) in volatile memories. The DRAM unit comprises an N-type field effect transistor formed on the p-type doped bulk silicon substrate, a gate oxide and a polysilicon gate are arranged above the channel of the transistor, the two ends of the channel of the transistor are respectively connected with n+ source and n+ drain, a majority of the outer sides of the n+ source and n+ drain is covered by an L-type insulating layer, an n doped layer is arranged below the channel, the distance between the top of the doped layer and the silicon surface is less than the distance between the bottom of the L-type insulating layer and the silicon surface, the distance between the bottom of the doped layer and the silicon surface is more than the distance between the bottom of the L-type insulating layer and the silicon surface, thus separating the p-type doped region above the n doped layer from the p-type doped substrate below the n doped layer. The invention is prepared based on bulk silicon substrate and needs no SOI substrate, reduces the contact area of the region where electric potential floats and source/drain through the L-type insulating layer and improves the maintenance abilities of region storage holes.
Description
Technical field
The invention belongs to dynamic random access memory (DRAM) technical field in the volatile storage, be specifically related to a kind of capless DRAM unit and preparation method thereof.
Background technology
Along with the continuous growth of semi-conductor market demand, semiconductor memory technologies develops rapidly, and particularly dynamic random access memory DRAM technology has obtained swift and violent development, in storage market, has occupied main position.Common DRAM unit constitutes the 1T1C structure by a transistor (Transistor) and a capacitor (Capacitor), by whether stored charge is distinguished logic state on the capacitor.Market proposes more and more higher requirement to the memory property and the cell size of DRAM unit, has brought stern challenge for the 1T1C unit.In order to improve the unit performance and to dwindle cellar area, need on unit are, prepare the capacitor of big capacitance, the dielectric material that this need adopt the three-dimensional capacitance structure and adopt high-k.The complicated process of preparation of three-dimensional capacitance structure, the dielectric material of introducing high-k also needs to carry out long-term and careful research, and to guarantee the compatible and stable of material, this brings great difficulty for the further developing of DRAM unit of 1T1C structure.
At the problem that the 1T1C structure runs into, people have proposed a kind of capless DRAM unit.(TakashiOhsawa shown in document, et al., " Memory Design Using a One-Transistor Gain Cell on SOI ", IEEE Journal ofSolid-State Circuits, vol.37, no.11, pp.1510-1522,2002.), this capless DRAM unit realizes that based on a N type MOS (metal-oxide-semiconductor) memory (MOSFET) for preparing its cellular construction is as shown in Figure 1 on the SOI substrate.This DRAM unit constitutes device by the source that forms, leakage, tagma, grid oxygen, preceding grid on the SOI substrate, the silicon of SOI substrate oxygen buried layer below connects negative voltage as back of the body grid.Leak in the source, and preceding grid are all drawn, and the tagma does not have and draws, and forms the tagma of floating; When the unit one writing, the unit leaks and the equal positive bias of preceding grid, and metal-oxide-semiconductor is operated in the saturation region, and near the channel electrons ionization that bumps drain terminal produces electron hole pair, and electronics is siphoned away by drain terminal, and the hole is mobile to the electromotive force minimum point.The body that current potential is floated, this moment, current potential was lower, and the hole can be piled up in the tagma, finishes one writing.When needs are write " 0 ", can make the PN junction positively biased of body and source or leakage, the hole in the buoyancy aid is discharged.When the unit carries out store status when reading, pipe work is at linear zone, and the hole of buoyancy aid is raised the buoyancy aid electromotive force, is equivalent to body effect, can increase and read electric current.By reading the difference of electric current under two states, can distinguish the canned data state.Compare with the 1T1C structure, the capless unit has many-sided advantage.At first, its unit only comprises a transistor, and structure is more simple, has solved the technology and the material that are caused by electric capacity and has realized problems such as difficulty.Next, the cellar area that simple cellular construction has dwindled DRAM greatly.What is more important, the structure that need not electric capacity improves the processing compatibility of DRAM unit and logical block greatly.Reading on the mode, when 1T1C read the unit, the electric charge on the storage capacitance was reallocated between storage capacitance and bit line capacitance, and stored charge changes, and is destructiveness and reads; And the capless unit can realize that non-destructive reads, and when the linear work district read, still can there be the tagma in the hole of tagma accumulation, and the unit need not to carry out the operation of " regeneration " after reading, simplify the process that reads.
At present the chip of realizing based on the body silicon substrate is in occupation of the leading position in market.But in order to be formed for accumulating the tagma in hole, capless DRAM unit need be realized based on the SOI substrate, increased on the one hand the cost of substrate, also limited its application on the other hand, can't carry out the system integration with the other system module that realizes on the body silicon substrate.This two aspect has limited the development and the application of capless DRAM unit.
Summary of the invention
At above-mentioned capless DRAM unit problem, in order to reduce the cost of substrate, the application of expanding element improves the ability that the unit carries out the system integration, the present invention proposes innovation from the device architecture aspect, proposed a kind of capless DRAM unit of realizing based on the body silicon substrate.
A kind of capless DRAM unit, it is characterized in that, comprise a n type field effect transistor that on p type adulterate body silicon substrate, forms, this is gate oxide and polysilicon gate above transistorized raceway groove, these transistorized raceway groove two ends connect the n+ source respectively and n+ leaks, the major part that n+ source and n+ leak the outside has L type insulating barrier to surround, a n doped layer is arranged below raceway groove, the distance of the distance from top silicon face of this layer is less than the distance of the distance from bottom silicon face of L type insulating barrier, the distance of this layer distance from bottom silicon face is greater than the distance of the distance from bottom silicon face of L type insulating barrier, thereby the p type doped substrate of this n doped layer top p type doped region and n doped layer below is separated.
The thickness of described gate oxide is 1～6nm.
The thickness of described L type insulating barrier is 5-50nm.
Described n doped layer thickness is 50-200nm, its depth location need guarantee to make the distance of the distance of L type insulating barrier bottom and silicon face less than this doped layer distance from bottom silicon face, and the distance of L type insulating barrier bottom and silicon face is greater than the distance of this doped layer distance from top silicon face.
The advantage of this invention structure is, can prepare based on the body silicon substrate, need not the SOI substrate, by L type insulating barrier the tagma that current potential floats and the contact area of source/leakage are reduced, improve the hold facility in storage hole, tagma, L type insulating barrier has been also for adjacent cells tagma separately provides horizontal isolation in addition, thereby need not extra lateral isolation structural design, makes adjacent cells can adopt the structure of common source or shared leakage.
Another object of the present invention is to, a kind of method for preparing above-mentioned capless DRAM unit is provided, may further comprise the steps:
1) on p type body silicon substrate, adopts shallow-trench isolation (STI) definition active area;
2) bottom n doped layer injects;
3) thermal oxidation gate oxide, deposit polysilicon gate and hard mask layer, the photoetching of grid mask, etching hard mask layer and polysilicon gate form the grid line bar;
4) shallow doped source/drain regions is injected, deposit silicon dioxide, and this silicon dioxide of anisotropic etching forms the grid side wall;
5) be protection with hard mask, the anisotropic etch silicon, etching depth is that L type insulating barrier top and silicon face are apart from d1;
6) deposit oxidation-resistant material, this oxidation-resistant material of anisotropic etching forms anti-oxidant side wall;
7) be protection with hard mask, the anisotropic etch silicon, source-drain area forms the structure of depression, the depth d 2 of depression;
8) silicon of oxidation exposure forms silica, forms L type insulating barrier;
9) remove anti-oxidant side wall, material is leaked in the deposit source, and for stopping layer, chemico-mechanical polishing forms source-drain area with hard mask layer;
10) deposit low temperature oxide layer, the etching fairlead, depositing metal, photoetching, etching form metal wire, alloy, passivation.
Some key structure parameters among the present invention, as gate oxide thickness, the thickness and the degree of depth of L type insulating barrier, thickness of n doped layer or the like can adjust technological parameter according to the needs that design.The junction depth of d1 decision field-effect transistor may be selected to be 20-80nm, and the degree of depth in d2 determining source drain region may be selected to be 100-800nm.Thickness and the degree of depth, the depth d 2 of source-drain area depression and the thickness of L type insulating barrier oxidation by controlling bottom n doped layer in the prepared process, make the distance of the distance of L type insulating barrier bottom and silicon face less than n doped layer distance from bottom silicon face, and the distance of L type insulating barrier bottom and silicon face is greater than the distance of this doped layer distance from top silicon face, thereby the tagma that the formation current potential is floated.
Technique effect of the present invention is: 1) realize capless DRAM unit based on the body silicon substrate, expanded the application of capless DRAM unit, reduced the substrate cost; 2) the L type insulating barrier tagma and the source/leakage of floating for current potential provides good isolation, improves the hold facility in storage hole; 3) structure of L type insulating barrier encirclement source-drain area makes adjacent cells can adopt the design of common source or shared leakage for adjacent cells tagma separately provides horizontal isolation.
Description of drawings
Fig. 1 is the capless DRAM unit structural representation of realizing based on the SOI substrate;
Grid 102-leaks the 103-source before the 101-
The shallow doped source 106-grid of the shallow doped drain 105-of 104-side wall
107-oxygen buried layer 108-back of the body grid 109-p doped body region
The 110-gate oxide
Fig. 2 is a capless DRAM unit structural representation provided by the invention;
201-grid 202-leaks the 203-source
The shallow doped source 206-grid of the shallow doped drain 205-of 204-side wall
207-n doped layer 208-p doped substrate 209-p doped body region
210-gate oxide 211-L type insulating barrier 212-hard mask layer
Fig. 3 is the schematic cross-section of three adjacent cells of capless DRAM structure provided by the present invention
The grid of the grid 303-unit 3 of the grid 302-unit 2 of 301-unit 1
The source that the leakage 305-unit 1 of 304-unit 1 and unit 2 are shared
The source of the leakage 307-unit 3 that 306-unit 2 and unit 3 are shared
The p doped body region of the p doped body region 309-unit 2 of 308-unit 1
The p doped body region 311-grid side wall of 310-unit 3
312-gate oxide 313-L type insulating barrier
314-n doped layer 315-p doped substrate
The 316-hard mask layer
Fig. 4 (a)-(g) is a kind of capless DRAM unit preparation method's the technological process of one embodiment of the invention and the schematic diagram of each step institute counter structure thereof.
Among Fig. 4 (a)-(g), identical label is represented identical parts:
401-n doped layer 402-p doped substrate 403-top p doped layer
404-gate oxide 405-polysilicon gate 406-hard mask layer
The shallow doped source of the shallow doped drain 409-of 407-grid side wall 408-
The anti-oxidant side wall 411-of 410-tagma 412-L type insulating barrier
413-source 414-leaks
Embodiment
Describe the structure and the preparation method of capless DRAM unit provided by the present invention in detail below in conjunction with accompanying drawing, but be not construed as limiting the invention.
As shown in Figure 2, be the capless DRAM unit structure of present embodiment.This structure realizes based on the body silicon substrate.The major part in the source 203 and leakage 202 outsides has L type insulating barrier 211 to surround.There is a n doped layer 207 the raceway groove below.L type insulating barrier 211, n doped layer 207, and shallow doped drain 204 and shallow doped source 205 surround out p doped body region 209, this tagma do not have draws, and current potential is floated, and can be used for storing the hole.When cell operation, the n doped layer connects 0.4V voltage, source connecting to neutral voltage; When grid meet 1V, when missing 2V, near the hot electron ionization that the drain terminal of raceway groove, bumps, the p doped body region accumulation of floating at current potential in the hole of generation, stored information " 1 "; As grid 1V, leakage adds back bias voltage, and the hole of tagma storage is swept leakage, storage " 0 "; When reading, grid meet 1V, miss 0.2V, and whether the tagma stores the hole will obtain the different electric currents that reads, thereby distinguish stored information.
Capless DRAM unit provided by the present invention is realized based on the body silicon substrate, has eliminated the demand to the SOI substrate, has reduced the substrate cost, and has expanded range of application; L type insulating barrier has surrounded most source and drain region, and the PN junction junction area that make tagma and source, leak to form reduces, can reduce storage hole, tagma from the source, the leakage of leakage, prolong the information retention time; L type insulating barrier also plays the effect of adjacent cells lateral isolation, can be on the basis that does not increase cellar area, lateral isolation is provided, in addition, can also guarantee that adjacent cells can adopt the design of common source and shared leakage, promptly L type insulating barrier has been also for adjacent cells tagma separately provides horizontal isolation, thereby need not extra lateral isolation structural design, make adjacent cells can adopt the structure of common source or shared leakage, as shown in Figure 3.
As shown in Figure 4.Each cross-section structure shown in Fig. 4 (a)-(g) is corresponding with each step among this preparation method.
Below in conjunction with each accompanying drawing this preparation method is elaborated:
1) on p type body silicon substrate, adopt shallow-trench isolation (STI) definition active area, the STI degree of depth is 350nm;
2) bottom n doped layer injects, and n doped layer thickness is 100nm, and n doped layer top and silicon face distance are 300nm, shown in Fig. 4 (a);
3) thermal oxidation gate oxide 4nm, deposit polysilicon gate material carries out the doping of n type to polycrystalline silicon material and injects the short annealing activator impurity;
4) the silicon oxide deposition layer is as hard mask layer, the photoetching of grid mask, and etching hard mask layer and polysilicon gate form the grid line bar, shown in Fig. 4 (b) successively;
5) shallow doped source/drain regions is carried out n type doping injection, deposit silicon dioxide, and this silicon dioxide of anisotropic etching forms the grid side wall, shown in Fig. 4 (c);
6) be protective layer with the grid side wall, the silicon of anisotropic etching source-drain area, etching depth d1 are 80nm, shown in Fig. 4 (d);
7) deposit silicon nitride Si
3N
4, anisotropic etching Si
3N
4, form Si
3N
4Side wall is as anti-oxidant side wall;
8) with Si
3N
4Side wall is a protective layer, the anisotropic etch silicon, and source-drain area forms the structure of depression, and the depth d 2 of depression is 320nm, shown in Fig. 4 (e);
9) silicon of thermal oxidation exposure forms silica, and oxide thickness is 30nm, forms L type insulating barrier;
10) wet etching Si
3N
4Side wall exposes shallow doped source/drain regions;
11) the deposit polycrystalline silicon material leaks as the source, and for stopping layer, chemico-mechanical polishing is shown in Fig. 4 (f) with hard mask layer;
12) etch polysilicon material, the height of lifting is leaked in the reduction source, and source-drain area is carried out the doping of n type inject, and the annealing activator impurity, shown in Fig. 4 (g);
13) deposit low temperature oxide layer, the etching fairlead, depositing metal, photoetching, etching form metal wire, alloy, passivation.
Thickness and the degree of depth, the depth d 2 of source-drain area depression and the thickness of L type insulating barrier oxidation by controlling bottom n doped layer in the prepared process, make the distance of the distance of L type insulating barrier bottom and silicon face less than n doped layer distance from bottom silicon face, and the distance of L type insulating barrier bottom and silicon face is greater than the distance of this doped layer distance from top silicon face, thereby the tagma that the formation current potential is floated.
More than by specific embodiment capless DRAM unit structure provided by the present invention and preparation method thereof has been described, those skilled in the art is to be understood that, in the scope that does not break away from essence of the present invention, can make certain deformation or modification to cellular construction of the present invention; Its preparation method also is not limited to disclosed content among the embodiment.
Claims (9)
1, a kind of capless DRAM unit, it is characterized in that, comprise a n type field effect transistor that on p type adulterate body silicon substrate, forms, this is gate oxide and polysilicon gate above transistorized raceway groove, these transistorized raceway groove two ends connect the n+ source respectively and n+ leaks, the major part that n+ source and n+ leak the outside has L type insulating barrier to surround, a n doped layer is arranged below raceway groove, the distance of the distance from top silicon face of this layer is less than the distance of the distance from bottom silicon face of L type insulating barrier, the distance of this layer distance from bottom silicon face is greater than the distance of the distance from bottom silicon face of L type insulating barrier, thereby the p type doped substrate of this n doped layer top p type doped region and n doped layer below is separated.
2, capless DRAM unit as claimed in claim 1 is characterized in that, the thickness range of described gate oxide is 1～6nm.
3, capless DRAM unit as claimed in claim 1 or 2 is characterized in that, the thickness range of described L type insulating barrier is 5-50nm.
4, capless DRAM unit as claimed in claim 1 is characterized in that, described n doped layer thickness range is 50-200nm.
5, a kind of method for preparing capless DRAM unit may further comprise the steps:
1) on p type body silicon substrate, adopts shallow-trench isolation definition active area;
2) bottom n doped layer injects;
3) thermal oxidation gate oxide, deposit polysilicon gate and hard mask layer, the photoetching of grid mask, etching hard mask layer and polysilicon gate form the grid line bar;
4) shallow doped source/drain regions is injected, deposit silicon dioxide, and this silicon dioxide of anisotropic etching forms the grid side wall;
5) be protection with hard mask, the anisotropic etch silicon, etching depth is that L type insulating barrier top and silicon face are apart from d1;
6) deposit oxidation-resistant material, this oxidation-resistant material of anisotropic etching forms anti-oxidant side wall;
7) be protection with hard mask, the anisotropic etch silicon, source-drain area forms the structure of depression, and the degree of depth of depression is d2;
8) silicon of oxidation exposure forms silica, forms L type insulating barrier;
9) remove anti-oxidant side wall, material is leaked in the deposit source, and for stopping layer, chemico-mechanical polishing forms source-drain area with hard mask layer;
10) deposit low temperature oxide layer, the etching fairlead, depositing metal, photoetching, etching form metal wire, alloy, passivation.
6, method as claimed in claim 5 is characterized in that, L type insulating barrier top and silicon face are 20-80nm apart from the span of d1.
As claim 5 or 6 described methods, it is characterized in that 7, the span of described cup depth d2 is 100-800nm.
8, method as claimed in claim 5 is characterized in that, described n doped layer thickness range is 50-200nm.
As claim 5 or 8 described methods, it is characterized in that 9, the thickness range of described L type insulating barrier is 5-50nm.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683211A (en) * | 2011-03-14 | 2012-09-19 | 南亚科技股份有限公司 | A method of a dram memory with a two-sided transistor and a two-sided transistor structure |
| CN102683347A (en) * | 2012-05-22 | 2012-09-19 | 清华大学 | Dynamic random access memory unit and preparation method thereof |
| WO2013026237A1 (en) * | 2011-08-22 | 2013-02-28 | 中国科学院微电子研究所 | Semiconductor device |
| US8927966B2 (en) | 2012-05-22 | 2015-01-06 | Tsinghua University | Dynamic random access memory unit and method for fabricating the same |
| US9012963B2 (en) | 2011-08-22 | 2015-04-21 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device |
| CN110224028A (en) * | 2019-05-17 | 2019-09-10 | 南京邮电大学 | A kind of VDMOS device with the low EMI of L-type dielectric layer |
| CN112038405A (en) * | 2020-08-19 | 2020-12-04 | 深圳市紫光同创电子有限公司 | Field effect transistor, preparation method thereof, static random access memory and integrated circuit |
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| WO2001082379A1 (en) * | 2000-04-21 | 2001-11-01 | Hitachi, Ltd. | Semiconductor device |
| CN1622295A (en) * | 2004-12-21 | 2005-06-01 | 北京大学 | Method for preparing field effect transistor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2001082379A1 (en) * | 2000-04-21 | 2001-11-01 | Hitachi, Ltd. | Semiconductor device |
| CN1622295A (en) * | 2004-12-21 | 2005-06-01 | 北京大学 | Method for preparing field effect transistor |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683211A (en) * | 2011-03-14 | 2012-09-19 | 南亚科技股份有限公司 | A method of a dram memory with a two-sided transistor and a two-sided transistor structure |
| CN102683211B (en) * | 2011-03-14 | 2014-11-19 | 南亚科技股份有限公司 | A method of a dram memory with a two-sided transistor and a two-sided transistor structure |
| WO2013026237A1 (en) * | 2011-08-22 | 2013-02-28 | 中国科学院微电子研究所 | Semiconductor device |
| US9012963B2 (en) | 2011-08-22 | 2015-04-21 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device |
| CN102683347A (en) * | 2012-05-22 | 2012-09-19 | 清华大学 | Dynamic random access memory unit and preparation method thereof |
| US8927966B2 (en) | 2012-05-22 | 2015-01-06 | Tsinghua University | Dynamic random access memory unit and method for fabricating the same |
| CN102683347B (en) * | 2012-05-22 | 2015-06-24 | 清华大学 | Dynamic random access memory unit and preparation method thereof |
| CN110224028A (en) * | 2019-05-17 | 2019-09-10 | 南京邮电大学 | A kind of VDMOS device with the low EMI of L-type dielectric layer |
| CN110224028B (en) * | 2019-05-17 | 2022-06-17 | 南京邮电大学 | VDMOS device with L-type dielectric layer and low EMI |
| CN112038405A (en) * | 2020-08-19 | 2020-12-04 | 深圳市紫光同创电子有限公司 | Field effect transistor, preparation method thereof, static random access memory and integrated circuit |
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