CN102683347B - Dynamic random access memory unit and preparation method thereof - Google Patents
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- CN102683347B CN102683347B CN201210161248.7A CN201210161248A CN102683347B CN 102683347 B CN102683347 B CN 102683347B CN 201210161248 A CN201210161248 A CN 201210161248A CN 102683347 B CN102683347 B CN 102683347B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 238000003860 storage Methods 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 30
- 230000037361 pathway Effects 0.000 claims description 17
- 239000002800 charge carrier Substances 0.000 claims description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
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- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The invention provides a dynamic random access memory unit and a preparation method thereof. The dynamic random access memory unit comprises a substrate, and a transistor operating area and a charge storage area formed above the substrate, wherein the transistor operating area is separated from the charge storage area in space and is connected with the charge storage area through a charge channel; a source electrode, a drain electrode and a channel area are formed inside the transistor operating area; and a grid dielectric layer, a grid electrode, a source electrode metal layer and a drain electrode metal layer are formed above the transistor operating area. According to the dynamic random access memory unit, a generated carrier is stored in the charge storage area below a transistor; during data reading, charges stored in the charge storage area are not destroyed, the maximum refresh time is improved; and the transistor operating area is separated from the charge storage area in space, and therefore, the charge leakage is remarkably decreased and the keeping time of data is increased. The preparation method is simple in technology and compatible with the conventional CMOS (complementary metal-oxide-semiconductor) technology.
Description
Technical field
The invention belongs to essential electronic element field, relate to the preparation of semiconductor device, particularly a kind of DRAM cell and preparation method thereof.
Background technology
Along with the size of dynamic random access memory (DRAM) unit constantly reduces, integrated level is more and more higher.On the one hand, a difficulty transistor (transistor) and capacitor (capacitor) integrated is more and more higher.On the other hand, it has destructive read-write mode and its short data hold time to storage information, and making constantly increases by refreshing the power consumption brought.Therefore, in recent years, transistor (1T) the DRAM unit not comprising capacitor causes the extensive concern of people, its reason can be summed up as this structure and have compared with transistor capacitor (1T1C) DRAM cellular construction with traditional, technique is more simple and compatible with CMOS technology, meanwhile, during read-write, do not destroy the data of storage, higher data hold time can be obtained.
The structural representation of this 1T DRAM unit as shown in Figure 1, on insulator silicon (SOI) wafer substrate forms transistor arrangement, with tagma 015 for the doping of P type, source region 013 and drain region 014 are doped to example for N-type, when this 1T DRAM cell operation, its hole produced is housed in the accumulation layer formed between soi layer and buried regions 012, namely means that hole is kept at the place near N+ source region 013 and drain region 014.The hole that this mode stores is easy to be collected by the off-state leakage current in source region 013 and drain region 014, simultaneously due to the effect of Carrier recombination effect, the hole stored is disappeared very fast, limits data hold time, its application is narrowed.
Summary of the invention
The present invention is intended at least solve the technical problem existed in prior art, especially innovatively proposes a kind of DRAM cell and preparation method thereof.
In order to realize above-mentioned purpose of the present invention, according to a first aspect of the invention, the invention provides a kind of DRAM cell, it comprises: substrate; Be formed in transistor operation district and the electric charge storage region of described substrate, described transistor operation district is spatially separated with electric charge storage region, and described transistor operation district is connected with described electric charge storage region by charge pathway; Source electrode, drain electrode and channel region is formed in described transistor operation district; Gate dielectric layer, grid, source metal and drain metal layer is formed on described transistor operation district.
The charge carrier of generation is stored in the electric charge storage region below transistor by DRAM cell of the present invention, and transistor operation district is spatially separated with electric charge storage region, and charge leakage is significantly reduced, and improves the retention time of data.
In order to realize above-mentioned purpose of the present invention, according to a second aspect of the invention, the invention provides a kind of preparation method of DRAM cell, it comprises the steps:
S1: substrate is provided;
S2: form electric charge storage region and transistor operation district over the substrate, described electric charge storage region is spatially separated with transistor operation district, and described electric charge storage region is connected by charge pathway with transistor operation district;
S3: form source electrode, drain electrode and channel region in described transistor operation district;
S4: be formed with gate dielectric layer, grid, source metal and drain metal layer on described transistor operation district.
Preparation method's technique of the present invention is simple and compatible with traditional CMOS technology, and its DRAM cell formed, in the process read, can not destroy the electric charge be stored in electric charge storage region, improve maximum refresh time.
In a preferred embodiment of the invention, the quantum well for storing charge carrier is comprised in electric charge storage region.
The present invention, by introducing the quantum well storing charge carrier in charge carrier memory block, considerably improves the retention time of data, improves maximum refresh time.
Additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 is the structural representation of 1T DRAM unit in prior art;
Fig. 2 is the structural representation of the first preferred implementation of DRAM cell of the present invention;
Fig. 3 is the structural representation of the second preferred implementation of DRAM cell of the present invention;
Fig. 4-Fig. 9 is the processing step schematic diagram of DRAM cell shown in Fig. 2.
Reference numeral:
011 substrate; 012 buried regions; 013 source region; 014 drain region; 015 tagma; 016 gate dielectric layer; 017 grid; 1 SOI substrate; 2 buried regions; 3 electric charge storage regions; 4 isolated areas; 51 epitaxial loayers; 5 transistor operation districts; 6 mask layers; 7 isolation channels; 8 source electrodes; 9 drain electrodes; 10 gate dielectric layers; 11 grids; 12 source metal; 13 drain metal layer; 141 quantum well barrier layers; 142 quantum well potential well layers.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
In describing the invention, it will be appreciated that, term " longitudinal direction ", " transverse direction ", " on ", D score, "front", "rear", "left", "right", " vertically ", " level ", " top ", " end " " interior ", the orientation of the instruction such as " outward " or position relationship be based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as limitation of the present invention.
In describing the invention, unless otherwise prescribed and limit, it should be noted that, term " installation ", " being connected ", " connection " should be interpreted broadly, such as, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be directly be connected, also indirectly can be connected by intermediary, for the ordinary skill in the art, the concrete meaning of above-mentioned term can be understood as the case may be.
Fig. 2 is the structural representation of the first preferred implementation of DRAM cell of the present invention, and be only the size giving each region of signal in figure, concrete size can design according to the requirement of device parameters.As seen from the figure, DRAM cell of the present invention comprises substrate, this substrate can be any backing material preparing DRAM cell, can be specifically but be not limited to SOI, silicon, germanium, GaAs, in the present embodiment, preferred employing SOI, this SOI comprise the buried regions 2 of SOI substrate 1 and upper formation thereof, and this buried regions 2 can be specifically but be not limited to the oxide of silicon, the oxide of germanium.Transistor operation district 5 and electric charge storage region 3 is formed on buried regions 2, the material of transistor operation district 5 and electric charge storage region 3 can be specifically but be not limited to silicon, germanium, GaAs, in the present embodiment, the material that electric charge storage region 3 preferably adopts is silicon, when the doping type of the channel region in transistor operation district 5 is P type, electric charge storage region 3 is intrinsic region or P type doped region, when the doping type of the channel region in transistor operation district 5 is N-type, this electric charge storage region 3 is intrinsic region or N-type doped region.This transistor operation district 5 is spatially separated with electric charge storage region 3, and this transistor operation district 5 is connected with electric charge storage region 3 by charge pathway, in the preferred embodiment of the present invention, transistor operation district 5 is spatially separated by isolated area 4 with electric charge storage region 3, the material of this isolated area 4 is non-conductive, isolated area 4 has through hole, and this through hole is charge pathway.In the present embodiment, charge pathway is 5nm-100nm along the length being parallel to transistor channel length direction, is 2nm-50nm along the degree of depth perpendicular to transistor channel length direction.In transistor operation district 5, be formed with source electrode 8, drain electrode 9 and channel region, on transistor operation district 5, be formed with gate dielectric layer 10, grid 11, source metal 12 and drain metal layer 13.The charge carrier produced during work is stored in electric charge storage region 3 by this DRAM cell, charge leakage is significantly reduced, transistor operation district 5 is spatially separated with electric charge storage region 3, during transistor, the electric charge stored in electric charge storage region 3 can not be revealed, and improves the retention time of data.
Fig. 3 is the structural representation of the second preferred implementation of DRAM cell of the present invention, as seen from the figure, the structure of the DRAM cell of this execution mode is substantially identical with the structure of DRAM cell shown in Fig. 2, difference is the quantum well be formed with in electric charge storage region 3 for storing charge carrier, illustrate only the structure of 1 quantum well in figure, the quantity of concrete quantum well can require to design according to actual parameter.When the doping type of the channel region in transistor operation district 5 is P type, electric charge storage region 3 is intrinsic region or P type doped region, in order to store hole, the material of the barrier layer 141 of the quantum well of electric charge storage region 3 is strain SiGe, and the material of the potential well layer 142 of quantum well is relaxation Si.When the doping type of the channel region in transistor operation district 5 is N-type, this electric charge storage region 3 is intrinsic region or N-type doped region, in order to store electrons, the material of the barrier layer 141 of electric charge storage region quantum well is relaxation SiGe, the material of the potential well layer 142 of quantum well is strain Si, the present invention, by introducing the quantum well structure storing charge carrier in charge carrier memory block, can significantly improve the retention time of data, improve maximum refresh time.
The invention allows for a kind of preparation method of DRAM cell, it comprises the steps:
S1: substrate is provided;
S2: form electric charge storage region 3 and transistor operation district 5 on substrate, this electric charge storage region 3 is spatially separated with transistor operation district 5, and electric charge storage region 3 is connected by charge pathway with transistor operation district 5;
S3: form source electrode 8, drain electrode 9 and channel region in transistor operation district 5;
S4: be formed with gate dielectric layer 10, grid 11, source metal 12 and drain metal layer 13 on transistor operation district 5.
Fig. 4-Fig. 9 is the processing step schematic diagram of DRAM cell shown in Fig. 2, as seen from the figure, prepares DRAM cell of the present invention and needs following steps:
The first step: as shown in Figure 4, substrate is provided, this substrate can be any backing material preparing DRAM cell, can be specifically but be not limited to SOI, silicon, germanium, GaAs, in the present embodiment, adopt SOI substrate, it comprises the buried regions 2 of SOI substrate 1 and upper formation thereof, and this buried regions 2 can be specifically but be not limited to the oxide of silicon, the oxide of germanium.
Second step: as shown in Figure 5-Figure 7, buried regions 2 is formed electric charge storage region 3 and transistor operation district 5, this electric charge storage region 3 is spatially separated with transistor operation district 5, electric charge storage region 3 is connected by charge pathway with transistor operation district 5, in the present embodiment, electric charge storage region 3 is spatially separated by isolated area 4 with transistor operation district 5, and isolated area 4 has through hole, this through hole is charge pathway, and the material of this isolated area 4 is non-conductive.In the present embodiment, electric charge storage region 3, the forming step in isolated area 4 and transistor operation district 5 is: first, as shown in Figure 5, buried regions 2 is formed electric charge storage region 3, the concrete grammar forming electric charge storage region 3 can be but be not limited to chemical vapor deposition, then, electric charge storage region 3 is formed isolated area 4 and epitaxial loayer 51, the concrete grammar forming isolated area 4 and epitaxial loayer 51 can be but be not limited to chemical vapor deposition, in the present embodiment, the material of this epitaxial loayer 51 is identical with the material in transistor operation district 5, again, as shown in Figure 6, epitaxial loayer 51 is formed mask layer 6, then photoetching, under the sheltering of mask layer 6, etching epitaxial loayer 51 and isolated area 4 are until electric charge storage region 3 exposes, isolated area 4 forms through hole, be charge pathway, in the present embodiment, charge pathway is 5nm-100nm along the length being parallel to transistor channel length direction, be 2nm-50nm along the degree of depth perpendicular to transistor channel length direction, finally, remove mask layer 6, as shown in Figure 7, epitaxial loayer 51 with the electric charge storage region 3 exposed carry out epitaxial growth, concrete epitaxial growth method can be but be not limited to chemical vapor deposition, the epitaxial loayer of this step growth and the common transistor formed operating space 5 of epitaxial loayer 51.
As shown in Figure 8, the present invention can form isolation channel 7 around DRAM cell, for isolating with other DRAM cells.
In the present embodiment, first electric conducting material can be used when electric charge storage region 3 is formed isolated area 4, behind formation transistor operation district 5, as shown in Figure 9, the electric conducting material of isolated area 4 is removed, be packed into non electrically conductive material, this non electrically conductive material is specifically as follows but is not limited to the oxide of silicon.
3rd step: formation source electrode 8, drain electrode 9 and channel region in transistor operation district 5, the method forming source electrode 8 and drain electrode 9 can be but be not limited to photoetching, carries out ion implantation, and spreads, the method for annealing when mask is sheltered.
4th step: be formed with gate dielectric layer 10, grid 11, source metal 12 and drain metal layer 13 on transistor operation district 5, forms the structure shown in Fig. 2.
According to the preparation method of DRAM cell of the present invention, in the preferred embodiment of the present invention, the preparation method of silica-based DRAM cell is: first, by CVD (Chemical Vapor Deposition) method deposit buried regions 2 in lightly doped P type SOI substrate 1, in present embodiment, to make DRAM cell on p-type substrate, for device prepared by n-type substrate, adulterate according to contrary doping type.Then, buried regions 2 utilize the lightly doped P-type silicon of CVD (Chemical Vapor Deposition) method deposit as electric charge storage region 3.Again, the SiGe layer utilizing CVD (Chemical Vapor Deposition) method to be formed successively in electric charge storage region 3 to strain completely and Si layer, this SiGe layer strained completely is as sacrifice layer.Subsequently, by plasma enhanced CVD method deposit one deck Si
3n
4layer, as mask layer 6, and utilizes photoetching in conjunction with lithographic technique, forms patterned window, by the Si in window
3n
4layer, Si epitaxial loayer and SiGe layer etching is got rid of, and forms conductive channel.Then, Si is removed
3n
4layer, utilizes CVD (Chemical Vapor Deposition) method to carry out Si extension, forms transistor operation district 5.Subsequently, by etching technics, the isolation channel 7 between formative dynamics random-access memory unit, removes the SiGe layer in isolated area 4, carries out oxide layer filling.Finally, photoetching in transistor operation district 5, carries out ion implantation when mask is sheltered, and spread, annealing, forms source electrode 8, drain electrode 9 and channel region, is formed with gate dielectric layer 10, grid 11, source metal 12 and drain metal layer 13 on transistor operation district 5.
In the other preferred implementation of the preparation method of DRAM cell of the present invention, in electric charge storage region, 3 can also be formed with the quantum well for storing charge carrier.When the doping type of the channel region in transistor operation district 5 is P type, the material of the barrier layer 141 of electric charge storage region quantum well is strain SiGe, and the material of the potential well layer 142 of quantum well is relaxation Si.When the doping type of the channel region in transistor operation district 5 is N-type, the material of the barrier layer 141 of electric charge storage region quantum well is relaxation SiGe, and the material of the potential well layer 142 of quantum well is strain Si.The formation method of this quantum well can be but be not limited to chemical vapor deposition, the quantity of quantum well, and the thickness of potential well layer and barrier layer can require design according to actual parameter.
Utilize the DRAM cell that method of the present invention is formed, how much realized the storage of information by the electric charge changed in electric charge storage region 3.Utilize hot carrier injection effect, source electrode is connect comparatively electronegative potential, drain electrode connects high potential, grid connects high potential, and the charge carrier so in raceway groove at drain terminal place, hot carrier's effect can occur, and produces substrate hole current, thus by iunjected charge memory block, hole 3, this is the process of one writing.When writing " 0 ", by any one in source electrode, drain electrode or be set to lower voltage simultaneously, making source electrode, drain electrode and the PN junction generation positively biased in tagma, thus electric charge is released from electric charge storage region 3.When read operation, because one state is different with the cut-in voltage of " 0 " state, by adding a voltage on grid 11, namely can by judging that the break-make of device judges the information stored.The charge carrier of generation is stored in the electric charge storage region 3 below transistor by DRAM cell of the present invention, and transistor operation district 5 is spatially separated with electric charge storage region 3, and charge leakage is significantly reduced, and improves the retention time of data.In the process of digital independent, the electric charge be stored in electric charge storage region 3 can not be destroyed, improve maximum refresh time.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and describe embodiments of the invention, those having ordinary skill in the art will appreciate that: can carry out multiple change, amendment, replacement and modification to these embodiments when not departing from principle of the present invention and aim, scope of the present invention is by claim and equivalents thereof.
Claims (7)
1. a DRAM cell, is characterized in that, comprising:
Substrate;
Be formed in transistor operation district and the electric charge storage region of described substrate, described transistor operation district is spatially separated by isolated area with electric charge storage region, the material of described isolated area is non-conductive, described isolated area has through hole, described through hole is charge pathway, described transistor operation district is connected with described electric charge storage region by charge pathway, wherein, described charge pathway is 5nm-100nm along the length being parallel to transistor channel length direction, be 2nm-50nm along the degree of depth perpendicular to transistor channel length direction, the quantum well for storing charge carrier is comprised in described electric charge storage region,
Source electrode, drain electrode and channel region is formed in described transistor operation district;
Gate dielectric layer is formed on described transistor operation district, grid, source metal and drain metal layer, wherein, when the doping type of the channel region in described transistor operation district is P type, described electric charge storage region is intrinsic region or P type doped region, the material of the barrier layer of described electric charge storage region quantum well is strain SiGe, the material of the potential well layer of described quantum well is relaxation Si, when the doping type of the channel region in described transistor operation district is N-type, described electric charge storage region is intrinsic region or N-type doped region, the material of the barrier layer of described electric charge storage region quantum well is relaxation SiGe, the material of the potential well layer of described quantum well is strain Si.
2. DRAM cell as claimed in claim 1, it is characterized in that, the material of described electric charge storage region is silicon.
3. a preparation method for DRAM cell, is characterized in that, comprises the steps:
S1: substrate is provided;
S2: form electric charge storage region over the substrate, isolated area and transistor operation district, described electric charge storage region is spatially separated by described isolated area with transistor operation district, the material of described isolated area is non-conductive, described isolated area has through hole, described through hole is charge pathway, described electric charge storage region is connected by charge pathway with transistor operation district, wherein, described charge pathway is 5nm-100nm along the length being parallel to transistor channel length direction, be 2nm-50nm along the degree of depth perpendicular to transistor channel length direction, the quantum well for storing charge carrier is comprised in described electric charge storage region,
S3: form source electrode, drain electrode and channel region in described transistor operation district;
S4: be formed with gate dielectric layer, grid, source metal and drain metal layer on described transistor operation district,
Wherein, when the doping type of the channel region in described transistor operation district is P type, described electric charge storage region is intrinsic region or P type doped region, the material of the barrier layer of described electric charge storage region quantum well is strain SiGe, the material of the potential well layer of described quantum well is relaxation Si, when the doping type of the channel region in described transistor operation district is N-type, described electric charge storage region is intrinsic region or N-type doped region, the material of the barrier layer of described electric charge storage region quantum well is relaxation SiGe, and the material of the potential well layer of described quantum well is strain Si.
4. the preparation method of DRAM cell as claimed in claim 3, is characterized in that, the forming step in described electric charge storage region, isolated area and transistor operation district is:
S21: form electric charge storage region over the substrate;
S22: form isolated area on described electric charge storage region,
S23: etch described isolated area and form charge pathway;
S24: form transistor operation district in described isolated area.
5. the preparation method of DRAM cell as claimed in claim 4, is characterized in that, the isolated area formed in step S22 uses electric conducting material, after step S24, is removed by the electric conducting material of isolated area, is packed into non electrically conductive material.
6. the preparation method of DRAM cell as claimed in claim 3, is characterized in that, after described step S2, around DRAM cell, form isolation channel.
7. the preparation method of DRAM cell as claimed in claim 3, it is characterized in that, the material of described electric charge storage region is silicon.
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| US13/703,722 US8927966B2 (en) | 2012-05-22 | 2012-10-18 | Dynamic random access memory unit and method for fabricating the same |
| PCT/CN2012/083158 WO2013174094A1 (en) | 2012-05-22 | 2012-10-18 | Dynamic random access memory cell and fabrication method therefor |
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| US8927966B2 (en) | 2012-05-22 | 2015-01-06 | Tsinghua University | Dynamic random access memory unit and method for fabricating the same |
| US8963251B2 (en) * | 2013-06-12 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with strain technique |
| CN108767014A (en) * | 2018-06-06 | 2018-11-06 | 中国科学院宁波材料技术与工程研究所 | Field-effect transistor, storage memory and its application |
| CN112017720A (en) * | 2020-07-09 | 2020-12-01 | 广东美的白色家电技术创新中心有限公司 | MOS (Metal oxide semiconductor) tube, storage unit, memory and electronic equipment |
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| US6888200B2 (en) * | 2002-08-30 | 2005-05-03 | Micron Technology Inc. | One transistor SOI non-volatile random access memory cell |
| CN101582426A (en) * | 2009-06-02 | 2009-11-18 | 北京大学 | Capless DRAM unit and preparation method thereof |
| CN102184926A (en) * | 2010-01-14 | 2011-09-14 | 硅绝缘体技术有限公司 | Memory cell in which the channel passes through a buried dielectric layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6888200B2 (en) * | 2002-08-30 | 2005-05-03 | Micron Technology Inc. | One transistor SOI non-volatile random access memory cell |
| CN101582426A (en) * | 2009-06-02 | 2009-11-18 | 北京大学 | Capless DRAM unit and preparation method thereof |
| CN102184926A (en) * | 2010-01-14 | 2011-09-14 | 硅绝缘体技术有限公司 | Memory cell in which the channel passes through a buried dielectric layer |
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