CN102376715B - Capacitor-free dynamic random access memory structure and preparation method thereof - Google Patents
Capacitor-free dynamic random access memory structure and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a capacitor-free dynamic random access memory structure and a preparation method thereof. On the premise of meeting the requirement of high leakage voltage of high impact ionization rate, the capacitor-free dynamic random access memory structure increases the electrical thickness of the gate dielectric in a source-drain junction region by adopting different gate dielectric materials or gate dielectric thicknesses near the region, thereby effectively reducing the electric field in the vertical direction, and simultaneously improves the gate control capability and inhibits the short channel effect by adopting a thin oxide layer or a high-K material in the central region of a channel. The structure can effectively inhibit the degradation of a gate dielectric, improve the reliability (durability) of the storage unit and facilitate the scaling-down of a device, and simultaneously, the capacitor-free structure completely avoids the complex process of a capacitor structure in the conventional 1T1C structure. The adopted manufacturing process is completely compatible with the conventional logic process, and is also beneficial to the integration of a high-density three-dimensional process.
Description
Technical field
The present invention relates to microelectronics manufacture and memory technology field, relate in particular to a kind of highly reliable without capacitor type dynamic random access memory structure and preparation method thereof.
Background technology
Microelectronic product is mainly divided into logical device and the large class of memory device two.As a pith of memory device, dynamic RAM (DRAM) can provide the high-speed read-write operation of data, yet the in the situation that of power down, canned data is easy to lose, and is therefore called as volatile semiconductor memory.In computer system, dynamic RAM is generally between high speed microprocessor and the non-volatility memorizer of low speed, and for realizing, high-speed data is processed and the coupling of low speed data access access.The development of information technology makes Developing High-speed, highdensity DRAM become an important directions of current memory technology research.
Traditional dynamic RAM part is generally consisted of an access transistor and an electric capacity (1T1C).Electric capacity is for the preservation of data, and the read-write of data is by transistor controls.Scaled along with device size, conventional 1T1C structure has been difficult to meet the requirement to the large storage capacity of transistorized low Leakage Current and electric capacity, no matter is that groove type capacitance or stacking-type electric capacity are also difficult to complete no-load voltage ratio on technique realizes simultaneously.For this reason, find the focus that new high speed dynamic random access memory structure becomes current memory technology research.
At present, adopt the memory cell (FBC) of floater effect because its technologic full compatibility and be easy to the extensive concern that no-load voltage ratio has been subject to industry.Conventional FBC structure can either realize on SOI substrate, also can on body silicon substrate, realize, and as shown in Figure 1, hole blocking layer can adopt SiO to basic structure here
2, also can adopt the realizations such as N-shaped silicon doping.Yet research finds, this floating body memory cell structure realize high-speed data erasable in, be faced with the challenge that comes from device reliability aspect.Fig. 2 has provided two kinds of programming modes for floating body memory cell.For hot electron programming pattern, (Fig. 2 a), applies a large malleation to leakage, to grid, applies a transistorized cut-in voltage Vg, Vg=Vd/4～Vd/2.In this case, electronics is obtaining higher energy from source to leaking motion process, near there is ionization by collision under the high electric field of drain terminal, is producing electron hole pair, and the hole of generation will be moved to substrate and form accumulation in the place near hole blocking layer.Because the accumulation in hole causes substrate potential to raise, will cause transistorized threshold voltage to reduce, we claim this state for writing state (" 1 ").Under this programming mode, because the drain terminal voltage that need to make of high impact ionization rate is greater than gate voltage, such as Vg=0.5V, Vd=2V, Vs=0V, therefore the hole producing is when moving to substrate, still some moves to gate medium, thereby near drain junction, produce interface trap and oxide traps, along with repeatedly program erase operation, hole in this gate medium will further be accumulated, and causes the threshold voltage of drain region annex raceway groove to reduce, thereby in the time of data reading, causes information disturbance or make mistakes.Programming mode (Fig. 2 b) for band-to-band-tunneling BTBT, conventionally source is floated, drain terminal voltage is much larger than gate voltage, such as Vg=0V, Vd=4V, under this pattern, electronics will be mobile to leaking by band-to-band-tunneling, the hole producing, when moving to substrate, can enter in grid at drain junction annex because potential difference large between grid leak will have part, causes equally the degeneration of gate medium to cause disturbance of data or read error.Although reduce the degeneration that drain terminal voltage can partly suppress this gate dielectric layer, yet low drain terminal voltage is when obviously thereby reduction ionization by collision probability is unfavorable for that hole produces, the probability that the electronics that its ionization by collision produces enters gate medium can rise rapidly, can cause the integrity problem of device equally, therefore adopting low drain voltage is not effective means.
Therefore, must find the gate medium vertical electric field that a kind of mode reduces grid source, grid leak crossover region annex when can effectively improving impact ionization rate.The present invention will be mainly for this problem, by employing, control the material of gate medium and the mode of thickness near source-and-drain junction and effectively control electric field, and press to obtain large ionization by collision probability by maintaining high leakage, thereby realize highly reliable without electric capacity dynamic RAM unit.
Summary of the invention
(1) technical problem that will solve
Because conventional floating body memory cell (FBC) can produce interface trap and oxide traps in the erasable operating process of data near knot, this will cause gate medium to degenerate, affect the threshold voltage of device, and then cause data read disturbance or read and make mistakes, for this reason, main purpose of the present invention is to attempt to suppress vertical gate electric field near knot, simultaneously the mode of enhanced level drain terminal electric field designs, and then provides a kind of highly reliable without capacitor type dynamic random access memory structure and preparation method thereof.
(2) technical scheme
For achieving the above object, the invention provides a kind of without capacitor type dynamic random access memory structure, this structure comprises substrate, hole blocking layer, raceway groove, source-drain area, gate medium district and gate electrode from the bottom to top successively, this structure is by adopting different gate dielectric materials or grid medium thickness near the source-and-drain junction district in channel region, increase the electrical thickness of the gate medium in this region, thereby effectively reduce the electric field of vertical direction, by adopting thin oxide layer at raceway groove middle section or adopting hafnium, improve grid-control ability and suppress short-channel effect simultaneously.
In such scheme, described substrate is body silicon substrate, SOI substrate, GOI substrate or stress silicon substrate; Described hole blocking layer adopts insulating barrier SiO
2, SiC or SiN, or adopt N-shaped doped silicon, or adopt hole potential well material SiGe or Ge.
In such scheme, near source, leak with first gate medium of grid crossover region part and adopt advanced low-k materials SiO
2or Si
3n
4, or the method that employing forms thicker gate dielectric material by control realizes; And the gate dielectric layer of raceway groove middle section adopts one deck or the sandwich construction HfO of high dielectric constant material
2, HfSiON, AlO, SiO/HfO, SiO/HfSiON or SiO/AlO, or by control, form thinner gate medium and realize.
In such scheme, described gate electrode adopts polygate electrodes, metal gate electrode, silicide, nitride or sandwich construction, and wherein silicide is CoSi or NiSi, and nitride is TaN, TiN or WN, and sandwich construction is TaN/Poly.
For achieving the above object, the present invention also provides a kind of preparation method without capacitor type dynamic random access memory structure, and method comprises:
Step 1: form hole blocking layer on substrate;
Step 2: adopt STI technique forming unit isolated area on the hole blocking layer forming;
Step 3: deposit gate insulation layer and mask layer;
Step 4: exposure definition gate region, and etching is removed mask layer and the dielectric layer of gate region;
Step 5: the mask layer of non-etch areas is carried out to isotropic control etching, complete the reduction of mask layer, form grid source/leakage crossover region;
Step 6: adopt the film dielectric layer of the method formation channel region of oxidation or deposit, then deposit gate material, finally adopts the method for chemico-mechanical polishing to complete planarization, forms gate insulation layer and gate electrode;
Step 7: adopt etching technics to remove mask layer and expose source-drain area;
Step 8: adopt method implanted dopant P or the As of Implantation, complete the automatic standard of source-drain area, leakage doped region, formation source;
Step 9: deposition insulating layer material, and adopt CMP method to realize the planarization of ILD layer;
Step 10: complete contact hole and metal connecting line.
In such scheme, the described hole blocking layer that forms on substrate, is the high barrier material SiO of deposit on substrate
2, SiC or SiN and form, or substrate is carried out to n+ doping and injects the N-shaped doped silicon forming.
In such scheme, described on substrate, form hole blocking layer after, further comprise: the doping of carrying out raceway groove injects to adjust the threshold voltage of device.
In such scheme, described step 2 comprises: on the hole blocking layer forming, adopt the isolated area of the method forming unit of etching, complete insulating material SiO
2filling, then adopt chemico-mechanical polishing to complete planarization.
In such scheme, the gate insulation layer of deposit described in step 3 is SiO
2, the mask layer of deposit is Si
3n
4.
In such scheme, described step 10 comprises: adopt photoetching process to complete the etching of contact hole, adopt depositing technics to complete the metal filled of contact hole, complete subsequently the deposit of metallic film, finally adopt chemical wet etching technique to complete the definition of metal connecting line.
In such scheme, the definition of described grid source, grid leak crossover region, adopts the method that laterally reduces mask layer to realize, or adopts side wall definition method to realize.
(3) beneficial effect
From technique scheme, can find out, the present invention has following beneficial effect:
The present invention is meeting desired high the leakage under the prerequisite of pressing of high impact ionization rate, by to adopting different gate dielectric materials or grid medium thickness to increase the electrical thickness of the gate medium in this region near source-and-drain junction district, thereby effectively reduce the electric field of vertical direction, by the thin oxide layer at raceway groove middle section or employing hafnium, thereby improved grid-control ability, suppressed short-channel effect simultaneously.This composition of sample, when the degeneration of suppressor medium, improving the reliability (durability) of memory cell, is also conducive to the scaled of this memory device.Meanwhile, this has been avoided the complicated technology of the capacitance structure in conventional 1T1C structure completely without capacitance structure.The manufacturing process that it adopts and conventional logic process are completely compatible, and the technique that is also conducive to density three-dimensional is integrated.
Accompanying drawing explanation
Fig. 1 is conventional without electric capacity floating body memory cell structure (PRIORART);
Fig. 2 is the programming mode of floating body memory cell, and wherein (a) is CHE programming mode, is (b) BTBT pattern;
Fig. 3 is the schematic diagram without the highly reliable floating body memory cell structure of electric capacity (symmetrical gate medium) provided by the invention;
Fig. 4 is the schematic diagram without the highly reliable floating body memory cell structure of electric capacity (asymmetric gate medium) provided by the invention;
Fig. 5 is the typical process flow figure of new memory cell described in Fig. 3;
Fig. 6 is the another kind of implementation method of step 4～6 in process flow shown in Fig. 5.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Fig. 1 is the conventional schematic diagram without electric capacity floating body memory cell structure, and hole is by the region being stored near hole blocking layer.Here hole blocking layer both can adopt SiO
2realize, also can adopt the Si of n doping to complete, adopt even SiGe, SiC etc. realize.Meanwhile, substrate or back of the body grid can ground connection, also can realize negative pressure biasing.
Fig. 2 is two kinds of programming mode schematic diagrames of conventional floating body memory cell.Under channel hot electron programming mode, (Fig. 2 a), applies a large malleation as 2V to leakage, to grid, applies a transistorized cut-in voltage as 0.5V.Source voltage terminal is 0V, and substrate can apply 0V or negative pressure.With this understanding, electronics is obtaining higher energy from source to leaking motion process, near there is ionization by collision under the high electric field of drain terminal, is producing electron hole pair, and the hole of generation will be moved to substrate.Because the existence of hole blocking layer makes hole form accumulation in the place near barrier layer when moving to substrate.The accumulation in hole will cause substrate potential rising to cause transistorized threshold voltage to reduce, and we claim this state for writing state (" 1 ").Yet, under this programming mode, because high grid leak electrical potential difference, the hole producing part when moving to substrate will move to gate medium, thereby near drain junction, be easy to produce the accumulation that trap causes hole, after multi-pass operation, data reading disturbance easily occur or make mistakes.
Programming mode (Fig. 2 b) for band-to-band-tunneling BTBT, conventionally source is floated, drain terminal voltage is much larger than gate voltage, such as Vg=0V, Vd=4V, under this pattern, electronics will be mobile to leaking by band-to-band-tunneling, the hole producing, when moving to substrate, can enter in grid at drain junction annex because potential difference large between grid leak will have part, causes equally the degeneration of gate medium to cause disturbance of data or read error.The degeneration of gate medium will affect the reliability of device, therefore becomes the significant challenge of its industrialization.For erasure case, can apply negative pressure to source or drain region, the hole of storing near substrate zone will be removed causes transistorized threshold voltage to increase, and we are called wiping state (" 0 ").The combination of this " 0 " one state will complete the erasable operation of high speed of the data of our needs.Erase mode does not provide in the drawings herein.
In Fig. 3, provided solution---the gate medium engineering of degenerating for suppressor medium, by to adopting different gate dielectric materials or grid medium thickness to increase the electrical thickness of the gate medium in this region near source-and-drain junction district, thereby effectively reduce the electric field of vertical direction, so just can in source, leak the degenerate problem of crossover region by control gate medium.By the thin oxide layer at raceway groove middle section or employing hafnium, reduce electrical thickness simultaneously, thereby can improve grid-control ability and suppress short-channel effect.This composition of sample, when the degeneration of suppressor medium, improving the reliability (durability) of memory cell, is also conducive to the scaled of this memory device
Consider that degenerate main Shi drain junction district annex of gate medium occurs, so Fig. 4 has provided another modification that realizes this invention thought, adopted asymmetrical gate medium to reach to control near the object of vertical gate electric field drain junction here.
Fig. 3 and Fig. 4 demonstrate for main thought of the present invention.Known to front, in order to meet high impact ionization rate and low grid injection efficiency, need to apply a large voltage to drain junction, and grid only needs to meet the small voltage that device is opened, there is a large vertical electric field at the overlapping place of grid leak in (CHE or BTBT pattern) in programming situation for this reason.This,, by making traditional floating gate memory cell produce interface trap and oxide traps near knot, causes the degeneration of device stores characteristic.Consider that vertical electric field is determined by drain-to-gate voltage and grid medium thickness, changing voltage or thickness will be possible measure for this reason.Yet low leakage is pressed will reduce impact ionization rate and increase grid hot electron and is injected, and is not a desirable solution.Increase grid medium thickness and will make grid-control ability weaken, be unfavorable for the scaled of device.
For this reason, in Fig. 3, the present invention proposes to adopt different gate dielectric materials or dielectric thickness in order to address the above problem; On the one hand, raceway groove middle section adopts the gate medium of thin gate medium or high-k can effectively improve grid-control ability, and the short channel effect that reduces floating body memory cell is beneficial to the no-load voltage ratio of device; On the other hand, thereby near source-and-drain junction annex, adopt thicker gate medium or low-k gate medium can in the situation that large drain terminal voltage by increasing electrical thickness, reduce the electric field of vertical direction suppress vertically to hole, the grid of electronics inject, improve the reliability of device.
Tu3Zhong， source-and-drain junction district dielectric thickness all changes.Fig. 4 has provided the mutation of this structure, and wherein near source-and-drain junction, gate medium is unsymmetric structure, and its basic thought is still identical.
In the present invention, do not specify substrate type, as SOI, body silicon, SiGe etc., we do not have specify devices type yet, as planar structure, vertical stratification, three-dimensional structure etc., in every case relating to the situation the present invention who adopts control source, near the gate dielectric material of drain junction and dielectric thickness to change vertical electric field and then this thought of raising device reliability will contain, and not give here to introduce one by one.
In this structure, substrate region can comprise body silicon substrate, SOI substrate, GOI substrate, stress silicon substrate etc.Hole blocking layer wherein can adopt SiO
2, SiC, the insulating barriers such as SiN, can adopt N-shaped doped silicon, can adopt hole potential well material, as SiGe, Ge etc.
In this structure, near source leakage and grid crossover region first gate medium partly, can adopt advanced low-k materials, such as SiO
2, Si
3n
4deng, also can adopt the method that forms thicker gate dielectric material by control to realize.And the gate dielectric layer of raceway groove middle section can adopt one deck or the sandwich construction of high dielectric constant material, as HfO
2, HfSiON, AlO, SiO/HfO, SiO/HfSiON, SiO/AlO etc., also can form thinner gate medium by control and realize.Its basic thought is that under identical grid voltage, the electric field on gate dielectric layer 1 is by the electric field being less than on raceway groove centre gate dielectric layer 2.
In this structure, gate material can adopt traditional polygate electrodes, also can adopt metal gate electrode, silicide (as CoSi, NiSi etc.), the combination of nitride (as TaN, TiN, WN etc.) or its sandwich construction (as TaN/Poly etc.).
In order better to understand this structure, as example adopts, large horse scholar (Damascene) technique has provided a kind of manufacture method of the present invention to the structure that Fig. 5 be take in Fig. 3, comprising: 1) form hole blocking layer, as SiO
2, N+doped Si, SiC etc. → 2) and forming unit isolated area, as adopted STI technique → 3) deposit gate insulation layer and mask layer, as SiO
2/ Si
3n
4→ 4) etching definition gate region, → 5) etching formation grid source/leakage crossover region, such as selectivity lateral etching part Si
3n
4.→ 6) form gate insulation layer and gate electrode, such as thermal oxidation, form the electrode materials such as thin oxide layer and depositing polysilicon, also can adopt ALD deposit high K dielectric as HfO
2deng formation gate medium.→ 7) remove mask layer and expose source-drain area → 8) leakage doped region → 9, formation source) ILD layer deposit → 10) complete contact hole and metal connecting line.
Fig. 6, for the committed step 4～6 in Fig. 5 technological process, has provided the implementation method that adopts side wall definition grid source, grid leak crossover region.
Be noted that the realization of structure of the present invention, not only can adopt above-mentioned technique, also can adopt other techniques.Such as the technique that forms multistep oxide layer in logical device for the distressed structure in Fig. 4 by convenient feasible, at this, do not repeat one by one.
From the above, in an embodiment of the present invention, by to adopting different gate dielectric materials or grid medium thickness to increase the electrical thickness of this region gate medium near source-and-drain junction district, thereby effectively reduce the electric field of vertical direction, by the thin oxide layer at raceway groove middle section or employing hafnium, thereby improved grid-control ability, suppressed short-channel effect simultaneously.This composition of sample, when the degeneration of suppressor medium, improving the reliability (durability) of memory cell, is also conducive to the scaled of this memory device.Meanwhile, this has been avoided the complicated technology of the capacitance structure in conventional 1T1C structure completely without capacitance structure.The manufacturing process that it adopts and conventional logic process are completely compatible, and the technique that is also conducive to density three-dimensional is integrated.
Thought of the present invention will be not limited only to the float structure device of planar channeling, also can be applied to nonplanar device as FinFET, vertical devices, and three-dimension device is integrated etc.All relate to adopt control source, drain junction near gate dielectric material will contain with situation the present invention that dielectric thickness changes vertical electric field and then this thought of raising device reliability.
Thought of the present invention is also not limited only to have the structure of symmetrical gate dielectric material, and the structure with asymmetric gate dielectric material also will be included for the present invention.Wherein near gate medium drain junction can adopt advanced low-k materials, such as SiO
2, Si
3n
4deng, also can adopt the method that forms thicker gate dielectric material by control to realize.And near source knot the gate dielectric layer of channel region can adopt one deck or the sandwich construction of high dielectric constant material, as HfO
2, HfSiON, AlO, SiO/HfO, SiO/HfSiON, SiO/AlO etc., also can form thinner gate dielectric material (as SiO by control
2deng) method realize.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (11)
1. one kind without capacitor type dynamic random access memory structure, this structure comprises substrate, hole blocking layer, raceway groove, source-drain area, gate medium district and gate electrode from the bottom to top successively, it is characterized in that, this structure is by adopting different gate dielectric materials or grid medium thickness near the source-and-drain junction district in channel region, increase the electrical thickness of the gate medium in this region, thereby effectively reduce the electric field of vertical direction, by adopting thin oxide layer at raceway groove middle section or adopting hafnium, improve grid-control ability and suppress short-channel effect simultaneously.
2. according to claim 1ly without capacitor type dynamic random access memory structure, it is characterized in that, described substrate is body silicon substrate, SOI substrate, GOI substrate or stress silicon substrate; Described hole blocking layer adopts insulating barrier SiO
2, SiC or SiN, or adopt N-shaped doped silicon, or adopt hole potential well material SiGe or Ge.
3. according to claim 1ly without capacitor type dynamic random access memory structure, it is characterized in that, near source, leak with first gate medium of grid crossover region part and adopt advanced low-k materials SiO
2or Si
3n
4, or the method that employing forms thicker gate dielectric material by control realizes; And the gate dielectric layer of raceway groove middle section adopts one deck or the sandwich construction HfO of high dielectric constant material
2, HfSiON, AlO, SiO/HfO, SiO/HfSiON or SiO/AlO, or by control, form thinner gate medium and realize.
4. according to claim 1 without capacitor type dynamic random access memory structure, it is characterized in that, described gate electrode adopts polygate electrodes, metal gate electrode, silicide, nitride or sandwich construction, wherein silicide is CoSi or NiSi, nitride is TaN, TiN or WN, and sandwich construction is TaN/Poly.
5. without a preparation method for capacitor type dynamic random access memory structure, it is characterized in that, method comprises:
Step 1: form hole blocking layer on substrate;
Step 2: adopt STI technique forming unit isolated area on the hole blocking layer forming;
Step 3: deposit gate insulation layer and mask layer;
Step 4: exposure definition gate region, and etching is removed mask layer and the dielectric layer of gate region;
Step 5: the mask layer of non-etch areas is carried out to isotropic control etching, complete the reduction of mask layer, form grid source/leakage crossover region;
Step 6: adopt the film dielectric layer of the method formation channel region of oxidation or deposit, then deposit gate material, finally adopts the method for chemico-mechanical polishing to complete planarization, forms gate insulation layer and gate electrode;
Step 7: adopt etching technics to remove mask layer and expose source-drain area;
Step 8: adopt method implanted dopant P or the As of Implantation, complete the automatic standard of source-drain area, leakage doped region, formation source;
Step 9: deposition insulating layer material, and adopt CMP method to realize the planarization of ILD layer;
Step 10: complete contact hole and metal connecting line.
6. the preparation method without capacitor type dynamic random access memory structure according to claim 5, is characterized in that, the described hole blocking layer that forms on substrate is the high barrier material SiO of deposit on substrate
2, SiC or SiN and form, or substrate is carried out to n+ doping and injects the N-shaped doped silicon forming.
7. the preparation method without capacitor type dynamic random access memory structure according to claim 5, is characterized in that, described on substrate, form hole blocking layer after, further comprise: the doping of carrying out raceway groove injects to adjust the threshold voltage of device.
8. the preparation method without capacitor type dynamic random access memory structure according to claim 5, is characterized in that, described step 2 comprises:
The isolated area that adopts the method forming unit of etching on the hole blocking layer forming, completes insulating material SiO
2filling, then adopt chemico-mechanical polishing to complete planarization.
9. the preparation method without capacitor type dynamic random access memory structure according to claim 5, is characterized in that, the gate insulation layer of deposit described in step 3 is SiO
2, the mask layer of deposit is Si
3n
4.
10. the preparation method without capacitor type dynamic random access memory structure according to claim 5, is characterized in that, described step 10 comprises:
Adopt photoetching process to complete the etching of contact hole, adopt depositing technics to complete the metal filled of contact hole, complete subsequently the deposit of metallic film, finally adopt chemical wet etching technique to complete the definition of metal connecting line.
11. preparation methods without capacitor type dynamic random access memory structure according to claim 5, is characterized in that, the definition of described grid source, grid leak crossover region adopts the method that laterally reduces mask layer to realize, or adopts side wall definition method to realize.
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| CN201010251514.6A CN102376715B (en) | 2010-08-11 | 2010-08-11 | Capacitor-free dynamic random access memory structure and preparation method thereof |
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| CN201010251514.6A CN102376715B (en) | 2010-08-11 | 2010-08-11 | Capacitor-free dynamic random access memory structure and preparation method thereof |
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| CN102376715B true CN102376715B (en) | 2014-03-12 |
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| US9263522B2 (en) * | 2013-12-09 | 2016-02-16 | Qualcomm Incorporated | Transistor with a diffusion barrier |
| CN105655254B (en) * | 2014-11-13 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN104966735A (en) | 2015-05-26 | 2015-10-07 | 株洲南车时代电气股份有限公司 | Silicon carbide MOSFET device and preparation method thereof |
| CN106019762B (en) | 2016-07-27 | 2019-05-07 | 深圳市华星光电技术有限公司 | A kind of naked eye 3D lenticular display devices and preparation method thereof |
| CN106887432B (en) * | 2017-03-10 | 2019-08-30 | 上海华力微电子有限公司 | A method of it improving SONOS device and reads electric current |
| US9853028B1 (en) * | 2017-04-17 | 2017-12-26 | International Business Machines Corporation | Vertical FET with reduced parasitic capacitance |
| CN110416301A (en) * | 2018-04-28 | 2019-11-05 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused transistor and forming method thereof |
| CN111627816B (en) * | 2019-02-28 | 2023-07-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US11031402B1 (en) * | 2019-12-05 | 2021-06-08 | International Business Machines Corporation | Capacitorless dram cell |
| CN117915653A (en) * | 2022-10-10 | 2024-04-19 | 长鑫存储技术有限公司 | Memory cell structure, preparation method thereof, read-write circuit and memory |
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