CN101581860B - Thin film transistor liquid crystal display pixel structure and thin film transistor liquid crystal display array base plate - Google Patents
Thin film transistor liquid crystal display pixel structure and thin film transistor liquid crystal display array base plate Download PDFInfo
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- CN101581860B CN101581860B CN2008101063407A CN200810106340A CN101581860B CN 101581860 B CN101581860 B CN 101581860B CN 2008101063407 A CN2008101063407 A CN 2008101063407A CN 200810106340 A CN200810106340 A CN 200810106340A CN 101581860 B CN101581860 B CN 101581860B
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Abstract
The invention provides a thin film transistor liquid crystal display pixel structure which comprises a data wire, a grid scanning wire and a pixel area, wherein the data wire and the grid scanning wire are overlapped to form an overlapped area. The thin film transistor liquid crystal display pixel structure is characterized by also comprising an electrostatic elimination area, and the electrostatic elimination area sequentially comprises a grid scanning wire metal layer, an insulating layer and a data wire metal layer, wherein the grid scanning wire metal layer is connected with the grid scanning wire; the insulating layer is used for insulating the grid scanning wire metal layer and the data wire metal layer; and the data wire metal layer is connected with the data wire. The invention also provides a thin film transistor liquid crystal display array base plate. The pixel structure and the array base plate can protect the overlapped area between the grid scanning wire and the data wireand reduce the puncture probability of the overlapped area.
Description
Technical field
The present invention relates to thin film transistor (TFT) (TFT) LCD (LCD) array base palte, relate in particular to pixel structure for thin film transistor liquid crystal display and array base palte.
Background technology
At present, the world has entered the information revolution epoch, and display technique and display device have occupied crucial status in the evolution of infotech.And, become the direction of display technique development because flat pannel display has little, radiationless, the advantage such as do not glimmer of in light weight, thin thickness, volume.
In flat panel display, TFT LCD has characteristics such as low in energy consumption, radiationless, therefore, has occupied leading position in flat panel display market.
Fig. 1 is traditional TFT LCD array substrate pixel structure synoptic diagram, and as shown in Figure 1, there are overlapping region 7 in data line 2 and controlling grid scan line 1.As everyone knows, the short-circuited conducting sleeve (not shown) in the pixel region periphery links to each other with data line 2 with illustrated controlling grid scan line 1 respectively, to prevent the charge unbalance in controlling grid scan line 1 and the data line 2, punctures.But; this short-circuited conducting sleeve (not shown) is to form in the last process of TFT LCD array base palte; in technology before, can not shield to controlling grid scan line 1 and data line 2; therefore; buildup of static electricity on data lines that process procedure caused 2 such as the substrate transferring of preceding technology, cleaning and controlling grid scan line 1; can't obtain discharging balance; in the production of reality; the phenomenon of puncture takes place in the normal overlapping region 7 that controlling grid scan line 1 and data line 2 take place, even punctures in the channel part (not shown).
In case overlapping region 7 punctures, common method for maintaining is earlier with laser (Laser) segment data line 2 that breaks, and the back is by chemical vapor deposition (CVD) reparation bridge joint, so that array base palte can normally use the maintenance process more complicated.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of pixel structure for thin film transistor liquid crystal display and array base palte, can protect the overlapping region of controlling grid scan line and data line, reduces the probability that puncture takes place described overlapping region.
For achieving the above object, technical scheme of the present invention is achieved in that
The invention provides a kind of pixel structure for thin film transistor liquid crystal display, comprise data line, controlling grid scan line and pixel region, data line and controlling grid scan line overlap and form overlapping region, this dot structure comprises that also static eliminates the zone, this static eliminate the zone successively by the controlling grid scan line metal level that is connected with controlling grid scan line, be used to make described controlling grid scan line metal level and the discrete isolation layer of data line metal level and the data line metal level that is connected with data line constitutes.
Wherein, described static is eliminated the distance between the controlling grid scan line metal level and data line metal level in the zone, is not more than the distance between the data line and controlling grid scan line in the overlapping region.
Described isolation layer is: the gate insulator between controlling grid scan line metal level and data line metal level; Perhaps,
Described isolation layer is: the composite bed that is combined at the gate insulator on the described controlling grid scan line metal level and the active layer between gate insulator and data line metal level.
Described static is eliminated the zone and is positioned near the overlapping region of data line and controlling grid scan line.
Comprise at least one described static elimination zone in the dot structure.
The present invention provides a kind of thin-film transistor LCD device array substrate simultaneously, comprise controlling grid scan line, data line and pixel region, data line and controlling grid scan line overlap and form overlapping region, this array base palte comprises that also static eliminates the zone, described static eliminate the zone by the controlling grid scan line metal level that is connected with controlling grid scan line, be used to make described controlling grid scan line metal level and the discrete isolation layer of data line metal level and the data line metal level that is connected with data line constitutes.
Wherein, comprise at least one described static elimination zone near the overlapping region of each controlling grid scan line and data line.
Every data line connects at least one described static to be eliminated zone and every controlling grid scan line and connects at least one described static and eliminate the zone.
Described static is eliminated the distance between the controlling grid scan line metal level and data line metal level in the zone, is not more than the distance between the data line and controlling grid scan line in the described overlapping region.
Dot structure provided by the present invention and array base palte, near data line and controlling grid scan line overlapping region, increase static and eliminate the zone, the structure in this static elimination zone can be identical with the structure of described overlapping region, also can be different, the controlling grid scan line metal level that static is eliminated in the zone is not connected mutually with the data line metal level, wherein, when the distance between data line and the controlling grid scan line is identical in distance between controlling grid scan line metal level and the data line metal level and the overlapping region, in when, buildup of static electricity taking place causing charge unbalance on controlling grid scan line and the data line, eliminate the zone by described static, can reduce the probability that puncture takes place described overlapping region; Perhaps, when the distance between controlling grid scan line metal level and the data line metal level than overlapping region in distance hour between data line and the controlling grid scan line, static is eliminated easier puncture of the more described overlapping region in zone, at this moment, in when, buildup of static electricity taking place causing charge unbalance on controlling grid scan line and the data line, at first eliminate the zone and puncture, better reduced the probability that puncture takes place described overlapping region by the static that increases.
And, in case eliminating the zone, described static punctures, because that static is eliminated is regional in dot structure and cut little ice, only need in the subsequent detection maintenance process, use Laser, disconnect this static elimination zone and get final product with being connected of data line and controlling grid scan line, easy to maintenance.
Description of drawings
Fig. 1 is traditional TFT LCD array substrate pixel structure synoptic diagram in the prior art;
Fig. 2 is a TFT LCD array substrate pixel structure synoptic diagram of the present invention;
Fig. 3 is the A-A schematic cross-section;
Fig. 4 is the B-B schematic cross-section;
Fig. 5 is the manufacture method schematic flow sheet of TFT LCD array substrate pixel structure shown in Figure 2.
Reference numeral: 1, controlling grid scan line; 2, data line; 3, active layer; 4, static is eliminated the zone; 5, gate insulator; 6, passivation layer; 7, overlapping region.
Embodiment
Basic thought of the present invention is: near data line and controlling grid scan line overlapping region, increase a static and eliminate the zone, the controlling grid scan line metal level is not connected by isolation layer mutually with the data line metal level in this static elimination zone.
Below, be described with reference to the accompanying drawings the realization of TFT LCD dot structure of the present invention and array base palte by specific embodiment.
Fig. 2 is a TFT LCD array substrate pixel structure synoptic diagram of the present invention, as shown in Figure 2, adjacent two data lines 2 and two adjacent controlling grid scan lines 1 overlap mutually, define a pixel region, each dot structure includes data line 2, controlling grid scan line 1 and described pixel region, comprise which kind of structure belongs to known technology, repeats no more here in the concrete pixel region.In the present invention, near the overlapping region 7 of data line 2 and controlling grid scan line 1, increase another one static and eliminate zone 4.The A-A sectional view in static elimination zone 4 is made of controlling grid scan line metal level (linking to each other with controlling grid scan line 1), gate insulator 5 and data line metal level (linking to each other with data line 2) as shown in Figure 3.Contrast as shown in Figure 4 prior art and dot structure provided by the present invention in the B-B sectional view of overlapping region 7 of data line 2 and controlling grid scan line 1, overlapping region 7 is formed with active layer 3 and gate insulator 5 between data line 2 and controlling grid scan line 1, and static is eliminated zone 4 between controlling grid scan line metal level and data line metal level, has only gate insulator 5 (thickness is generally 2000～8000 dusts), and there is not active layer 3 (thickness is generally 500～5000 dusts), distance between controlling grid scan line metal level and the data line metal level is shorter, therefore, compare with the overlapping region 7 of data line 2 and controlling grid scan line 1, it is the zone that easier generation punctures that the static of increase is eliminated zone 4.Therefore, when buildup of static electricity takes place, when causing controlling grid scan line 1 and data line 2 charge unbalances, at first be to eliminate zone 4 according to the static that the present invention program provides to puncture.In case static is eliminated after zone 4 punctures, and in the subsequent detection maintenance process, uses Laser, disconnect this static and eliminate regional 4 and get final product controlling grid scan line 1 and being connected of data line 2, easy to maintenance.
Wherein, the structure in static elimination zone 4 shown in Figure 2 also can be identical with the structure of overlapping region 7, that is: comprise gate insulator 5 and active layer 3 between controlling grid scan line metal level and the data line metal level, at this moment, be not more than the distance between the controlling grid scan line 1 and data line 2 in the overlapping region 7 as long as guarantee distance between controlling grid scan line metal level and the data line metal level, can finish goal of the invention of the present invention equally.But, when the distance between controlling grid scan line metal level and the data line metal level less than overlapping region 7 between controlling grid scan line 1 and the data line 2 apart from the time, static of the present invention is eliminated zone 4 will can obtain better invention effect than overlapping region 7 easier punctures.
Same, in the prior art, in the overlapping region 7 of data line 2 and controlling grid scan line 1, also can not comprise active layer 3 between controlling grid scan line 1 and the data line 2, this moment overlapping region 7 structure and static shown in Figure 3 to eliminate regional 4 structure identical, at this moment, static among the present invention is eliminated zone 4 still can use structure shown in Figure 3, eliminate the thickness that the thickness of the gate insulator in the zone 4 is not more than gate insulator in the overlapping region as long as guarantee static, and, the thickness that static is eliminated the gate insulator in the zone 4 can be obtained better invention effect during less than the thickness of gate insulator in the overlapping region.
In addition, preferably all increase described static and eliminate zone 4 near each overlapping region 7, to protect each overlapping region 7, the static of increase is eliminated the number in zone 4 and is not limit, but in order to guarantee pixel aperture ratio, is preferably 1.Perhaps; when dot structure shown in Figure 2 is applied to array base palte; be not that certain each dot structure includes at least 1 static elimination zone 4; also can connect at least one static elimination zone 4 and at least one static elimination zone 4 of each data line 2 connection by each controlling grid scan line 1; like this, also can finish the purpose of protection overlapping region 7 preferably.And, though eliminating zone 4, described static in Fig. 2, provided concrete shape.But, in actual applications, have more than and be limited to the shape shown in Fig. 2, as long as the controlling grid scan line metal level that static is eliminated zone 4 links to each other with corresponding controlling grid scan line 1, the data line metal level links to each other with corresponding data line 2 and gets final product.
Eliminate on the data line metal level in zone 4 and also be coated with passivation layer 6 on the data line of the prior art 2 at the static that the present invention program provided as can be known from Fig. 3 and Fig. 4.
Below, will describe the concrete manufacture method of TFT LCD array substrate pixel structure of the present invention shown in Figure 2 in detail in conjunction with Fig. 2 and Fig. 3, as shown in Figure 5, this method comprises:
Step 501: depositing metal films on glass substrate, the gate electrode (not shown among Fig. 2), common electrode signal line (not shown among Fig. 2) and the static that form controlling grid scan line 1, TFT by composition technologies such as photoetching process and etch processs are eliminated the controlling grid scan line metal level in zone 4, the controlling grid scan line metal level that static is eliminated zone 4 is connected with the controlling grid scan line that static is eliminated regional 4 correspondences, as shown in Figure 2.
Wherein, specifically how depositing metal films, how to carry out photoetching and etching is very known in the prior art, repeat no more here.
Wherein, the metallic film in this step specifically by which kind of material deposition is formed also belongs to known technology, repeats no more here.
Step 502: deposition gate insulator 5 on the substrate of completing steps 501.
Step 503: successive sedimentation amorphous silicon membrane and n+ amorphous silicon membrane on the substrate of completing steps 502, by composition technologies such as photoetching process and etch process above the TFT gate electrode, the overlapping region 7 of data line 2 and controlling grid scan line 1, form amorphous silicon layer and n+ amorphous silicon layer, promptly active layer 3.Wherein, etch away amorphous silicon membrane and n+ amorphous silicon membrane on the static elimination zone 4, to guarantee the controlling grid scan line metal level and the data line metal level distance in static elimination zone 4,, be easier to puncture less than the distance of controlling grid scan line in the overlapping region 71 with data line 2.
Wherein, specifically how deposition of amorphous silicon films and n+ amorphous silicon membrane are very known in the prior art, repeat no more here.
Step 504: depositing metal films on the substrate of completing steps 503, form the source electrode of data line 2, TFT and the data line metal level in drain electrode (not shown among Fig. 2) and static elimination zone 4 by composition technologies such as photoetching process and etch processs, the data line metal level in static elimination zone 4 is eliminated regional 4 corresponding data line 2 with static and is connected, as shown in Figure 2.
Wherein, it is very known in the prior art that the metallic film in this step specifically by which kind of material deposition is formed, and repeats no more here.
Step 505: deposit passivation layer 6 on the substrate of completing steps 504, form passivation layer via hole by composition technologies such as photoetching process and etch processs, in order to connect the drain electrode of pixel electrode and TFT.
Wherein, specifically use which kind of material and how deposit passivation layer is very known in the prior art, repeat no more here.
Step 506: pixel deposition electrode layer on the substrate of completing steps 505 forms pixel electrode by composition technologies such as photoetching process and etch processs.
Wherein, specifically use which kind of material and how to deposit described pixel electrode layer very known in the prior art, repeat no more here.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (7)
1. pixel structure for thin film transistor liquid crystal display, comprise data line, controlling grid scan line, and pixel region, data line and controlling grid scan line overlap and form overlapping region, it is characterized in that, this dot structure also comprises static elimination zone, this static is eliminated the zone successively by the controlling grid scan line metal level that is connected with controlling grid scan line, be used to make described controlling grid scan line metal level and the discrete isolation layer of data line metal level, and the data line metal level that is connected with data line constitutes, described static is eliminated the distance between the controlling grid scan line metal level and data line metal level in the zone, is not more than the distance between the data line and controlling grid scan line in the overlapping region.
2. dot structure according to claim 1 is characterized in that, described isolation layer is: the gate insulator between controlling grid scan line metal level and data line metal level; Perhaps,
Described isolation layer is: the composite bed that is combined at the gate insulator on the described controlling grid scan line metal level and the active layer between gate insulator and data line metal level.
3. dot structure according to claim 1 and 2 is characterized in that, described static is eliminated the zone and is positioned near the overlapping region of data line and controlling grid scan line.
4. dot structure according to claim 1 and 2 is characterized in that, comprises at least one described static elimination zone in the dot structure.
5. thin-film transistor LCD device array substrate, comprise controlling grid scan line, data line, and pixel region, data line and controlling grid scan line overlap and form overlapping region, it is characterized in that, this array base palte also comprises static elimination zone, described static is eliminated the zone by the controlling grid scan line metal level that is connected with controlling grid scan line, be used to make described controlling grid scan line metal level and the discrete isolation layer of data line metal level, and the data line metal level that is connected with data line constitutes, described static is eliminated the distance between the controlling grid scan line metal level and data line metal level in the zone, is not more than the distance between the data line and controlling grid scan line in the overlapping region.
6. array base palte according to claim 5 is characterized in that, comprises at least one described static elimination zone near the overlapping region of each controlling grid scan line and data line.
7. array base palte according to claim 6 is characterized in that, every data line connects at least one described static to be eliminated zone and every controlling grid scan line and connect at least one described static and eliminate the zone.
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| CN103941440B (en) * | 2013-12-30 | 2017-02-15 | 上海中航光电子有限公司 | Array substrate, display panel and displayer |
| CN105549288B (en) * | 2016-03-04 | 2021-03-02 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN111323984B (en) * | 2020-03-25 | 2023-04-11 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN111367130A (en) * | 2020-04-27 | 2020-07-03 | Tcl华星光电技术有限公司 | Array substrate, display panel and display device |
| CN111710684A (en) * | 2020-06-10 | 2020-09-25 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1194039A (en) * | 1995-08-07 | 1998-09-23 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
| CN101025489A (en) * | 2006-02-17 | 2007-08-29 | 三星电子株式会社 | Array substrate, display device having the same, and method thereof |
| CN201007770Y (en) * | 2006-09-29 | 2008-01-16 | 上海广电光电子有限公司 | Thin-film transistor array substrates for LCD |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1194039A (en) * | 1995-08-07 | 1998-09-23 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
| CN101025489A (en) * | 2006-02-17 | 2007-08-29 | 三星电子株式会社 | Array substrate, display device having the same, and method thereof |
| CN201007770Y (en) * | 2006-09-29 | 2008-01-16 | 上海广电光电子有限公司 | Thin-film transistor array substrates for LCD |
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