CN101581860A - Thin film transistor liquid crystal display pixel structure and thin film transistor liquid crystal display array base plate - Google Patents
Thin film transistor liquid crystal display pixel structure and thin film transistor liquid crystal display array base plate Download PDFInfo
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- CN101581860A CN101581860A CNA2008101063407A CN200810106340A CN101581860A CN 101581860 A CN101581860 A CN 101581860A CN A2008101063407 A CNA2008101063407 A CN A2008101063407A CN 200810106340 A CN200810106340 A CN 200810106340A CN 101581860 A CN101581860 A CN 101581860A
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- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 56
- 230000008030 elimination Effects 0.000 claims abstract description 54
- 238000003379 elimination reaction Methods 0.000 claims abstract description 54
- 230000003068 static effect Effects 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 25
- 230000005611 electricity Effects 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000012423 maintenance Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
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Abstract
The invention provides a thin film transistor liquid crystal display pixel structure which comprises a data wire, a grid scanning wire and a pixel area, wherein the data wire and the grid scanning wire are overlapped to form an overlapped area. The thin film transistor liquid crystal display pixel structure is characterized by also comprising an electrostatic elimination area, and the electrostatic elimination area sequentially comprises a grid scanning wire metal layer, an insulating layer and a data wire metal layer, wherein the grid scanning wire metal layer is connected with the grid scanning wire; the insulating layer is used for insulating the grid scanning wire metal layer and the data wire metal layer; and the data wire metal layer is connected with the data wire. The invention also provides a thin film transistor liquid crystal display array base plate. The pixel structure and the array base plate can protect the overlapped area between the grid scanning wire and the data wire and reduce the puncture probability of the overlapped area.
Description
Technical Field
The present invention relates to a Thin Film Transistor (TFT) Liquid Crystal Display (LCD) array substrate, and more particularly, to a TFT liquid crystal display pixel structure and an array substrate.
Background
At present, the world has entered the information revolution era, and display technologies and display devices have occupied a very important position in the development process of the information technologies. Since the flat panel display has the advantages of light weight, thin thickness, small volume, no radiation, no flicker, etc., it has become the development direction of the display technology.
In the flat panel display technology, the TFT LCD has features of low power consumption, no radiation, etc., and thus, has a dominant position in the flat panel display market.
Fig. 1 is a schematic view of a pixel structure of a conventional TFT LCD array substrate, and as shown in fig. 1, an overlap region 7 exists between a data line 2 and a gate scan line 1. As is well known, a shorting ring (not shown) at the periphery of the pixel region is connected to the gate scan lines 1 and the data lines 2, respectively, to prevent charge imbalance and breakdown in the gate scan lines 1 and the data lines 2. However, the short ring (not shown) is formed in the final process of the TFT LCD array substrate, and cannot protect the gate scan line 1 and the data line 2 in the previous process, so that static electricity accumulated on the data line 2 and the gate scan line 1 due to the processes of substrate transportation, cleaning, and the like in the previous process cannot be discharged in balance, and in the actual production, the overlapping region 7 between the gate scan line 1 and the data line 2 is often broken, and even the channel portion (not shown) is broken.
Once the overlapped area 7 is broken down, the conventional repair method is to first use a Laser (Laser) to break off a part of the data line 2, and then repair the bridge by Chemical Vapor Deposition (CVD) to make the array substrate usable normally, and the repair process is complicated.
Disclosure of Invention
In view of the above, the present invention provides a pixel structure of a tft-lcd and an array substrate thereof, which can protect the overlapping area of a gate scan line and a data line and reduce the probability of breakdown in the overlapping area.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the invention provides a pixel structure of a thin film transistor liquid crystal display, which comprises a data line, a grid scanning line and a pixel area, wherein the data line and the grid scanning line are overlapped to form an overlapped area.
And the distance between the grid scanning line metal layer and the data line metal layer in the static elimination region is not more than the distance between the data line and the grid scanning line in the overlapping region.
The isolation layer is: the grid insulation layer is positioned between the grid scanning line metal layer and the data line metal layer; or,
the isolation layer is: the composite layer is composed of a grid insulation layer positioned on the grid scanning line metal layer and an active layer positioned between the grid insulation layer and the data line metal layer.
The static elimination area is positioned near the overlapping area of the data line and the grid scanning line.
The pixel structure comprises at least one static elimination area.
The invention also provides a thin film transistor liquid crystal display array substrate which comprises grid scanning lines, data lines and a pixel area, wherein the data lines and the grid scanning lines are overlapped to form an overlapped area.
And the vicinity of an overlapping region of each gate scanning line and each data line comprises at least one static elimination region.
Each data line is connected with at least one static elimination region, and each grid scanning line is connected with at least one static elimination region.
And the distance between the grid scanning line metal layer and the data line metal layer in the static electricity elimination region is not more than the distance between the data line and the grid scanning line in the overlapping region.
According to the pixel structure and the array substrate provided by the invention, the static elimination area is added near the overlapping area of the data line and the grid scanning line, the structure of the static elimination area can be the same as or different from that of the overlapping area, and the grid scanning line metal layer and the data line metal layer in the static elimination area are not connected with each other, wherein when the distance between the grid scanning line metal layer and the data line metal layer is the same as that between the data line and the grid scanning line in the overlapping area, when the charges on the grid scanning line and the data line are unbalanced due to static accumulation, the probability of breakdown of the overlapping area can be reduced through the static elimination area; or, when the distance between the gate scan line metal layer and the data line metal layer is smaller than the distance between the data line and the gate scan line in the overlap region, the electrostatic elimination region is more prone to breakdown than the overlap region, and at this time, when charge imbalance on the gate scan line and the data line due to electrostatic accumulation occurs, breakdown occurs in the increased electrostatic elimination region first, so that the probability of breakdown in the overlap region is better reduced.
Moreover, once the static elimination area is broken down, as the static elimination area does not play any role in the pixel structure, only the Laser is used to disconnect the connection of the static elimination area with the data line and the grid scanning line in the subsequent detection and maintenance process, and the maintenance is simple.
Drawings
FIG. 1 is a schematic diagram of a conventional TFT LCD array substrate pixel structure in the prior art;
FIG. 2 is a schematic diagram of a pixel structure of a TFT LCD array substrate according to the present invention;
FIG. 3 is a schematic sectional view taken along line A-A;
FIG. 4 is a schematic cross-sectional view B-B;
fig. 5 is a flow chart illustrating a manufacturing method of the pixel structure of the TFT LCD array substrate shown in fig. 2.
Reference numerals: 1. a gate scan line; 2. a data line; 3. an active layer; 4. a static electricity eliminating area; 5. a gate insulating layer; 6. a passivation layer; 7. an overlap region.
Detailed Description
The basic idea of the invention is: and a static elimination area is added near the overlapping area of the data line and the grid scanning line, and the grid scanning line metal layer and the data line metal layer in the static elimination area are not connected with each other through an isolation layer.
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
Fig. 2 is a schematic diagram of a pixel structure of a TFT LCD array substrate according to the present invention, and as shown in fig. 2, two adjacent data lines 2 and two adjacent gate scan lines 1 are overlapped with each other to define a pixel region, each pixel structure includes a data line 2, a gate scan line 1 and the pixel region, and a specific structure included in the pixel region belongs to the prior art, which is not described herein again. In the present invention, another static elimination region 4 is added near the overlapping region 7 of the data line 2 and the gate scan line 1. As shown in fig. 3, the sectional view a-a of the static electricity eliminating region 4 is composed of a gate scanning line metal layer (connected to the gate scanning line 1), a gate insulating layer 5, and a data line metal layer (connected to the data line 2). For the B-B cross-sectional view of the overlapping region 7 of the data line 2 and the gate scan line 1 in the pixel structure provided by the present invention and the prior art shown in fig. 4, the overlapping region 7 forms the active layer 3 and the gate insulating layer 5 between the data line 2 and the gate scan line 1, and the static elimination region 4 is between the gate scan line metal layer and the data line metal layer, and only the gate insulating layer 5 (with the thickness of 2000-8000 angstroms) but not the active layer 3 (with the thickness of 500-5000 angstroms generally) is provided, and the distance between the gate scan line metal layer and the data line metal layer is shorter, so that the static elimination region 4 is added as a region where breakdown is more likely to occur compared with the overlapping region 7 of the data line 2 and the gate scan line 1. Therefore, when static electricity is accumulated to cause charge imbalance between the gate scan lines 1 and the data lines 2, firstly, the static electricity elimination regions 4 provided according to the scheme of the present invention are broken down. Once the electrostatic elimination region 4 is broken down, in the subsequent detection and maintenance process, the Laser is used to disconnect the electrostatic elimination region 4 from the grid scanning line 1 and the data line 2, and the maintenance is simple.
Here, the structure of the static elimination region 4 shown in fig. 2 may also be the same as that of the overlap region 7, that is: the gate insulating layer 5 and the active layer 3 are included between the gate scan line metal layer and the data line metal layer, and at this time, the object of the present invention can be accomplished as long as the distance between the gate scan line metal layer and the data line metal layer is not greater than the distance between the gate scan line 1 and the data line 2 in the overlap region 7. However, when the distance between the gate scan line metal layer and the data line metal layer is smaller than the distance between the gate scan line 1 and the data line 2 in the overlap region 7, the static electricity elimination region 4 according to the present invention is more likely to break down than the overlap region 7, and a better invention effect can be obtained.
Similarly, in the prior art, in the overlapping region 7 between the data line 2 and the gate scan line 1, the active layer 3 may not be included between the gate scan line 1 and the data line 2, and at this time, the structure of the overlapping region 7 is the same as that of the static elimination region 4 shown in fig. 3, and at this time, the structure shown in fig. 3 may still be used for the static elimination region 4 in the present invention, as long as it is ensured that the thickness of the gate insulating layer in the static elimination region 4 is not greater than that of the gate insulating layer in the overlapping region, and when the thickness of the gate insulating layer in the static elimination region 4 is smaller than that of the gate insulating layer in the overlapping region, a better inventive effect can be obtained.
In addition, the static elimination region 4 is preferably added near each overlapping region 7 to protect each overlapping region 7, and the number of the added static elimination regions 4 is not limited, but is preferably 1 in order to ensure the pixel aperture ratio. Or, when the pixel structure shown in fig. 2 is applied to an array substrate, each pixel structure does not necessarily include at least 1 static elimination region 4, and each gate scan line 1 may be connected to at least one static elimination region 4, and each data line 2 may be connected to at least one static elimination region 4, so that the purpose of protecting the overlapping region 7 may be well achieved. Also, the static electricity elimination region 4 is shown in a specific shape in fig. 2. However, in practical applications, the shape is not limited to that shown in fig. 2, as long as the gate scan line metal layer of the static elimination region 4 is connected to the corresponding gate scan line 1, and the data line metal layer is connected to the corresponding data line 2.
As can be seen from fig. 3 and 4, the passivation layer 6 is covered on the data line metal layer of the static electricity elimination region 4 provided in the solution of the present invention and on the data line 2 in the prior art.
Hereinafter, a specific method for manufacturing the pixel structure of the TFT LCD array substrate of the present invention shown in fig. 2 will be described in detail with reference to fig. 2 and 3, as shown in fig. 5, the method includes:
step 501: a metal thin film is deposited on a glass substrate, and a gate scan line 1, a gate electrode (not shown in fig. 2) of the TFT, a common electrode signal line (not shown in fig. 2), and a gate scan line metal layer of an electrostatic elimination region 4 are formed through a patterning process such as a photolithography process and an etching process, and the gate scan line metal layer of the electrostatic elimination region 4 is connected to a gate scan line corresponding to the electrostatic elimination region 4, as shown in fig. 2.
The details of how to deposit a metal film, how to perform photolithography and etching are well known in the art and will not be described herein.
The specific material of the metal film in this step is deposited, which is also a known technology, and is not described herein again.
Step 502: a gate insulating layer 5 is deposited on the substrate completing step 501.
Step 503: an amorphous silicon thin film and an n + amorphous silicon thin film are continuously deposited on the substrate after step 502 is completed, and an amorphous silicon layer and an n + amorphous silicon layer, namely, an active layer 3 are formed on the overlap region 7 of the data line 2 and the gate scanning line 1 above the gate electrode of the TFT through patterning processes such as a photolithography process and an etching process. The amorphous silicon film and the n + amorphous silicon film on the static elimination area 4 are etched away, so that the distance between the grid scanning line metal layer and the data line metal layer of the static elimination area 4 is ensured to be smaller than the distance between the grid scanning line 1 and the data line 2 in the overlapping area 7, and breakdown is easier.
Particularly, how to deposit the amorphous silicon thin film and the n + amorphous silicon thin film is well known in the prior art, and is not described herein again.
Step 504: a metal thin film is deposited on the substrate after step 503, and a data line 2, a source electrode and a drain electrode (not shown in fig. 2) of the TFT, and a data line metal layer of the static electricity elimination region 4 are formed through a patterning process such as a photolithography process and an etching process, and the data line metal layer of the static electricity elimination region 4 is connected to the data line 2 corresponding to the static electricity elimination region 4, as shown in fig. 2.
The specific material of which the metal film in this step is deposited is well known in the prior art, and is not described herein again.
Step 505: and depositing a passivation layer 6 on the substrate after the step 504, and forming a passivation layer via hole through a patterning process such as a photolithography process and an etching process to connect the pixel electrode and the drain electrode of the TFT.
The specific materials used and how to deposit the passivation layer are well known in the art and will not be described in detail here.
Step 506: a pixel electrode layer is deposited on the substrate after step 505, and a pixel electrode is formed through a patterning process such as a photolithography process and an etching process.
The specific materials used and how to deposit the pixel electrode layer are well known in the art, and are not described herein.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (9)
1. The pixel structure of the thin film transistor liquid crystal display comprises a data line, a grid scanning line and a pixel area, wherein the data line and the grid scanning line are overlapped to form an overlapped area.
2. The pixel structure according to claim 1, wherein a distance between the gate scan line metal layer and the data line metal layer in the static elimination region is not greater than a distance between the data line and the gate scan line in the overlap region.
3. The pixel structure of claim 2, wherein the insulating layer is: the grid insulation layer is positioned between the grid scanning line metal layer and the data line metal layer; or,
the isolation layer is: the composite layer is composed of a grid insulation layer positioned on the grid scanning line metal layer and an active layer positioned between the grid insulation layer and the data line metal layer.
4. The pixel structure according to any one of claims 1 to 3, wherein the static elimination region is located near an overlapping region of the data line and the gate scan line.
5. A pixel structure according to any one of claims 1 to 3, wherein at least one of said static charge eliminating regions is included in the pixel structure.
6. The array substrate of the thin film transistor liquid crystal display comprises grid scanning lines, data lines and a pixel area, wherein the data lines and the grid scanning lines are overlapped to form an overlapped area.
7. The array substrate of claim 6, wherein the vicinity of the overlapping region of each gate scan line and data line comprises at least one static elimination region.
8. The array substrate of claim 7, wherein each data line is connected to at least one of the static elimination regions, and each gate scan line is connected to at least one of the static elimination regions.
9. The array substrate of any one of claims 5 to 7, wherein the distance between the gate scan line metal layer and the data line metal layer in the static elimination region is not greater than the distance between the data line and the gate scan line in the overlap region.
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| CN2008101063407A CN101581860B (en) | 2008-05-12 | 2008-05-12 | Thin film transistor liquid crystal display pixel structure and thin film transistor liquid crystal display array base plate |
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| CN2008101063407A CN101581860B (en) | 2008-05-12 | 2008-05-12 | Thin film transistor liquid crystal display pixel structure and thin film transistor liquid crystal display array base plate |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103941440A (en) * | 2013-12-30 | 2014-07-23 | 上海中航光电子有限公司 | Array substrate, display panel and displayer |
| CN105549288A (en) * | 2016-03-04 | 2016-05-04 | 京东方科技集团股份有限公司 | Array substrate, preparing method of array substrate and display device |
| CN111323984A (en) * | 2020-03-25 | 2020-06-23 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN111367130A (en) * | 2020-04-27 | 2020-07-03 | Tcl华星光电技术有限公司 | Array substrate, display panel and display device |
| CN111710684A (en) * | 2020-06-10 | 2020-09-25 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1103061C (en) * | 1995-08-07 | 2003-03-12 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
| KR101229881B1 (en) * | 2006-02-17 | 2013-02-05 | 삼성디스플레이 주식회사 | Array substrate and display device having the same |
| CN201007770Y (en) * | 2006-09-29 | 2008-01-16 | 上海广电光电子有限公司 | Thin-film transistor array substrates for LCD |
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2008
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103941440A (en) * | 2013-12-30 | 2014-07-23 | 上海中航光电子有限公司 | Array substrate, display panel and displayer |
| CN103941440B (en) * | 2013-12-30 | 2017-02-15 | 上海中航光电子有限公司 | Array substrate, display panel and displayer |
| CN105549288A (en) * | 2016-03-04 | 2016-05-04 | 京东方科技集团股份有限公司 | Array substrate, preparing method of array substrate and display device |
| CN105549288B (en) * | 2016-03-04 | 2021-03-02 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN111323984A (en) * | 2020-03-25 | 2020-06-23 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN111367130A (en) * | 2020-04-27 | 2020-07-03 | Tcl华星光电技术有限公司 | Array substrate, display panel and display device |
| CN111710684A (en) * | 2020-06-10 | 2020-09-25 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| WO2021248605A1 (en) * | 2020-06-10 | 2021-12-16 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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| CN101581860B (en) | 2011-03-16 |
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