CN101581860A - Thin film transistor liquid crystal display pixel structure and thin film transistor liquid crystal display array base plate - Google Patents

Abstract

The present invention provides a pixel structure of a thin film transistor liquid crystal display, including data lines, gate scanning lines, and pixel areas, where the data lines overlap the gate scanning lines to form an overlapping area, and the pixel structure also includes electrostatic The elimination area, the static elimination area is sequentially composed of the gate scanning line metal layer connected to the gate scanning line, the isolation layer used to make the gate scanning line metal layer and the data line metal layer are not connected to each other, and the data line The connected data line metal layer is formed. The present invention also provides an array substrate of a thin film transistor liquid crystal display, the pixel structure and the array substrate can protect the overlapping area of the gate scanning line and the data line, and reduce the probability of breakdown in the overlapping area.

Description

Thin film transistor liquid crystal display pixel structure and array substrate

technical field

The invention relates to a thin film transistor (TFT) liquid crystal display (LCD) array substrate, in particular to a thin film transistor liquid crystal display pixel structure and an array substrate.

Background technique

At present, the world has entered the era of information revolution, and display technology and display devices occupy a very important position in the development of information technology. Since the flat panel display has the advantages of light weight, thin thickness, small size, no radiation, no flicker, etc., it has become the development direction of display technology.

In flat panel display technology, TFT LCD has the characteristics of low power consumption and no radiation, so it occupies a dominant position in the flat panel display market.

FIG. 1 is a schematic diagram of a pixel structure of a traditional TFT LCD array substrate. As shown in FIG. 1 , there is an overlapping area 7 between the data line 2 and the gate scanning line 1 . As we all know, the short-circuit ring (not shown in the figure) on the periphery of the pixel area is respectively connected to the gate scanning line 1 and the data line 2 shown in the figure, so as to prevent the charge imbalance in the gate scanning line 1 and the data line 2, Breakdown occurs. However, the short circuit ring (not shown) is formed in the final process of the TFT LCD array substrate, and cannot protect the gate scanning line 1 and the data line 2 in the previous process. Therefore, the previous process The accumulation of static electricity on the data line 2 and the gate scanning line 1 caused by the substrate handling, cleaning and other process links will not be able to be released and balanced. In actual production, the grid scanning line 1 and the data line 2 often occur Breakdown occurs in the overlapping region 7, even in the channel portion (not shown in the figure).

Once a breakdown occurs in the overlapping area 7, the usual maintenance method is to use a laser (Laser) to cut off part of the data line 2, and then repair the bridge by chemical vapor deposition (CVD), so that the array substrate can be used normally, and the maintenance process is relatively complicated. .

Contents of the invention

In view of this, the main purpose of the present invention is to provide a thin film transistor liquid crystal display pixel structure and an array substrate, which can protect the overlapping area of the gate scanning line and the data line, and reduce the probability of breakdown in the overlapping area.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

The present invention provides a pixel structure of a thin film transistor liquid crystal display, including a data line, a gate scanning line, and a pixel area. The data line overlaps with the gate scanning line to form an overlapping area. The pixel structure also includes a static elimination area. The static elimination area is sequentially composed of the gate scan line metal layer connected to the gate scan line, the isolation layer for making the gate scan line metal layer and the data line metal layer not connected to each other, and the data line connected to the data line metal layers.

Wherein, the distance between the metal layer of the gate scan line and the metal layer of the data line in the static elimination area is not greater than the distance between the data line and the gate scan line in the overlapping area.

The isolation layer is: a gate insulating layer located between the metal layer of the gate scan line and the metal layer of the data line; or,

The insulating layer is a composite layer composed of a gate insulating layer located on the gate scanning line metal layer and an active layer located between the gate insulating layer and the data line metal layer.

The static elimination area is located near the overlapping area of the data line and the gate scanning line.

The pixel structure includes at least one static elimination area.

The present invention also provides an array substrate of a thin film transistor liquid crystal display, including a gate scanning line, a data line, and a pixel area, the data line and the gate scanning line overlap to form an overlapping area, and the array substrate also includes a static elimination area, The static elimination area is composed of a gate scan line metal layer connected to the gate scan line, an isolation layer for making the gate scan line metal layer and the data line metal layer not connected to each other, and a data line connected to the data line. Line metal layer composition.

Wherein, at least one static elimination area is included near the overlapping area of each gate scanning line and data line.

Each data line is connected to at least one static elimination area, and each gate scan line is connected to at least one static elimination area.

The distance between the metal layer of the gate scan line and the metal layer of the data line in the static elimination area is not greater than the distance between the data line and the gate scan line in the overlapping area.

In the pixel structure and array substrate provided by the present invention, a static elimination area is added near the overlapping area of the data line and the gate scanning line. The structure of the static elimination area may be the same as or different from that of the overlapping area. The gate scanning line metal layer and the data line metal layer in the static elimination area are not connected to each other, wherein, when the distance between the gate scanning line metal layer and the data line metal layer is the same as the data line and the gate scanning line in the overlapping area When the distance between them is the same, when the charge imbalance between the gate scanning line and the data line is caused by static electricity accumulation, the probability of breakdown in the overlapping area can be reduced through the static elimination area; or, when the gate The distance between the electrode scan line metal layer and the data line metal layer is smaller than the distance between the data line and the gate scan line in the overlapping area, and the static electricity elimination area is more prone to breakdown than the overlapping area. At this time, When the charge imbalance between the gate scanning line and the data line is caused by the accumulation of static electricity, the increased static elimination area first causes breakdown, which better reduces the probability of breakdown in the overlapping area.

Moreover, once the static elimination area breaks down, since the static elimination area does not play any role in the pixel structure, it is only necessary to use a Laser to disconnect the static elimination area from the data lines and gates in the subsequent inspection and maintenance process. The connection of the pole scanning line is enough, and the maintenance is simple.

Description of drawings

Fig. 1 is a schematic diagram of the pixel structure of a traditional TFT LCD array substrate in the prior art;

Fig. 2 is the schematic diagram of pixel structure of TFT LCD array substrate of the present invention;

Fig. 3 is A-A sectional schematic diagram;

Fig. 4 is B-B section schematic diagram;

5 is a schematic flow chart of a manufacturing method for the pixel structure of the TFT LCD array substrate shown in FIG. 2 .

Reference signs: 1. Gate scanning line; 2. Data line; 3. Active layer; 4. Static elimination area; 5. Gate insulating layer; 6. Passivation layer; 7. Overlapping area.

Detailed ways

The basic idea of the present invention is to add a static elimination area near the overlapping area of the data line and the gate scanning line, and in the static elimination area, the metal layer of the gate scanning line and the metal layer of the data line are not connected to each other through the isolation layer.

Hereinafter, the implementation of the TFT LCD pixel structure and array substrate of the present invention will be described in detail through specific embodiments in conjunction with the accompanying drawings.

Figure 2 is a schematic diagram of the pixel structure of the TFT LCD array substrate of the present invention, as shown in Figure 2, two adjacent data lines 2 and two adjacent gate scanning lines 1 overlap each other to define a pixel area, each Each pixel structure includes a data line 2 , a gate scanning line 1 and the pixel area. What kind of structure is included in the specific pixel area belongs to the known technology and will not be repeated here. In the present invention, another static elimination region 4 is added near the overlapping region 7 of the data line 2 and the gate scanning line 1 . The A-A cross-sectional view of the static elimination area 4 is shown in Figure 3, which is composed of a gate scan line metal layer (connected to the gate scan line 1), a gate insulating layer 5, and a data line metal layer (connected to the data line 2) . Comparing the prior art shown in FIG. 4 and the B-B sectional view of the overlapping area 7 of the data line 2 and the gate scanning line 1 in the pixel structure provided by the present invention, the overlapping area 7 is between the data line 2 and the gate scanning line An active layer 3 and a gate insulating layer 5 are formed between the lines 1, while the static elimination region 4 is between the metal layer of the gate scanning line and the metal layer of the data line, and only the gate insulating layer 5 (thickness is generally 2000-8000 Angstroms), without active layer 3 (thickness is generally 500 ~ 5000 Angstroms), the distance between the metal layer of the gate scanning line and the metal layer of the data line is shorter, therefore, the distance between the data line 2 and the gate scanning line 1 Compared with the overlapping area 7, the increased static elimination area 4 is an area more prone to breakdown. Therefore, when the accumulation of static electricity occurs, resulting in charge imbalance between the gate scanning line 1 and the data line 2, the static electricity eliminating region 4 provided according to the solution of the present invention first breaks down. Once the static elimination area 4 breaks down, in the subsequent detection and maintenance process, use a Laser to disconnect the static elimination area 4 from the gate scanning line 1 and the data line 2, and the maintenance is simple.

Wherein, the structure of the static elimination region 4 shown in FIG. 2 may also be the same as that of the overlapping region 7, that is, the gate insulating layer 5 and the active layer 3 are included between the metal layer of the gate scan line and the metal layer of the data line. , at this time, as long as the distance between the metal layer of the gate scanning line and the metal layer of the data line is not greater than the distance between the gate scanning line 1 and the data line 2 in the overlapping area 7, the invention object of the present invention can also be achieved . However, when the distance between the gate scanning line metal layer and the data line metal layer is smaller than the distance between the gate scanning line 1 and the data line 2 in the overlapping area 7, the static electricity elimination area 4 described in the present invention will be relatively small. The overlapping region 7 is more prone to breakdown and can achieve better inventive effects.

Similarly, in the prior art, in the overlapping region 7 of the data line 2 and the gate scanning line 1, the active layer 3 may not be included between the gate scanning line 1 and the data line 2, and at this time the overlapping region The structure of 7 is the same as that of the static elimination region 4 shown in FIG. 3. At this time, the static elimination region 4 in the present invention can still use the structure shown in FIG. The thickness of the gate insulating layer in the overlapping region can be no greater than the thickness of the gate insulating layer in the overlapping region, and when the thickness of the gate insulating layer in the static elimination region 4 is smaller than the thickness of the gate insulating layer in the overlapping region, a better invention can be achieved. Effect.

In addition, it is preferable to increase the static elimination area 4 near each overlapping area 7 to protect each overlapping area 7. The number of the increased static elimination area 4 is not limited, but in order to ensure the pixel aperture ratio, the best Good for 1. Alternatively, when the pixel structure shown in FIG. 2 is applied to an array substrate, it is not necessary that each pixel structure includes at least one static elimination region 4, and each gate scanning line 1 may be connected to at least one static elimination region 4, and Each data line 2 is connected to at least one static elimination area 4, so that the purpose of protecting the overlapping area 7 can also be better achieved. Moreover, although the static electricity elimination region 4 has given a specific shape in FIG. 2 . However, in practical application, it is not limited to the shape shown in FIG. Just connect.

It can be seen from FIG. 3 and FIG. 4 that a passivation layer 6 is also covered on the metal layer of the data line in the static elimination area 4 provided by the solution of the present invention, and on the data line 2 in the prior art.

Below, with reference to Fig. 2 and Fig. 3, describe in detail the specific manufacturing method of the TFT LCD array substrate pixel structure of the present invention shown in Fig. 2, as shown in Fig. 5, this method comprises:

Step 501: Deposit a metal thin film on a glass substrate, and form a gate scanning line 1, a gate electrode of a TFT (not shown in FIG. 2 ), and a common electrode signal line (not shown in FIG. ), and the metal layer of the gate scanning line in the static elimination area 4, the metal layer of the gate scanning line in the static elimination area 4 is connected to the corresponding gate scanning line of the static elimination area 4, as shown in FIG. 2 .

Wherein, how to deposit a metal thin film, how to perform photolithography and etching are well known in the prior art, and will not be repeated here.

Wherein, what kind of material the metal thin film is deposited in this step also belongs to the known technology, and will not be repeated here.

Step 502: depositing a gate insulating layer 5 on the substrate after step 501 is completed.

Step 503: Continuously deposit an amorphous silicon thin film and an n+ amorphous silicon thin film on the substrate completed in step 502, and through patterning processes such as photolithography and etching, etc. The overlapping region 7 forms an amorphous silicon layer and an n+ amorphous silicon layer, that is, the active layer 3 . Wherein, the amorphous silicon film and the n+ amorphous silicon film on the static elimination area 4 are etched away, so as to ensure that the distance between the metal layer of the gate scan line and the metal layer of the data line in the static elimination area 4 is smaller than that of the gate scan line in the overlapping area 7 The distance between line 1 and data line 2 is easier to break down.

Wherein, how to deposit the amorphous silicon thin film and the n+ amorphous silicon thin film is very well known in the prior art, and will not be repeated here.

Step 504: Deposit a metal thin film on the substrate that completed step 503, and form the data line 2, the source electrode and the drain electrode of the TFT (not shown in FIG. 2 ), and the static elimination region 4 through patterning processes such as photolithography process and etching process The data line metal layer of the static elimination area 4 is connected to the data line 2 corresponding to the static elimination area 4, as shown in FIG. 2 .

Wherein, the specific material from which the metal thin film is deposited in this step is well known in the prior art, and will not be repeated here.

Step 505 : Deposit a passivation layer 6 on the substrate after step 504 , and form a passivation layer via hole through patterning processes such as photolithography and etching to connect the pixel electrode and the drain electrode of the TFT.

Wherein, which material to use and how to deposit the passivation layer are well known in the prior art, and will not be repeated here.

Step 506: Deposit a pixel electrode layer on the substrate after step 505, and form the pixel electrode through patterning processes such as photolithography process and etching process.

Wherein, which material to use and how to deposit the pixel electrode layer are well known in the prior art, and will not be repeated here.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (9)

1. The pixel structure of the thin film transistor liquid crystal display comprises a data line, a grid scanning line and a pixel area, wherein the data line and the grid scanning line are overlapped to form an overlapped area.

2. The pixel structure according to claim 1, wherein a distance between the gate scan line metal layer and the data line metal layer in the static elimination region is not greater than a distance between the data line and the gate scan line in the overlap region.

3. The pixel structure of claim 2, wherein the insulating layer is: the grid insulation layer is positioned between the grid scanning line metal layer and the data line metal layer; or,

the isolation layer is: the composite layer is composed of a grid insulation layer positioned on the grid scanning line metal layer and an active layer positioned between the grid insulation layer and the data line metal layer.

4. The pixel structure according to any one of claims 1 to 3, wherein the static elimination region is located near an overlapping region of the data line and the gate scan line.

5. A pixel structure according to any one of claims 1 to 3, wherein at least one of said static charge eliminating regions is included in the pixel structure.

6. The array substrate of the thin film transistor liquid crystal display comprises grid scanning lines, data lines and a pixel area, wherein the data lines and the grid scanning lines are overlapped to form an overlapped area.

7. The array substrate of claim 6, wherein the vicinity of the overlapping region of each gate scan line and data line comprises at least one static elimination region.

8. The array substrate of claim 7, wherein each data line is connected to at least one of the static elimination regions, and each gate scan line is connected to at least one of the static elimination regions.

9. The array substrate of any one of claims 5 to 7, wherein the distance between the gate scan line metal layer and the data line metal layer in the static elimination region is not greater than the distance between the data line and the gate scan line in the overlap region.

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