CN101567334A - 加工静电放电阻抗隧道式磁阻性读传感器的方法 - Google Patents
加工静电放电阻抗隧道式磁阻性读传感器的方法 Download PDFInfo
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Abstract
公开了一种加工隧道式磁阻性(TMR)读传感器的方法。在晶片衬底之上淀积绝缘层，在所述绝缘层之上淀积底部导线。在所述底部导线之上淀积具有多个叠层的分层TMR层。在所述TMR层中定义具有磁条高度的TMR传感器，还在所述TMR层中定义并联电阻器以及第一和第二分流电阻器。在所述TMR传感器之上淀积顶部导线。所述并联电阻器被电连接到所述底部导线和所述顶部导线上。所述第一分流电阻器被电连接到所述底部导线和所述晶片衬底上，所述第二分流电阻器被电连接到所述顶部导线和所述晶片衬底上。
Description
技术领域
【0001】本发明总体涉及信息存储器件，并且更具体地涉及用于保护磁性记录头免受静电放电影响的方法。
背景技术
【0002】典型的硬盘驱动器包括磁头盘组件(HDA)和连接到该HDA的磁盘驱动器底部的印刷电路板(PCB)。该磁头盘组件包括至少一个磁盘、用于旋转该磁盘的主轴电动机以及磁头堆组件(HSA)。该电路板组件包括电子元件和固件以用来控制主轴电动机的转动和控制HSA的位置，同时用来在磁盘驱动器与其主机之间提供数据转换通道。
【0003】所述主轴电动机一般包括转子和定子，所述转子包含一个或更多个转子磁铁和在其上安装和夹持磁盘的旋转轮轴。如果多于一个磁盘被安装在该轮轴上，则这些磁盘一般由安装在该轮轴上的磁盘之间的间隔环分离开来。有选择地给所述定子的各种线圈施加电压以产生电磁场，该电磁场推动/拉动所述转子磁铁，由此转动所述轮轴。主轴电动机轮轴的转动致使所安装的磁盘转动。
【0004】所述磁头堆组件一般包括一个致动器、至少一个磁头万向节组件(HGA)和柔性电缆组件。在磁盘驱动器工作期间，致动器必须旋转以将HGA定位到邻近磁盘上的所需信息磁轨处。所述致动器包含枢轴承盒式磁带以便于这一旋转定位。该枢轴承盒式磁带适合于致动器主体的孔径。一个或更多个致动臂从致动器主体延伸出来。致动器线圈由致动器主体支持，且与所述致动臂反向布置。所述致动器线圈被配置为与HDA中一个或更多个(一般为一对)固定磁铁相互作用，以形成音圈电机。印刷电路板组件提供并控制流经致动器线圈的电流，导致一转矩被施加于致动器。
【0005】每一个HGA包括用于对磁盘读出和写入数据的磁头。在磁记录应用中，所述磁头一般包括空气轴承滑块和包含有读写元件的磁传感器。例如，图1描述了包括磁记录头102的典型HGA 100的远端部分。磁头102包括空气轴承滑块104和磁传感器106。该磁传感器的写元件可以是纵向或者垂直设计的，且该磁传感器的读元件一般是磁阻性(MR)的。磁头102粘附于悬架组件110的万向节112。悬架组件110还包括负载束114、弯曲区域(未图示)和锻接板(未图示)。悬架组件110对与磁盘表面相对的空气轴承滑块预加负载。磁传感器的电通讯通过万向节迹线116来完成，该万向节迹线通过焊球120电连接到磁头上的焊盘上。
【0006】所有类型的MR读元件均易于被静电放电(ESD)损坏，尤其隧道式MR读传感器(又名“TMR”读传感器)更容易被静电放电损坏，甚至在相对较低的电压下。保护MR读传感器以免被ESD损坏的现有技术的方法由于各种原因仅具有有限的效果。例如，一些现有技术方法在磁记录头的加工过程中具有不需要的和/或过于复杂的晶片加工步骤。其它的现有技术方法提供不充足的ESD保护和/或在加工过程中没有提供充分早的保护。例如，在加工过程中，在磁头的焊盘被电连接到HGA万向节迹线上之前(可能自身连接到一些保护电路)，TMR读传感器特别易被ESD损坏。因此，本领域需要一种加工包含TMR读传感器的读传感器的改进方法。
发明内容
【0007】公开了一种加工隧道式磁阻性(TMR)读传感器的方法并要求进行保护。在晶片衬底之上淀积绝缘层，并在绝缘层之上淀积底部导线。在底部导线之上淀积具有多个层的分层TMR层。在TMR层中定义具有磁条高度的TMR传感器，且在TMR层中还定义并联电阻器和第一和第二分流电阻器。在TMR传感器之上淀积顶部导线。并联电阻器电连接到底部导线和顶部导线上。第一分流电阻器电连接到底部导线和晶片衬底上，第二分流电阻器电连接到顶部导线和晶片衬底上。
附图说明
【0008】图1描述当前的磁头万向节组件的远端部分。
【0009】图2描述根据本发明实施例的加工隧道式磁阻性读传感器的方法。
【0010】图3A是根据本发明实施例的隧道式磁阻性读传感器的示意图。
【0011】图3B是描述垂直于分层TMR层的平面的电流流动示意图。
【0012】图3C是描述平行于分层TMR层的平面的电流流动示意图。
【0013】图4描述根据本发明实施例的晶片表面区域。
【0014】图5描述包括本发明六个其它实施例的晶片表面区域。
【0015】图6描述根据本发明另一个实施例的晶片表面区域。
【0016】图7描述根据本发明另一个实施例的晶片表面区域。
具体实施方式
【0017】MR读传感器可以包括多种叠层结构，每层展示出独特的加工挑战和有希望的独特的潜在性能特征和灵敏度。隧道式MR读传感器(又名“TMR”读传感器)是MR读传感器的最灵敏类型中的一种，因此可用于探测非常微弱的磁场。TMR读传感器是叠层结构，它们包括包含薄“势垒”叠层在内的多种叠层，该薄“势垒”叠层包含可能整体呈绝缘性的材料。
【0018】势垒叠层的完整性会强烈影响TMR读传感器的性能，但这一完整性会被静电放电(ESD)所抵消。例如，次要ESD事件会在势垒叠层中造成针孔(pin-hole)缺陷，这些缺陷会降低TMR读传感器的性能，而主要ESD事件会严重损坏势垒叠层，显著毁坏TMR读传感器。
【0019】图2描述根据本发明实施例的加工隧道式磁阻性读传感器的方法200。在步骤202中，在晶片衬底之上淀积绝缘层。该绝缘层可以包含氧化铝(例如，矾土)、氧化硅或诸如其它金属氧化物之类的其它绝缘材料。在步骤204中，在绝缘层之上淀积底部导线。此处所用的术语“之上”希望包括，例如，部分重叠或完全重叠的情况。此外，与这一公开相一致的是，重叠层可以理解为在底层“之上”，其中重叠层直接淀积在底层上，或者其中一个或更多个中间层位于重叠层和底层之间。底部导线可以包含导电金属，例如钽、金、铝、镍、钴、铁或铜，或其合金或叠层。
【0020】仍然参考图2的实施例，在步骤206中，在底部导线之上淀积分层TMR层。该分层TMR层可以是所谓的全膜层，例如，其覆盖了比下面要通过刻蚀定义的TMR传感器的预想区域大得多的区域。分层TMR层包含多个叠层。例如，所述多个叠层可以包括一个或更多个子叠层。该子叠层可以包括一种或更多种金属，例如钽、铬、镍、铁和/或钌。在某些实施例中，这一子叠层的厚度可为
(埃)到
所述多个叠层也可以包括抗铁磁性叠层。例如，这一抗铁磁性叠层可包含铂锰或铱锰。在某些实施例中，这一抗铁磁性叠层的厚度可为到所述多个叠层也可以包括一个或更多个铁磁针插(pinned)叠层，可能包含例如镍、铁和/或钴。在某些实施例中，这种铁磁针插叠层的厚度可为
到
所述多个叠层包括至少一个势垒叠层，该势垒叠层包含可能整体呈绝缘性的材料，例如，氧化铝、氧化钛或氧化镁，和/或氮化铝、氮化硅或氮化铌。在某些实施例中，这一势垒叠层的厚度可为到
所述多个叠层也可以包括一个或更多个铁磁单体叠层，可能包括例如镍、铁和/或钴。在某些实施例中，这一铁磁单体叠层的厚度可为
到
所述多个叠层也可以包括一个或更多个顶盖叠层，可能包含例如钽或钌。在某些实施例中，这一顶盖叠层的厚度可为
到
所述分层TMR膜可优选阻值面积的乘积不大于10′Ω*μm2。
【0021】仍然参考图2的实施例，在步骤208中，在TMR层中定义TMR传感器。该TMR传感器可以由通过例如刻蚀定义的磁条高度来刻画。这一刻蚀可以利用真空加工设备来实现，该设备是例如用来引导离子瞄准装入排气室的晶片靶的商用设备。在步骤210中，在TMR层中定义并联电阻器。在优选实施例中，利用与步骤208所用的相同真空加工设备和相同刻蚀技术来完成步骤210。在优选实施例中，步骤210与步骤208在单个工艺步骤中同时进行。在步骤212中，在TMR层中定义第一和第二分流电阻器。在优选实施例中，步骤212是通过使用与步骤208和210中所用的相同真空加工设备和相同刻蚀技术来完成的。在优选实施例中，步骤212与步骤208和210在单个工艺步骤中同时进行。
【0022】仍然参考图2的实施例，在步骤218中，在TMR传感器之上淀积顶部导线。该顶部导线优选但非必需包括一种或更多种与步骤204淀积的底部导线所用的相同金属。该顶部导线可以在一个或更多个定义步骤210和212之前或之后淀积，但是优选在所有定义步骤208、210和212之后进行淀积。
【0023】仍然参考图2的实施例，在步骤214中第一分流电阻器被电连接到底部导线和晶片衬底上，而在步骤216中第二分流电阻器被电连接到顶部导线和晶片衬底上。可以通过在步骤206中淀积TMR层之前图案化在步骤202被淀积在晶片衬底上的绝缘层来部分完成步骤214和216。也可以通过淀积和图案化导电层(例如金属层)，如用于定义顶部导线的所述层，来部分或全部完成步骤214和216。例如，步骤218的执行优选但非必需同时部分执行步骤216(例如在淀积顶部导线以便与第二分流电阻器相接触的实施例中)。
【0024】仍然参考图2的实施例，在步骤220中并联电阻器被电连接到底部导线和顶部导线。可以通过在步骤206中在底部导线之上淀积分层TMR层来部分完成步骤220。也可以通过淀积和图案化导电层(例如金属层)，如用于定义顶部导线的所述层，来部分完成步骤220。例如，步骤218的执行优选但非必需同时部分执行步骤220(例如在淀积顶部导线以便与并联电阻器相接触的实施例中)。
【0025】磁阻性(MR)读元件响应所施加的磁场来改变电阻。电阻的变化量ΔR可表示为与整体电阻之比，即ΔR/R。为了测量ΔR和R，可以使电流穿过MR读元件，同时测量其两端的电压。通过淀积于MR读元件上或邻近MR读元件的导线，电流流入和流出MR读元件。例如，导线可淀积在MR元件相反的两端上，且电流在MR元件的平面内流过。通过这样的导线结构，MR元件可作为“电流在平面内”(即CIP)的MR元件来运行。作为替代，导线可淀积在MR元件相反的两侧上，且电流沿垂直于MR元件平面的方向流过MR元件。通过这样的导线结构，MR元件可作为“电流垂直于平面”(即CPP)的MR元件来运行。
【0026】图3A是根据本发明实施例的隧道式磁阻性读传感器300的示意图。分层TMR层310包括势垒叠层312。在图3A中叠层厚度不是按比例示出的，使得势垒叠层的表观的相对厚度被夸大以增强标注的清晰度。顶部导线314位于分层TMR层310中用于定义TMR传感器350的一部分的上面，而底部导线316则位于该部分的下面。顶部导线314被电连接到焊盘370和并联电阻器320上。底部导线316被电连接到焊盘380和并联电阻器320上。分流电阻器330被电连接到顶部导线314和衬底336上。分流电阻器340被电连接到底部导线316和衬底336上。
【0027】在图3A的实施例中，并联电阻器320以及分流电阻器330和340利用部分(未图示)分层TMR层310，但与TMR传感器350的利用方式不同。具体地说，尽管在TMR传感器350中电流Itmr沿垂直与分层TMR层310的平面的方向流动(如图3B所示)，但在并联电阻器和分流电阻器中电流Iesd沿平行于分层TMR层310的平面流动(如图3C所示)。
【0028】在本发明的不同实施例中，并联电阻器和分流电阻器可采用不同的形式。例如，图4描述了依据本发明的实施例包括多个读传感器的晶片表面区域。现在关注图4中部所示的读传感器400，并联电阻器420被电连接到焊盘470上，该焊盘被电连接到顶部导线(未图示)。并联电阻器420也被电连接到焊盘480，该焊盘被电连接到底部导线(未图示)。在图4的实施例中，并联电阻器420被定义为具有并联电阻器路径宽度和并联电阻器路径长度的矩形。在某些实施例中，优选并联电阻器路径宽度和并联电阻器路径长度被选择以使该并联电阻器的阻值范围为0.1k′Ω到5k′Ω。在某些实施例中，优选并联电阻器路径宽度被选择在0.2微米到5微米范围内。在某些实施例中，优选并联电阻器路径长度被选择在5微米到1250微米范围内。在某些实施例中，并联电阻器420可以提供额外保护以防止ESD毁坏TMR传感器，和/或使TMR传感器的动态范围更加可控。
【0029】在图4的实施例中，分流电阻器430被电连接到焊盘470上并通过通孔460连接到衬底上，分流电阻器440被电连接到焊盘480上并通过通孔460连接到衬底上。在某些实施例中，分流电阻器430的阻值优选在分流电阻器440的阻值的±10％范围内。在图4的实施例中，分流电阻器430和440分别被定义为具有蛇形形状，并分别具有分流电阻器路径宽度和分流电阻器路径长度。在某些实施例中，分流电阻器路径宽度和分流电阻器路径长度被选择，从而每个分流电阻器430和440优选具有大于1k′Ω的阻值。在某些实施例中，分流电阻器路径宽度优选被选择在0.2微米到5微米范围内。在某些实施例中，分流电阻器路径长度优选被选择在50微米到50毫米范围内。
【0030】图5描述包括本发明的六个其它实施例的晶片表面区域，其中为了更加清晰地描述分流电阻器的几何形状未在图中显示并联电阻器。分流电阻器530、531、532、533、534和535分别电连接到焊盘570、571、572、573、574和575，同时分别通过通孔560、561、562、563、564和565连接到衬底上。分流电阻器540、541、542、543、544和545分别电连接到焊盘580、581、582、583、584和585，同时分别通过通孔560、561、562、563、564和565连接到衬底上。每个分流电阻器530、531、532、533、534和535均为蛇形形状，且具有不同的分流电阻器路径长度以实现不同的所需电阻值。每个分流电阻器540、541、542、543、544和545也均为蛇形形状，且具有不同的分流电阻器路径长度以实现不同的所需电阻值。在某些实施例中，在考虑分层TMR层的电阻率并考虑所选的实际分流电阻器路径宽度的情况下，选择分流电阻器路径长度以使得到的电阻值大于1k′Ω。在某些实施例中，实际分流电阻器路径宽度优选被选择在0.2微米到5微米范围内。
【0031】图6描述根据本发明另一实施例的晶片表面区域，其中为了更加清晰地描述分流电阻器的几何形状未在图中显示并联电阻器。分流电阻器630被电连接到焊盘670上并通过通孔660连接到衬底上。分流电阻器640被电连接到焊盘680上并通过通孔660连接到衬底上。分流电阻器630和640均为蛇形形状，且在某些实施例中分流电阻器630的阻值优选在分流电阻器640的阻值的±10％范围内。
【0032】图7描述根据本发明另一实施例的晶片表面区域。并联电阻器720为蛇形形状，并被连接到焊盘770上，该焊盘被电连接到顶部导线(未图示)。并联电阻器720还被电连接到焊盘780上，该焊盘被电连接到底部导线(未图示)。分流电阻器730也为蛇形形状，其被电连接到焊盘770上并通过通孔760连接到衬底上。分流电阻器740也为蛇形形状，其被电连接到焊盘780并通过通孔760连接到衬底上。
【0033】在前述的说明中，通过参考其具体的示例性实施例对本发明进行了描述，但本领域的技术人员应该认识到本发明并不限制于此。可以预期上述发明中的各种特征和方面可单独使用或联合使用，并可应用于超出本文所述这些示例的环境和应用中。因此，说明书和附图被认为是说明性的和示例性的而不是限制性的。在本文中使用的术语“包含”、“包括”和“具有”希望被解读为开端(open-ended)术语。
Claims (15)
1.一种加工隧道式磁阻性TMR读传感器的方法，其包括以下步骤：
在晶片衬底之上淀积绝缘层；
在所述绝缘层之上淀积底部导线；
在所述底部导线之上淀积分层TMR层，所述分层TMR层包含多个叠层；
在所述TMR层中定义具有磁条高度的TMR传感器；
在所述TMR层中定义并联电阻器；
在所述TMR层中定义第一和第二分流电阻器；
在所述TMR传感器之上淀积顶部导线；
电连接所述并联电阻器到所述底部导线和所述顶部导线；
电连接所述第一分流电阻器到所述底部导线和所述晶片衬底；
电连接所述第二分流电阻器到所述顶部导线和所述晶片衬底。
2.根据权利要求1所述的方法，其中定义所述传感器磁条高度、定义所述并联电阻器和定义所述第一和第二分流电阻器的动作均包括刻蚀所述TMR层。
3.根据权利要求2所述的方法，其中定义所述传感器磁条高度的动作是利用真空加工设备并通过刻蚀技术完成的，且其中定义所述并联电阻器和定义所述第一和第二分流电阻器的动作是利用相同的真空加工设备并通过相同的刻蚀技术完成的。
4.根据权利要求2所述的方法，其中定义所述传感器磁条高度、定义所述并联电阻器和定义所述第一和第二分流电阻器的步骤是在单个工艺步骤中同时执行的。
5.根据权利要求1所述的方法，其中所述第一分流电阻器的阻值在所述第二分流电阻器的阻值的±10％范围内。
6.根据权利要求1所述的方法，其中所述第一和第二分流电阻器中的每一个均被定义具有分流电阻器路径宽度和分流电阻器路径长度，且其中所述分流电阻器路径宽度和所述分流电阻器路径长度被选择以使所述第一和第二分流电阻器中的每一个具有大于1k′Ω的阻值。
7.根据权利要求6所述的方法，其中所述第一和第二分流电阻器中的每一个被定义为具有蛇形形状。
8.根据权利要求6所述的方法，其中所述分流电阻器路径宽度被选择为在0.2微米到5微米范围内。
9.根据权利要求6所述的方法，其中所述分流电阻器路径长度被选择为在50微米到50毫米范围内。
10.根据权利要求1所述的方法，其中所述并联电阻器被定义为具有并联电阻器路径宽度和并联电阻器路径长度，且其中所述并联电阻器路径宽度和所述并联电阻器路径长度被选择以使所述并联电阻器的阻值范围在0.1k′Ω到5k′Ω。
11.根据权利要求10所述的方法，其中所述并联电阻器路径宽度被选择为在0.2微米到5微米范围内。
12.根据权利要求10所述的方法，其中所述并联电阻器路径长度被选择为在5微米到1250微米范围内。
13.根据权利要求1所述的方法，其中所述多个叠层包括势垒叠层，该势垒叠层包含氧化铝、氧化钛或氧化镁，该氧化物整体上呈电绝缘性。
14.根据权利要求1所述的方法，其中所述多个叠层包括势垒叠层，该势垒叠层包含氮化铝、氮化硅或氮化铌，该氮化物整体上呈电绝缘性。
15.根据权利要求1所述的方法，其中所述分层TMR层具有不大于10′Ω*μm2的阻值面积乘积。
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2007
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2008
- 2008-04-24 CN CN2008100923694A patent/CN101567334B/zh not_active Expired - Fee Related
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104133098A (zh) * | 2013-05-03 | 2014-11-05 | 英飞凌科技股份有限公司 | 电子电路的布线结构中电流测量的集成 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101567334B (zh) | 2011-08-17 |
| HK1136902A1 (en) | 2010-07-09 |
| US7389577B1 (en) | 2008-06-24 |
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