CN101561483A

CN101561483A - Chip design method for improving acquisition speed of Big Dipper satellite signals on the basis of clock frequency multiplication

Info

Publication number: CN101561483A
Application number: CNA2009100689530A
Authority: CN
Inventors: 宋保军; 王祥峰; 华中; 侯亚峰; 常亮; 吕岭鹏; 刘世峰
Original assignee: TIANJIN COMMUNICATION AND BROADCASTING MICRO-ELECTRONICS Co Ltd; Beijing Hualongtong Technology Co Ltd
Current assignee: Beijing Hualongtong Technology Co., Ltd.; Tianjin 712 Communication and Broadcasting Co Ltd
Priority date: 2009-05-21
Filing date: 2009-05-21
Publication date: 2009-10-21
Anticipated expiration: 2029-05-21
Also published as: CN101561483B

Abstract

The invention relates to a chip design method for improving the acquisition speed of Big Dipper satellite signals on the basis of clock frequency multiplication. The method arranges a clock frequency multiplication module, a high-frequency sampling module and a low-frequency conversion module on the front and the rear of an acquisition module in the prior art, wherein analog signals enter a digital-to-analog conversion module to become digital signals, and then the digital signals are sent to the high-frequency sampling module to improve the data sampling frequency and meet high-speed clock requirement; the acquisition module adopts a high-speed clock to process data after data storage and obtains an operation result; and finally the low-frequency conversion module outputs converted low-frequency marks, wherein the clock frequency multiplication module outputs N times of clock for the high-frequency sampling module, the acquisition module and the low-frequency conversion module. The method improves the acquisition speed and simultaneously guarantees the high sensitivity of acquisition.

Description

Improve the chip design method of Big Dipper satellite signal capture speed based on clock multiplier

Technical field

The present invention relates to the design of big-dipper satellite baseband processing chip, relate in particular to a kind of chip design method that improves Big Dipper satellite signal capture speed based on clock multiplier.

Background technology

Main modular such as big-dipper satellite baseband processing chip in traditional design (hereinafter to be referred as Big Dipper baseband chip) is inner catches, follow the tracks of, synchronous all are to be operated under the identical frequency.After Big Dipper baseband chip receives Big Dipper satellite signal, at first convert thereof into digital signal, then it is comprised that a series of complex calculation such as sampling, frequency conversion, storage, frequency and phase search, judgement finish its acquisition procedure, after acquisition success, just begin Big Dipper satellite signal is followed the tracks of and synchronous operation.In order to improve the minimum signal strength that acquisition sensitivity promptly can be caught, have in the traditional design in catching this part, lot of data be carried out complex calculations, and the high more calculated amount of sensitivity that requires is just big more, thereby makes acquisition procedure become the longest part consuming time in the Base-Band Processing.The design of trapping module had both determined the sensitivity of catching also to determine to catch the spent time in the whole Base-Band Processing simultaneously in the Big Dipper baseband chip, how to guarantee that again acquisition sensitivity has become the bottleneck of traditional design under the situation that reduces capture time.

Summary of the invention

At existing situation, the objective of the invention is, provide a kind of and improve the method for the acquisition speed of big-dipper satellite based on clock multiplier, so just can under the prerequisite that guarantees acquisition sensitivity, reduce and catch the used time.

The objective of the invention is to realize by such technical scheme, a kind of chip design method that improves Big Dipper satellite signal capture speed based on clock multiplier, the big-dipper satellite baseband processing chip comprises trapping module, it is characterized in that, increase clock multiplier module, high frequency sampling module and low frequency modular converter before the trapping module in the big-dipper satellite baseband processing chip of traditional design and behind the trapping module.

The simulating signal that comes from satellite is admitted to the AD D/A converter module and is transformed into digital signal;

The digital signal of AD D/A converter module output is admitted to the high frequency sampling module;

The system clock frequency signal produces N and doubly send tremendously high frequency sampling module, trapping module and low frequency modular converter respectively to the clock of system clock frequency as catching local work clock through the clock multiplier resume module;

The clock multiplier module is used for producing the frequency N clock doubly that has clock now and is used as catching local work clock, simulating signal enters delivers to the high frequency sampling module after D/A converter module becomes digital signal, the low-speed clock data that the high frequency sampling module comes out digital-to-analog conversion are converted to the high power clock data and flow to and catch part, and trapping module adopts the high-frequency clock deal with data to draw operation result after the data storage; The low frequency modular converter then is converted to original low-speed clock with some marking signals of trapping module output after finishing and flows to the back and do to follow the tracks of and handle catching.

The advantage of this method is: can guarantee the sensitivity of catching when improving acquisition speed again.

Description of drawings

Fig. 1: general trapping module block diagram;

Fig. 2: based on the design frame chart of clock multiplier raising Big Dipper satellite signal capture speed, and as Figure of abstract;

The data input high frequency sampling module synoptic diagram of Fig. 3: AD (D/A converter module)

Fig. 4: capture of labels input low frequency modular converter synoptic diagram;

Fig. 5: clock multiplier module side synoptic diagram;

Embodiment

Describe implementation process of the present invention in detail below in conjunction with accompanying drawing:

As shown in Figure 1, simulating signal enters and delivers to trapping module after D/A converter module becomes digital signal.Trapping module is caught back output to it and is caught whether successful mark continues to handle for other module.This system works is under same frequency.

As shown in Figure 2, simulating signal enters D/A converter module and becomes and deliver to the high frequency sampling module after the digital signal and improve the data sampling frequency and satisfy the high-frequency clock requirement, trapping module adopts the high-frequency clock deal with data to draw operation result after the data storage, at last by the lf marker after the low frequency modular converter output conversion.Wherein N times of clock of clock multiplier module output offers high frequency sampling module, trapping module and low frequency modular converter.

As shown in Figure 3, simulating signal enters delivers to the high frequency sampling module after D/A converter module becomes digital signal, because the clock difference of two modules causes same data can become N data under N clock doubly, because N data are identical data, so can select one of them data arbitrarily, choose second data in N the data in the reality.

As shown in Figure 4, the capture of labels of having caught back output is given other module, and we must reduce to original system clock with its clock before handling, so we need prolong N to the lasting incident of marking signal and doubly could be adopted by the module of back.

As shown in Figure 5, clock multiplier module module is the clock of input to be exported as required the clock of different multiples, realizes under the prior art that clock multiplier is fairly simple, and the clock multiplier module that is adopted in actual applications is general standard module.

Claims

1. chip design method that improves Big Dipper satellite signal capture speed based on clock multiplier, the big-dipper satellite baseband processing chip comprises trapping module, it is characterized in that: increase clock multiplier module, high frequency sampling module and low frequency modular converter before the trapping module in the big-dipper satellite baseband processing chip and behind the trapping module; The frequency N clock doubly that uses the clock multiplier module to produce existing clock is used as catching local work clock, simulating signal enters delivers to the high frequency sampling module after D/A converter module becomes digital signal, the low-speed clock data that the high frequency sampling module comes out digital-to-analog conversion are converted to the high power clock data and flow to and catch part, trapping module adopts the high-frequency clock deal with data to draw operation result after the data storage, and the low frequency modular converter then is converted to original low-speed clock with some marking signals of trapping module output after finishing and flows to the back and do to follow the tracks of and handle catching.