CN201096890Y - Detection device for real time computation of centroid of onsite programmable logic array - Google Patents

Abstract

The utility model belongs to the technical field of photoelectric imaging and tracking, and relates to a real-time calculation spot centroid detection device of a field programmable logic array. The device consists of an image input unit (21), an image output unit (24), a centroid data output unit (25), a field programmable logic array unit (31), and a field programmable logic array auxiliary device unit (32). ; This device can solve the light spot centroid data of an image in tens of nanoseconds, so the bottleneck bandwidth limitation of the APT system is transferred from the image processing equipment to the photoelectric imaging equipment, that is, the CCD camera or CMOS camera, thereby greatly improving the APT. The overall bandwidth of the system. The calculation speed is increased from 500 to 2,000 images per second of the existing DSP embedded image processing system to 3,000 to 10,000,000 images per second; the equipment volume is reduced from the original 200mm×300mm×30mm to 300mm×500mm×800mm to 150mm×150mm×30mm; the power consumption is reduced from 0.8w to 2.0w to 0.5w; the number of devices is reduced from 20 to 30 to 15.

Description

The detecting device for real-time computing facula mass center of field programmable logic array (FPLA)

Technical field

The utility model belongs to photoelectronic imaging tracking technique field, relates to the detecting device for real-time computing facula mass center of field programmable logic array (FPLA).

Background technology

In laser space communication system, the beacon laser of communicating pair needs at first the other side orientation to be caught, and accurately aims at the other side's fiber optic then, re-uses communication laser and communicates, and remain the accurate aligning of beacon beam to the other side in the process of communication.This process promptly is called catches (Acquisition), aligning (Pointing), tracking (Tracking), is called for short APT.(list of references: " technical research of free space optical communication ATP system core ", author Shao Bing etc., publication " piezoelectricity and acousto-optic ").

Fig. 1 is the structural representation of APT device.By thick tracking camera unit 11, smart camera unit 12, the image processing equipment unit 13 followed the tracks of, diaxon servo turntable unit 14 constitutes.

The thick camera unit 11 of following the tracks of is exported to image processing equipment unit 13 with image.Image processing equipment unit 13 is actually the device that calculates facula mass center, and it is industrial computer (PC), embedded small computing machine (PC104 machine), ARM embedded image disposal system or DSP embedded image disposal system.

Wherein, DSP embedded image disposal system is the comparatively desirable a kind of image processing apparatus of every comparatively speaking performance index.Fig. 2 is the DSP embedded image disposal system structural representation of APT device.Form by image input block 21, digital signal processor (DSP) unit 22, DSP additional device unit 23, image output unit 24 and barycenter data output unit 25.(list of references: PhD dissertation " design of embedded colored TV tracker system and realization ", author Gu Haijun, china academia periodical (CD version) e-magazine society) still, digital signal processor (DSP) unit 22 is the same with other device of image processing equipment unit 13, exists problems such as the computing degree is low, volume is big, power consumption is high, number of devices is numerous.

Summary of the invention

For there are problems such as arithmetic speed is low, volume is big, power consumption is high, number of devices is numerous in the DSP embedded image disposal system that overcomes the APT device, the utility model provides a kind of pick-up unit of the real-time computing facula mass center based on field programmable logic array (FPLA).

According to the manufacturing principle of field programmable logic array (FPLA) as can be known, this Flame Image Process account form is based on the pure hardware digital circuit basis, so have advantages such as real time high-speed, volume are little, low in energy consumption, multithreading.

As shown in Figure 3, the composition of the detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model has image input block 21, image output unit 24, barycenter data output unit 25 also have field programmable logic array (FPLA) unit 31, field programmable logic array (FPLA) additional device unit 32; Described field programmable logic array (FPLA) unit 31 respectively with image input block 21, image output unit 24, barycenter data output unit 25, field programmable logic array (FPLA) additional device unit 32 connects.

During use, a kind of detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model is connected with diaxon servo turntable unit 14 with the thick tracking camera unit 11 of APT device, the smart camera unit 12 of following the tracks of;

The dynamic duty process of a kind of detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model is as follows: by thick tracking camera unit 11 or smartly follow the tracks of the data image signal that camera unit 12 is sent out, convert to enter in the field programmable logic array (FPLA) unit 31 behind the parallel digital signal through image input block 21 and handle.Use hardware description language (VHDL, Verylog, AHDL all can) making software, and will be downloaded to behind this software translating in the field programmable logic array (FPLA) unit 31, this software is finished following technical functionality:

A) sequential of change input signal deposits among the FIFO and cushions;

B) digital picture of input is carried out initialization process, remove garbage signal, improve signal to noise ratio, obtain light spot image more easy to identify;

C) all pixel grey scales are differentiated, the shared pixel of identification hot spot obtains light spot shape information;

D) the shared pixel of hot spot is resolved, obtain the center-of-mass coordinate data;

E) send the center-of-mass coordinate data to diaxon servo turntable 14 by barycenter data output unit 25;

F) suitably select some consecutive image to export to miscellaneous equipment by visual output unit 24, other surveillance equipment can be VGA display, PAL/NTSC monitor, is used for manually monitoring and other purposes processing.

The digital picture that enters field programmable logic array (FPLA) unit 31 is to need the image information of processing in real time, this digital picture simplified to take out can send other surveillance equipment to by image output unit 24 after frame is handled, image output unit 24 can be Camera Link interface mode, VGA interface mode, the output of LVDS difference, 1394 interface modes, usb mode, serial output mode, LVTTL the walk abreast way of output, pal mode or TSC-system formula.Other surveillance equipment can be VGA display, PAL/NTSC monitor, is used for manually monitoring and other purposes processing.The way of output can be selected digital signal output or simulating signal output.

After calculating facula mass center by field programmable logic array (FPLA) unit 31, the barycenter data are exported to diaxon servo turntable unit 14 by barycenter data output unit 25.Barycenter data output unit 25 can be exported the barycenter data for which kind of mode no matter RS485 serial mode, RS232 serial mode, the LVDS difference way of output or the LVTTL way of output adopt, all will satisfy the requirement of input picture frame frequency, strictness is accomplished whenever to come piece image and is then exported one group of barycenter data.

The effect that the utility model is useful: the utility model has characteristics such as multithreading, high integration owing to adopted the digital circuit mode of pure hardware to carry out Digital Image Processing.The field programmable logic array (FPLA) device of this device can calculate the facula mass center data of piece image in tens nanoseconds, so that it is CCD camera or CMOS camera that the bottleneck bandwidth of APT system restriction has been transferred to photoelectronic imaging equipment by image processing equipment, thereby improved the overall bandwidth of APT system greatly.

Advantages such as the speed that the utlity model has is fast, volume is little, low in energy consumption, number of devices is few improve system reliability, have reduced cost.Computing velocity is brought up to per second 3000～10000000 width of cloth images by per second 500 width of cloth～2000 width of cloth images of the DSP embedded image disposal system of former utility model; Equipment volume is reduced to 150mm * 150mm * 30mm by original 200mm * 300mm * 30mm～300mm * 500mm * 800mm; Power consumption drops to 0.5w by original 0.8w～2.0w; Number of devices reduces to 15 by original 20～30.

Description of drawings

Fig. 1 is the structural representation of APT.

Fig. 2 is a DSP embedded image disposal system structural representation.

Fig. 3 is a kind of detecting device for real-time computing facula mass center structural representation based on field programmable logic array (FPLA) of the utility model.

The structural representation of Fig. 4 embodiment 1.

Fig. 5 software synoptic diagram.

Embodiment:

Embodiment 1

As shown in Figure 3, the composition of the detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model has image input block 21, image output unit 24, barycenter data output unit 25 also have field programmable logic array (FPLA) unit 31, field programmable logic array (FPLA) additional device unit 32; Described field programmable logic array (FPLA) unit 31 respectively with image input block 21, image output unit 24, barycenter data output unit 25, field programmable logic array (FPLA) additional device unit 32 connects.

During use, a kind of detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model is connected with diaxon servo turntable unit 14 with the thick tracking camera unit 11 of APT device, the smart camera unit 12 of following the tracks of.

Device shown in Figure 4 is one of specific embodiments of the detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model as shown in Figure 3:

1) the field programmable logic array (FPLA) unit 31, use hardware description language (VHDL, Verylog or AHDL all can) making software, and will be downloaded in the field programmable logic array (FPLA) unit 31 behind this software translating.As shown in Figure 5, constituting of the structural unit corresponding: Clock management module 51, image interface module 52, adaptive threshold module 53,3 * 3 window modules 54, line count device module 55, hot spot judge module 56, centroid calculation module 57, VGA display module 58 and miss distance output module 59 with software;

Described Clock management module 51 is connected with VGA display module 58; Image interface module 52 is connected respectively with VGA display module 58 with Clock management module 51, adaptive threshold module 53,3 * 3 window modules 54, line count device module 55; Hot spot judge module 56 is connected respectively with centroid calculation module 57 with adaptive threshold module 53,3 * 3 window modules 54; Centroid calculation module 57 also is connected respectively with miss distance output module 59 with line count device module 55; VGA display module 58 is connected with image output unit 24; Miss distance output module 59 also is connected with barycenter data output unit 25; Described image interface module 52 also is connected with DS90CR287 unit 43, DS90LV048 unit 44 and the DS90LV0475 unit 45 of image input block 21;

(1) the Clock management module 51: be responsible for the reference clock of crystal oscillator unit 41 inputs of field programmable logic array (FPLA) additional device unit 32 is handled, and the signal behind frequency multiplication and the frequency division is sent to other module make the benchmark drive clock.

(2) the image interface module 52: the image parallel data of input can be handled, and therefrom extraction place field effectively, row effectively, signal such as pixel is effective, give the subsequent treatment module respectively with view data.

(3) the adaptive threshold module 53: pixel grey scale value of averaging of a last field picture can be calculated, thereby obtain the comparison gray-scale value of this field picture pixel.

(4) 3 * 3 window modules 54: image pixel is carried out medium filtering handle, the noise pixel in the image can be removed like this, thereby obtain image information more easy to identify.

(5) line count device module 55: for the centroid calculation module provides some locations of pixels information, promptly the place line number and the columns of pixel are counted, and offered the centroid calculation module.

(6) the hot spot judge module 56: obtain relatively to compare with all pixels that will be worth behind the gray-scale value with this field picture from the adaptive threshold module, thereby determine which pixel of this field picture is the pixel that comprises facula information.

(7) the centroid calculation module 57: use the pixel data that comprises facula information to calculate, and calculate facula mass center according to following formula:

$\stackrel{\‾}{x}=\frac{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}i(G_{\mathrm{ij}}-T)}{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}(G_{\mathrm{ij}}-T)}$

$\stackrel{\‾}{y}=\frac{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}j(G_{\mathrm{ij}}-T)}{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}(G_{\mathrm{ij}}-T)}$

Wherein, T is a pixel threshold value relatively, G _IjBe the gray-scale value of the shared pixel of hot spot, x and y are respectively the ranks value (position coordinates just) of facula mass center.

(8) the VGA display module 58: use the parallel data form to send AL250 unit 24 to image.

(9) the miss distance output module 59: the data and the picture centre coordinate that are sent by the centroid calculation module compare, thereby the distance that draws the centroid distance center is the miss distance data, sends these miss distance data to barycenter output unit 25 by the UART serial mode.

2) as shown in Figure 4, field programmable logic array (FPLA) additional device unit 32 is made of jointly crystal oscillator unit 41, EPC2 unit 42; Crystal oscillator unit 41: be responsible for providing reference clock with field programmable logic array (FPLA) unit 31; EPC2 unit 42: be a kind of eeprom memory, after total system powers on, can send the Automatic Program of the field programmable logic array (FPLA) preserved in it to field programmable logic array (FPLA) unit 31.

3) as shown in Figure 4, image input block 21 is made of jointly DS90CR287 unit 43, DS90LV048 unit 44, DS90LV047 unit 45; The DS90CR287 unit 43 of image input block 21 is chip DS90CR288: be a kind of Camera Link transport protocol conversion device, the LVDS level formal transformation that meets the CameraLink transmission mode can be become the parallel data of 28 road LVTTL level forms; The DS90LV048 unit 44 of image input block 21 is chip DS90LV048: be a kind of Camera Link transport protocol conversion device, the LVDS level formal transformation that meets Camera Link transmission mode can be become the parallel data of 4 road LVTTL level forms; The DS90LV047 unit 45 of image input block 21 is chip DS90LV047: be a kind of Camera Link transport protocol conversion device, the parallel data of 4 road LVTTL level forms can be converted to the LVDS level form that meets Camera Link transmission mode.

4) image output unit 24 is chip AL250: the parallel image data-switching of programmable logic array unit 31 outputs can be become meet the view data of VGA form, can directly connect other VGA image display.

5) barycenter data output unit 25 is chip MAX485: can convert the serial miss distance data of unit 31 outputs to meet the RS485 host-host protocol device by LVTTL, be about to the miss distance data serial and export to diaxon servo turntable unit 14.

Need to prove that described image input block 21 can also be VGA interface mode, the output of LVDS difference, 1394 interface modes, usb mode, serial output mode, the LVTTL parallel way of output, pal mode or TSC-system formula except CameraLink interface mode that this preferred embodiment proposed is; Field programmable logic array (FPLA) unit 31 is existing commodity; Image output unit 24 can also be Camera Link interface mode, the output of LVDS difference, 1394 interface modes, usb mode, serial output mode, the LVTTL parallel way of output, pal mode or TSC-system formula except the VGA mode that this preferred embodiment proposed; Barycenter output unit 25 can also be RS232 serial mode, the LVDS difference way of output or the LVTTL way of output except the RS485 serial mode that this preferred embodiment proposed, no matter adopt which kind of mode to export the barycenter data, all will satisfy the requirement of input picture frame frequency, strictness is accomplished whenever to come piece image and is then exported one group of barycenter data.

Claims (3)

1. The real-time calculation light spot centroid detection device of field programmable logic array, the composition of this device has image input unit (21), image output unit (24), centroid data output unit (25), it is characterized in that, also has on-site Programming logic array (31), field programmable logic array auxiliary device unit (32); Described field programmable logic array (31) is respectively connected with image input unit (21), image output unit (24), centroid data output unit (25), field programmable logic array auxiliary device unit (32) is connected; The real-time calculation spot centroid detection device of the field programmable logic array is connected with the coarse tracking camera unit (11), the fine tracking camera unit (12) and the two-axis servo turntable unit (14) of the APT device; The digital image signal transmitted by the coarse tracking camera unit (11) or the fine tracking camera unit (12) is converted into a parallel digital signal by the image input unit (21) and then enters the field programmable logic array unit (31) for processing; The digital image that enters the Field Programmable Logic Array unit (31) is image information that needs to be processed in real time, and after the digital image is simplified and frame-picked, it is transmitted to other monitoring equipment through the image output unit (24); Image output unit (24) is Camera Link interface mode, VGA interface mode, LVDS differential output mode, 1394 interface mode, USB interface mode, serial output interface mode, LVTTL parallel output mode, PAL system or NTSC system; The other monitoring equipment described is a VGA monitor, a PAL/NTSC monitor, and the output mode selects digital signal output or analog signal output; After the centroid of the light spot is calculated by the field programmable logic array unit (31), the centroid data is output to the two-axis servo turntable unit (14) through the centroid data output unit (25); the centroid output unit (25) is RS485 serial mode, RS232 Serial mode, LVDS differential output mode or LVTTL output mode. 2. the real-time calculation spot centroid detection device of field programmable logic array as claimed in claim 1, is characterized in that, described: 1) Field programmable logic array unit (31), which stores software, and the structural unit corresponding to the software is composed of: clock management module (51), image interface module (52), self-adaptive threshold module (53), 3×3 window module (54), row and column counter module (55), spot judgment module (56), centroid calculation module (57), VGA display module (58) and miss output module (59); Described clock management module (51) is connected with VGA display module (58); Image interface module (52) and clock management module (51), adaptive threshold module (53), 3 * 3 window module (54), The row and column counter module (55) is connected with the VGA display module (58) respectively; the spot judgment module (56) is connected with the adaptive threshold module (53), the 3×3 window module (54) and the centroid calculation module (57) respectively; The centroid calculation module (57) is also connected respectively with the row and column counter module (55) and the miss output module (59); the VGA display module (58) is connected with the image output unit (24); the miss output module (59) is also connected with the centroid Data output unit (25) is connected; Described image interface module (52) is also connected with DS90CR287 unit (43), DS90LV048 unit (44) and DS90LV047 unit (45) of image input unit (21); 2) The field programmable logic array auxiliary device unit (32) is composed of a crystal oscillator unit (41) and an EPC2 unit (42); wherein, the crystal oscillator unit (41): is responsible for providing the field programmable logic array unit (31) with a reference Clock; EPC2 unit (42): it is a kind of EEPROM memory, after the whole system is powered on, the program of the field programmable logic array stored in it can be automatically transmitted to the field programmable logic array unit (31); 3) The image input unit (21) is composed of DS90CR287 unit (43), DS90LV048 unit (44), and DS90LV047 unit (45); wherein, the DS90CR287 unit (43) of the image input unit (21) is a chip DS90CR287; the image input The DS90LV048 unit (44) of the unit (21) is a chip DS90LV048; the DS90LV047 unit (45) of the image input unit (21) is a chip DS90LV047; 4) The image output unit (24) is a chip AL250: it can convert the parallel image data output by the field programmable logic array unit (31) into image data conforming to the VGA format, and can be directly connected to other VGA image display devices; 5) The centroid data output unit (25) is a chip MAX485: it can convert the serial miss data outputted by the field programmable logic array unit (31) into a device conforming to the RS485 transmission protocol by LVTTL, and serially output the miss data to Two-axis servo turntable unit (14). 3. the real-time calculation spot centroid detection device of Field Programmable Logic Array as claimed in claim 1, is characterized in that, the interface mode of described image input unit (21) is: VGA interface mode, LVDS differential output interface mode, 1394 interface mode, USB interface mode, serial output mode, LVTTL parallel output mode, PAL system or NTSC system; The interface mode of described image output unit (24) is: Camera Link interface mode, LVDS differential output interface mode, 1394 interface mode, USB interface mode, serial output mode, LVTTL parallel output mode, PAL system or NTSC system; The output mode of the centroid output unit (25) is RS232 serial output mode, LVDS differential output mode or LVTTL output mode.

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