CN201096890Y - Detection device for real time computation of centroid of onsite programmable logic array - Google Patents

Abstract

The utility model relates to a real-time calculating light spot centroid detection device of the field programmable logical array, which belongs to the photo-electric imaging and tracking technology field. The real-time calculating spot centroid detection device is composed of an image input unit (21), an image output unit (24), a centroid data output unit (25), a field programmable logical array unit (31) and a field programmable logical array auxiliary component unit (32); the light spot centroid data of one image can be calculated within scores of nanoseconds through the device, the bottleneck bandwidth limit of an APT system is transferred to a photo-electric imaging equipment, namely CCD camera or CMOS camera from an image processing equipment, thereby greatly improving the overall band width of the APT system. The computation speed is enhanced to 3000 to 10000000 images per second from 500 to 2000 images per second of the prior DSP embedded image process system; the equipment volume is reduced to 150 mm X 150 mm X 30 mm from original 200 mm X 300 mm X 30 mm to 300 mm X 500 mm X 800 mm; the power consumption is decreased to 0.5 w from original 0.8 w to 2.0 w; the component quantity is reduced to 15 from original 20 to 30.

Description

The detecting device for real-time computing facula mass center of field programmable logic array (FPLA)

Technical field

The utility model belongs to photoelectronic imaging tracking technique field, relates to the detecting device for real-time computing facula mass center of field programmable logic array (FPLA).

Background technology

In laser space communication system, the beacon laser of communicating pair needs at first the other side orientation to be caught, and accurately aims at the other side's fiber optic then, re-uses communication laser and communicates, and remain the accurate aligning of beacon beam to the other side in the process of communication.This process promptly is called catches (Acquisition), aligning (Pointing), tracking (Tracking), is called for short APT.(list of references: " technical research of free space optical communication ATP system core ", author Shao Bing etc., publication " piezoelectricity and acousto-optic ").

Fig. 1 is the structural representation of APT device.By thick tracking camera unit 11, smart camera unit 12, the image processing equipment unit 13 followed the tracks of, diaxon servo turntable unit 14 constitutes.

The thick camera unit 11 of following the tracks of is exported to image processing equipment unit 13 with image.Image processing equipment unit 13 is actually the device that calculates facula mass center, and it is industrial computer (PC), embedded small computing machine (PC104 machine), ARM embedded image disposal system or DSP embedded image disposal system.

Wherein, DSP embedded image disposal system is the comparatively desirable a kind of image processing apparatus of every comparatively speaking performance index.Fig. 2 is the DSP embedded image disposal system structural representation of APT device.Form by image input block 21, digital signal processor (DSP) unit 22, DSP additional device unit 23, image output unit 24 and barycenter data output unit 25.(list of references: PhD dissertation " design of embedded colored TV tracker system and realization ", author Gu Haijun, china academia periodical (CD version) e-magazine society) still, digital signal processor (DSP) unit 22 is the same with other device of image processing equipment unit 13, exists problems such as the computing degree is low, volume is big, power consumption is high, number of devices is numerous.

Summary of the invention

For there are problems such as arithmetic speed is low, volume is big, power consumption is high, number of devices is numerous in the DSP embedded image disposal system that overcomes the APT device, the utility model provides a kind of pick-up unit of the real-time computing facula mass center based on field programmable logic array (FPLA).

According to the manufacturing principle of field programmable logic array (FPLA) as can be known, this Flame Image Process account form is based on the pure hardware digital circuit basis, so have advantages such as real time high-speed, volume are little, low in energy consumption, multithreading.

As shown in Figure 3, the composition of the detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model has image input block 21, image output unit 24, barycenter data output unit 25 also have field programmable logic array (FPLA) unit 31, field programmable logic array (FPLA) additional device unit 32; Described field programmable logic array (FPLA) unit 31 respectively with image input block 21, image output unit 24, barycenter data output unit 25, field programmable logic array (FPLA) additional device unit 32 connects.

During use, a kind of detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model is connected with diaxon servo turntable unit 14 with the thick tracking camera unit 11 of APT device, the smart camera unit 12 of following the tracks of;

The dynamic duty process of a kind of detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model is as follows: by thick tracking camera unit 11 or smartly follow the tracks of the data image signal that camera unit 12 is sent out, convert to enter in the field programmable logic array (FPLA) unit 31 behind the parallel digital signal through image input block 21 and handle.Use hardware description language (VHDL, Verylog, AHDL all can) making software, and will be downloaded to behind this software translating in the field programmable logic array (FPLA) unit 31, this software is finished following technical functionality:

A) sequential of change input signal deposits among the FIFO and cushions;

B) digital picture of input is carried out initialization process, remove garbage signal, improve signal to noise ratio, obtain light spot image more easy to identify;

C) all pixel grey scales are differentiated, the shared pixel of identification hot spot obtains light spot shape information;

D) the shared pixel of hot spot is resolved, obtain the center-of-mass coordinate data;

E) send the center-of-mass coordinate data to diaxon servo turntable 14 by barycenter data output unit 25;

F) suitably select some consecutive image to export to miscellaneous equipment by visual output unit 24, other surveillance equipment can be VGA display, PAL/NTSC monitor, is used for manually monitoring and other purposes processing.

The digital picture that enters field programmable logic array (FPLA) unit 31 is to need the image information of processing in real time, this digital picture simplified to take out can send other surveillance equipment to by image output unit 24 after frame is handled, image output unit 24 can be Camera Link interface mode, VGA interface mode, the output of LVDS difference, 1394 interface modes, usb mode, serial output mode, LVTTL the walk abreast way of output, pal mode or TSC-system formula.Other surveillance equipment can be VGA display, PAL/NTSC monitor, is used for manually monitoring and other purposes processing.The way of output can be selected digital signal output or simulating signal output.

After calculating facula mass center by field programmable logic array (FPLA) unit 31, the barycenter data are exported to diaxon servo turntable unit 14 by barycenter data output unit 25.Barycenter data output unit 25 can be exported the barycenter data for which kind of mode no matter RS485 serial mode, RS232 serial mode, the LVDS difference way of output or the LVTTL way of output adopt, all will satisfy the requirement of input picture frame frequency, strictness is accomplished whenever to come piece image and is then exported one group of barycenter data.

The effect that the utility model is useful: the utility model has characteristics such as multithreading, high integration owing to adopted the digital circuit mode of pure hardware to carry out Digital Image Processing.The field programmable logic array (FPLA) device of this device can calculate the facula mass center data of piece image in tens nanoseconds, so that it is CCD camera or CMOS camera that the bottleneck bandwidth of APT system restriction has been transferred to photoelectronic imaging equipment by image processing equipment, thereby improved the overall bandwidth of APT system greatly.

Advantages such as the speed that the utlity model has is fast, volume is little, low in energy consumption, number of devices is few improve system reliability, have reduced cost.Computing velocity is brought up to per second 3000～10000000 width of cloth images by per second 500 width of cloth～2000 width of cloth images of the DSP embedded image disposal system of former utility model; Equipment volume is reduced to 150mm * 150mm * 30mm by original 200mm * 300mm * 30mm～300mm * 500mm * 800mm; Power consumption drops to 0.5w by original 0.8w～2.0w; Number of devices reduces to 15 by original 20～30.

Description of drawings

Fig. 1 is the structural representation of APT.

Fig. 2 is a DSP embedded image disposal system structural representation.

Fig. 3 is a kind of detecting device for real-time computing facula mass center structural representation based on field programmable logic array (FPLA) of the utility model.

The structural representation of Fig. 4 embodiment 1.

Fig. 5 software synoptic diagram.

Embodiment:

Embodiment 1

As shown in Figure 3, the composition of the detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model has image input block 21, image output unit 24, barycenter data output unit 25 also have field programmable logic array (FPLA) unit 31, field programmable logic array (FPLA) additional device unit 32; Described field programmable logic array (FPLA) unit 31 respectively with image input block 21, image output unit 24, barycenter data output unit 25, field programmable logic array (FPLA) additional device unit 32 connects.

During use, a kind of detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model is connected with diaxon servo turntable unit 14 with the thick tracking camera unit 11 of APT device, the smart camera unit 12 of following the tracks of.

Device shown in Figure 4 is one of specific embodiments of the detecting device for real-time computing facula mass center based on field programmable logic array (FPLA) of the present utility model as shown in Figure 3:

1) the field programmable logic array (FPLA) unit 31, use hardware description language (VHDL, Verylog or AHDL all can) making software, and will be downloaded in the field programmable logic array (FPLA) unit 31 behind this software translating.As shown in Figure 5, constituting of the structural unit corresponding: Clock management module 51, image interface module 52, adaptive threshold module 53,3 * 3 window modules 54, line count device module 55, hot spot judge module 56, centroid calculation module 57, VGA display module 58 and miss distance output module 59 with software;

Described Clock management module 51 is connected with VGA display module 58; Image interface module 52 is connected respectively with VGA display module 58 with Clock management module 51, adaptive threshold module 53,3 * 3 window modules 54, line count device module 55; Hot spot judge module 56 is connected respectively with centroid calculation module 57 with adaptive threshold module 53,3 * 3 window modules 54; Centroid calculation module 57 also is connected respectively with miss distance output module 59 with line count device module 55; VGA display module 58 is connected with image output unit 24; Miss distance output module 59 also is connected with barycenter data output unit 25; Described image interface module 52 also is connected with DS90CR287 unit 43, DS90LV048 unit 44 and the DS90LV0475 unit 45 of image input block 21;

(1) the Clock management module 51: be responsible for the reference clock of crystal oscillator unit 41 inputs of field programmable logic array (FPLA) additional device unit 32 is handled, and the signal behind frequency multiplication and the frequency division is sent to other module make the benchmark drive clock.

(2) the image interface module 52: the image parallel data of input can be handled, and therefrom extraction place field effectively, row effectively, signal such as pixel is effective, give the subsequent treatment module respectively with view data.

(3) the adaptive threshold module 53: pixel grey scale value of averaging of a last field picture can be calculated, thereby obtain the comparison gray-scale value of this field picture pixel.

(4) 3 * 3 window modules 54: image pixel is carried out medium filtering handle, the noise pixel in the image can be removed like this, thereby obtain image information more easy to identify.

(5) line count device module 55: for the centroid calculation module provides some locations of pixels information, promptly the place line number and the columns of pixel are counted, and offered the centroid calculation module.

(6) the hot spot judge module 56: obtain relatively to compare with all pixels that will be worth behind the gray-scale value with this field picture from the adaptive threshold module, thereby determine which pixel of this field picture is the pixel that comprises facula information.

(7) the centroid calculation module 57: use the pixel data that comprises facula information to calculate, and calculate facula mass center according to following formula:

$\stackrel{\‾}{x}=\frac{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}i(G_{\mathrm{ij}}-T)}{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}(G_{\mathrm{ij}}-T)}$

$\stackrel{\‾}{y}=\frac{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}j(G_{\mathrm{ij}}-T)}{\underset{i_0}{\overset{i_f}{\mathrm{\Σ}}}\underset{j_0}{\overset{j_f}{\mathrm{\Σ}}}(G_{\mathrm{ij}}-T)}$

Wherein, T is a pixel threshold value relatively, G _IjBe the gray-scale value of the shared pixel of hot spot, x and y are respectively the ranks value (position coordinates just) of facula mass center.

(8) the VGA display module 58: use the parallel data form to send AL250 unit 24 to image.

(9) the miss distance output module 59: the data and the picture centre coordinate that are sent by the centroid calculation module compare, thereby the distance that draws the centroid distance center is the miss distance data, sends these miss distance data to barycenter output unit 25 by the UART serial mode.

2) as shown in Figure 4, field programmable logic array (FPLA) additional device unit 32 is made of jointly crystal oscillator unit 41, EPC2 unit 42; Crystal oscillator unit 41: be responsible for providing reference clock with field programmable logic array (FPLA) unit 31; EPC2 unit 42: be a kind of eeprom memory, after total system powers on, can send the Automatic Program of the field programmable logic array (FPLA) preserved in it to field programmable logic array (FPLA) unit 31.

3) as shown in Figure 4, image input block 21 is made of jointly DS90CR287 unit 43, DS90LV048 unit 44, DS90LV047 unit 45; The DS90CR287 unit 43 of image input block 21 is chip DS90CR288: be a kind of Camera Link transport protocol conversion device, the LVDS level formal transformation that meets the CameraLink transmission mode can be become the parallel data of 28 road LVTTL level forms; The DS90LV048 unit 44 of image input block 21 is chip DS90LV048: be a kind of Camera Link transport protocol conversion device, the LVDS level formal transformation that meets Camera Link transmission mode can be become the parallel data of 4 road LVTTL level forms; The DS90LV047 unit 45 of image input block 21 is chip DS90LV047: be a kind of Camera Link transport protocol conversion device, the parallel data of 4 road LVTTL level forms can be converted to the LVDS level form that meets Camera Link transmission mode.

4) image output unit 24 is chip AL250: the parallel image data-switching of programmable logic array unit 31 outputs can be become meet the view data of VGA form, can directly connect other VGA image display.

5) barycenter data output unit 25 is chip MAX485: can convert the serial miss distance data of unit 31 outputs to meet the RS485 host-host protocol device by LVTTL, be about to the miss distance data serial and export to diaxon servo turntable unit 14.

Need to prove that described image input block 21 can also be VGA interface mode, the output of LVDS difference, 1394 interface modes, usb mode, serial output mode, the LVTTL parallel way of output, pal mode or TSC-system formula except CameraLink interface mode that this preferred embodiment proposed is; Field programmable logic array (FPLA) unit 31 is existing commodity; Image output unit 24 can also be Camera Link interface mode, the output of LVDS difference, 1394 interface modes, usb mode, serial output mode, the LVTTL parallel way of output, pal mode or TSC-system formula except the VGA mode that this preferred embodiment proposed; Barycenter output unit 25 can also be RS232 serial mode, the LVDS difference way of output or the LVTTL way of output except the RS485 serial mode that this preferred embodiment proposed, no matter adopt which kind of mode to export the barycenter data, all will satisfy the requirement of input picture frame frequency, strictness is accomplished whenever to come piece image and is then exported one group of barycenter data.

Claims (3)

1. the detecting device for real-time computing facula mass center of field programmable logic array (FPLA), the composition of this device has image input block (21), image output unit (24), barycenter data output unit (25), it is characterized in that also having field programmable logic array (FPLA) (31), field programmable logic array (FPLA) additional device unit (32); Described field programmable logic array (FPLA) (31) respectively with image input block (21), image output unit (24), barycenter data output unit (25), field programmable logic array (FPLA) additional device unit (32) connects;

The detecting device for real-time computing facula mass center of described field programmable logic array (FPLA) is connected with diaxon servo turntable unit (14) with the thick tracking camera unit (11) of APT device, the smart camera unit (12) of following the tracks of;

By thick tracking camera unit (11) or smart follow the tracks of the data image signal that camera unit (12) is sent out, convert to enter in the field programmable logic array (FPLA) unit (31) behind the parallel digital signal through image input block (21) and handle; The digital picture that enters field programmable logic array (FPLA) unit (31) is to need the image information of processing in real time, this digital picture is simplified to take out sending other surveillance equipment to by image output unit (24) after frame is handled;

Image output unit (24) is Camera Link interface mode, VGA interface mode, the LVDS difference way of output, 1394 interface modes, usb mode, serial output interface mode, the LVTTL parallel way of output, pal mode or TSC-system formula;

Described other surveillance equipment is VGA display, PAL/NTSC monitor, and the way of output is selected digital signal output or simulating signal output;

Behind field programmable logic array (FPLA) unit (31) clearing glossing up barycenter, the barycenter data are exported to diaxon servo turntable unit (14) by barycenter data output unit (25); Barycenter output unit (25) is RS485 serial mode, RS232 serial mode, the LVDS difference way of output or the LVTTL way of output.

2. the detecting device for real-time computing facula mass center of field programmable logic array (FPLA) as claimed in claim 1 is characterized in that, and is described:

1) field programmable logic array (FPLA) unit (31), store software, the constituting of the structural unit corresponding: Clock management module (51), image interface module (52), adaptive threshold module (53), 3 * 3 window modules (54), line count device module (55), hot spot judge module (56), centroid calculation module (57), VGA display module (58) and miss distance output module (59) with this software;

Described Clock management module (51) is connected with VGA display module (58); Image interface module (52) is connected respectively with Clock management module (51), adaptive threshold module (53), 3 * 3 window modules (54), line count device module (55) and VGA display module (58); Hot spot judge module (56) is connected respectively with adaptive threshold module (53), 3 * 3 window modules (54) and centroid calculation module (57); Centroid calculation module (57) also is connected respectively with miss distance output module (59) with line count device module (55); VGA display module (58) is connected with image output unit (24); Miss distance output module (59) also is connected with barycenter data output unit (25); Described image interface module (52) also is connected with DS90LV047 unit (45) with DS90CR287 unit (43), DS90LV048 unit (44) of image input block (21);

2) field programmable logic array (FPLA) additional device unit (32) are made of jointly crystal oscillator unit (41), EPC2 unit (42); Wherein, crystal oscillator unit (41): be responsible for providing reference clock with field programmable logic array (FPLA) unit (31); EPC2 unit (42): be a kind of eeprom memory, after total system powers on, can send the Automatic Program of the field programmable logic array (FPLA) preserved in it to field programmable logic array (FPLA) unit (31);

3) image input block (21) is made of jointly DS90CR287 unit (43), DS90LV048 unit (44), DS90LV047 unit (45); Wherein, the DS90CR287 unit (43) of image input block (21) is chip DS90CR287; The DS90LV048 unit (44) of image input block (21) is chip DS90LV048; The DS90LV047 unit (45) of image input block (21) is chip DS90LV047;

4) image output unit (24) is chip AL250: the parallel image data-switching of field programmable logic array (FPLA) unit (31) output can be become meet the view data of VGA form, can directly connect other VGA image display;

5) barycenter data output unit (25) is chip MAX485: can convert the serial miss distance data of field programmable logic array (FPLA) unit (31) output to meet the RS485 host-host protocol device by LVTTL, be about to the miss distance data serial and export to diaxon servo turntable unit (14).

3. the detecting device for real-time computing facula mass center of field programmable logic array (FPLA) as claimed in claim 1, it is characterized in that the interface mode of described image input block (21) is: VGA interface mode, LVDS difference output interface mode, 1394 interface modes, usb mode, serial output mode, the LVTTL parallel way of output, pal mode or TSC-system formula;

The interface mode of described image output unit (24) is: Camera Link interface mode, LVDS difference output interface mode, 1394 interface modes, usb mode, serial output mode, the LVTTL parallel way of output, pal mode or TSC-system formula;

The way of output of described barycenter output unit (25) is RS232 serial output mode, the LVDS difference way of output or the LVTTL way of output.

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