CN105635648A - Video real-time edge detection system - Google Patents

Abstract

The present invention relates to a video detection system. The video detection system on the basis of FPGA comprises a master control FPGA module, a camera, an SDRAM module and a VGA liquid crystal display; the master control FPGA module is connected with the camera, the SDRAM module and the VGA liquid crystal display; the master control FPGA module includes an I2C configuration module, a video data acquisition module, an SDRAM control module, an Sobel edge detection module and a VGA control module; the FPGA is configured to initiate the camera through the I2C bus and then convert the collected data to video data with a RG565 standard through the video data acquisition module, and image data is subjected to buffering in the SDRAM module through an IFI_IN module. The video real-time edge detection system is fast in speed and high in precision, and is applicable to the fields of target identification, target tracking, intelligent video monitoring and the like.

Description

The real-time edge inspection system of video

Technical field

The present invention relates to video detection system, particularly relate to a kind of real-time edge inspection system of video.

Background technology

Along with the development of science and technology, video acquisition system is increasingly widely used in every field, as sports show, video conference, guided missile TV guidance etc. And image border is one of basic feature of image, wherein containing critically important boundary information, these information are the bases of graphical analysis, target recognition. Controlling in application in transport information, rim detection has been the important step in the technology such as Car license recognition, vehicle flowrate monitoring, self-navigation. By effective rim detection, it is possible to be greatly simplified the analytical work to image information of the successive image processing procedure. For the rim detection of video image, realize the restriction owing to being subject to system processing speed according to software mode, it is easy to disconnected frame phenomenon occurs, will be a very big defect under when this is for requiring to process in real time. Hardware realizes mainly to be had based on special chip, based on DSP with based on three kinds of processing modes of FPGA. The exploitation of early stage product it is not appropriate for based on special chip mode. Based on the mode of DSP in arithmetic speed, data throughout etc. restricted.

Summary of the invention

The technique effect of the present invention can overcome drawbacks described above, it is provided that a kind of real-time edge inspection system of the video based on FPGA, it utilizes the parallel organization that FPGA is good, makes computation rate be greatly improved, and has reached the requirement of real-time of system.

For achieving the above object, the present invention adopts the following technical scheme that it includes master control FPGA module, photographic head, SDRAM module, VGA liquid crystal display, and master control FPGA module is connected with photographic head, SDRAM module, VGA liquid crystal display respectively; Wherein master control FPGA module includes I²C configures module, video data acquiring module, SDRAM control module, Sobel edge edge detection module and VGA and controls module, and FPGA first passes through I²C bus completes the initialization to photographic head, then the data collected are converted to by video data acquiring module the video data of RGB565 standard, view data is cushioned in SDRAM module by FIFO_IN module, Sobel edge edge detection module reads data by FIFO_OUT module and processes, and the row of VGA control module control USB interface synchronizes and field sync signal completes VGA and shows.

Master control FPGA module adopts EP4CE115F29CN7 model.

Photographic head adopts OV7670 model.

The present invention devises a real-time edge inspection system of the video based on FPGA, utilizes the parallel organization that FPGA is good, makes computation rate be greatly improved, has reached the requirement of real-time of system. Achieve the colored display on liquid crystal display screen of the VGA resolution video, gray scale shows, edge-detected image shows. This system speed is fast, and precision is high, it is possible to be well applied in the fields such as target recognition, target following, intelligent video monitoring.

Accompanying drawing explanation

Fig. 1 is overall system architecture block diagram;

Fig. 2 is I2C transmission time sequence figure;

Fig. 3 is data sampling time sequence analogous diagram;

Fig. 4 is Sobel gradient operator;

Fig. 5 is convolution hardware structure diagram;

Fig. 6 is that Signaltap II captures VGA sequential chart.

Detailed description of the invention

The technical problem to be solved is to propose the design of a kind of real-time edge inspection system of the video based on FPGA.

One, the master-plan of system

Native system is based on the CycloneIV series EP4CE115F29CN7 master control FPGA of a piece of altera corp, and the overall structure block diagram of system is as shown in Figure 1. Specifically include that photographic head I2C configures module, video data acquiring module, SDRAM control module, Sobel edge edge detection module and VGA and controls module. FPGA first passes through I2C bus and completes the initialization to OV7670, then the data collected are converted to by video data acquiring module the video data of RGB565 standard, view data is cushioned in SDRAM by FIFO_IN module, Sobel edge edge detection module reads data by FIFO_OUT module and processes, and the row of VGA control module control USB interface synchronizes and field sync signal completes VGA and shows.

Two, video acquisition and rim detection submodule

I²C configures module

Native system adopts this cmos sensor of OV7670 of OmniVision company, provides video signal for system. By SCCB (SerialCameraControlBus) bus, totally 201 control depositors of OV7670 are configured, change the output form of data, video resolution, transmission means, adjust the white balance of image, saturation, colourity, gamma curve etc. The SCCB bus of two-wire system and I²C bus is identical, is all two-way two-wire system synchronous serial bus. I²C transmission time sequence is as in figure 2 it is shown, I²C_SCLK is equivalent to SIOC, I in SCCB²C_SDAT is equivalent to the SIOD in SCCB, module transmits 24 bit data every time, and first 8 is from device address (0x42 represents and writes depositor, 0x43 representative degree depositor), middle 8 is from device register address, and last 8 is the data that depositor is configured.

Video data acquiring module

Video data acquiring module, coordinates the row of CMOS camera OV7670, field sync signal acquisition of image data mainly by FPGA. First passing through configuration control register, controlling OV7670 output video data is RGB565 form. Because OV7670 data bit width is 8,2, front and back, 8 bit data collected mainly are merged into 16 bit data by video data acquiring module, to facilitate the process of data buffer memory in SDRAM and subsequent module. It is illustrated in figure 3 data acquisition ModelSim time stimulatiom figure.

SDRAM controls module

SDRAM module is mainly made up of FIFO and off-chip SDRAM two parts, because it is different that the data rate that CMOS camera OV7670 gathers and SDRAM read and write speed, in order to mate the module of the two different transmission rates, a FIFO memory wherein must be added. Wherein FIFO need not describe separately through language and obtain, it is only necessary to obtained by the configuration of MegaWizard instrument. The SDRAM used in the design is two 64M byte SDRAM on DE2-115 development board, and wherein each SDRAM comprises again 4 BANK. SDRAM row address line and column address conductor are the address bus of multiplexing 13, when read-write, first to activate certain BANK, then latch row address, finally latch column address when read write command is effective. The highest read-write speed of SDRAM can reach 166MHz, and in native system, application is 100MHz, simultaneously each rising edge clock read-write 16bit data again, and therefore SDRAM can realize the seamless buffering work of data completely.

Sobel edge edge detection module

Image border is the region that in piece image, grey scale change is more violent, calculates the gradient magnitude in each region in gray level image and can be used to the marginal information of process decision chart picture. If the brightness of image be f (x, y), then gradient can be defined as follows:

$\▿\▿f(x,y)={[\∂f(x,y)/\∂x,\∂f(x,y)/\∂y]}^T={[f_x(x,y),f_y(x,y)]}^T...\left(1\right)$

Amplitude is: | and f (x, y) |=[f_x ²(x, y), f_y ²(x,y)]^1/2����������������(2)

Direction is: ��=arctan [f_y(x,y)/f_x(x,y)]������������������������(3)

The detection of Sobel edge edge is based on the detection of gradient, and it utilizes Sobel operator Gx and Gy as shown in Figure 4, does convolution algorithm with brightness data in the Image neighborhood of 3 �� 3, and expression formula is as follows:

$\begin{array}{c}{f}_x(x,y)=f(x-1,y+1)+2f(x,y+1)+f(x+1,y+1)-f(x-1,y-1)\\ -2f(x,y-1)-f(x+1,y-1)\end{array}\·\·\·\left(4\right)$

$\begin{array}{c}{f}_x(x,y)=f(x+1,y-1)+2f(x+1,y)+f(x+1,y+1)-f(x-1,y-1)\\ -2f(x-1,y)-f(x-1,y+1)\end{array}\·\·\·\left(5\right)$

Rim detection is done with hardware, owing to being real-time process, in SDRAM, the data of buffer memory are a two field picture in continuous videos image, and video data is also ceaselessly transmitted through from photographic head, therefore a two-dimentional data array cannot first be set up as software processes, pipeline system thus must be adopted to carry out computing, and the number of pixels of pipeline number and every time participation computing is equal, just altogether needs 9 streamlines here. For this specialized designs, 3Line_Buffer carrys out the computing of perfect (4) and formula (5), article 3, Line_Buffer is completed by the altshift_tab of configuration in MegaWizard, altshift_tab is actually a shift register, because video resolution is 640 �� 480 pixels, so every Line_Buffer is really rearward displacement one full line, namely 640 pixel values. Thus being equal in the data video image in 3 Line_Buffer the three row view data adjoined mutually, these 3 row data do convolution with Sobel operator again. It is illustrated in figure 5 convolution algorithm hardware structure diagram, wherein P₉��P₁For pixel data, X₉��X₁For Sobel gradient operator. Multiplication and parallel addition part have MegaWizard altmult_add and parallel_add configured to complete respectively.

VGA display module

The display of VGA display adopts progressive scan, from screen upper left side, from left to right, scans from top to bottom. The reality of every a line is subject to line synchronising signal (HREF) and controls, and the signal of each frame is subject to field sync signal (VSYNC) and controls. In native system, CMOS camera gathers image resolution ratio is 640 �� 480 pixels, the industrial standard of VGA (640 �� 480) is row scanning: Ta (lock-out pulse)=96, Tb (horizontal blanking back porch)=40, Tc=8, Td (effective sequential)=640, Te=80, Tf (horizontal blanking crop)=8, Tg (line period)=800; Field scanning: Ta (lock-out pulse)=2, Tb (field blanking back porch)=25, Tc=8, Td (has

Effect sequential)=480, Te=8, Tf (field blanking crop)=2, Tg (field duration)=525. Fig. 6 is the VGA sequential chart captured by SignalTapII, and wherein last column data are when the line number statistics shown by former frame video.

Claims (3)

1. the real-time edge inspection system of the video based on FPGA, it is characterised in that including master control FPGA module, photographic head, SDRAM module, VGA liquid crystal display, master control FPGA module is connected with photographic head, SDRAM module, VGA liquid crystal display respectively; Wherein master control FPGA module includes I²C configures module, video data acquiring module, SDRAM control module, Sobel edge edge detection module and VGA and controls module, and FPGA first passes through I²C bus completes the initialization to photographic head, then the data collected are converted to by video data acquiring module the video data of RGB565 standard, view data is cushioned in SDRAM module by FIFO_IN module, Sobel edge edge detection module reads data by FIFO_OUT module and processes, and the row of VGA control module control USB interface synchronizes and field sync signal completes VGA and shows.

2. the real-time edge inspection system of the video based on FPGA according to claim 1, it is characterised in that master control FPGA module adopts EP4CE115F29CN7 model.

3. the real-time edge inspection system of the video based on FPGA according to claim 1, it is characterised in that photographic head adopts OV7670 model.