CN205388775U - Adopt parallel data processing's figure processing system - Google Patents
Adopt parallel data processing's figure processing system Download PDFInfo
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- CN205388775U CN205388775U CN201620173762.6U CN201620173762U CN205388775U CN 205388775 U CN205388775 U CN 205388775U CN 201620173762 U CN201620173762 U CN 201620173762U CN 205388775 U CN205388775 U CN 205388775U
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Abstract
The utility model discloses an adopt parallel data processing's figure processing system, including a processing unit, the 2nd processing unit, the 3rd processing unit, fourth processing unit, image acquisition device, the image acquisition device passes through compact PCI bus interface and connects a processing unit the 2nd processing unit with the 3rd processing unit, a processing unit the 2nd processing unit with the 3rd processing unit all connects fourth processing unit, a processing unit disposes first predetermined image processing program, the 2nd processing unit disposes the predetermined image processing program of second, the 3rd processing unit disposes the predetermined image processing program of third, it is right that fourth processing unit is used for first result the second result with the third result is handled, obtains the fourth result, and will the fourth result is exported. Four image processing unit collaborative works are passed through to this patent, have improved image processor's processing performance and treatment effeciency.
Description
Technical field
This utility model relates to image processing field, particularly to a kind of graphic system adopting parallel data to process.
Background technology
Development along with microelectric technique, the particularly appearance of large scale integrated circuit and digital signal processing chip, the speed making signal processing constantly increases, means are also more flexible, modern photodetection is followed the tracks of system and is just developed towards the direction of artificial intelligence, and the picture frame frequency of the designing requirement detection of system is higher on the one hand, visual field occasion background bigger, that be suitable for is increasingly complex changeable；Another aspect is increasingly extensive along with infrared imagery technique application, the requirement of infrared image processing technology real-time is also more and more higher, require that again Video processing has sufficiently high processing speed and complex applicable track algorithm, to guarantee the precision followed the tracks of, identify.
But, in field of image recognition, along with image processing algorithm becomes increasingly complex, it is necessary to same image is carried out repeatedly different algorithm process, then carries out the work such as follow-up synthesis, this is accomplished by processor better parallel running performance, existing image processor generally all adopts bi-processor architecture, and the computing of independent algorithm is responsible for by a processor, and the synthesis after computing is responsible for by another processor, but this processing mode is inefficient, process performance is poor.
Utility model content
This utility model is in that to overcome the above-mentioned deficiency of prior art, it is provided that the graphic system that the employing parallel data that a kind for the treatment of effeciency is high, process performance is high processes.
In order to realize above-mentioned utility model purpose, the technical solution adopted in the utility model is:
A kind of graphic system adopting parallel data to process, including the first processing unit, the second processing unit, the 3rd processing unit, fourth processing unit, image collecting device；
Described image collecting device connects described first processing unit, described second processing unit and described 3rd processing unit by CompactPCI EBI, for the target image information collected is separately sent to described first processing unit, described second processing unit and the 3rd processing unit；
nullDescribed first processing unit、Described second processing unit and described 3rd processing unit are all connected with described fourth processing unit，Described first processing unit is configured with the first predetermined image and processes program，The first result is obtained for described target image information being carried out process according to described first predetermined image process program，And the first result is sent to described fourth processing unit，Described second processing unit is configured with the second predetermined image and processes program，The second result is obtained for described target image information being carried out process according to described second predetermined image process program，And the second result is sent to described fourth processing unit，Described 3rd processing unit is configured with the 3rd predetermined image and processes program，The 3rd result is obtained for described target image information being carried out process according to described 3rd predetermined image process program，And the 3rd result is sent to described fourth processing unit；
Described fourth processing unit, for described first result, described second result are processed with described 3rd result, obtains fourth process result, and described fourth process result is exported.
Further, described first processing unit, the second processing unit, the 3rd processing unit and fourth processing unit all include a fpga chip, two dsp chips, described fpga chip connects said two dsp chip, and the fpga chip of described first processing unit, the fpga chip of described second processing unit and the fpga chip of described 3rd processing unit are all connected with the fpga chip of the connection of described CompactPCI EBI and described fourth processing unit respectively.
Further, described image collector is set to thermal camera.
Further, the model of described FPGA is XC5VLX50.
Further, the model of described DSP is TMS320C6414.
Further, the model of described CompactPCI Bus Interface Chip is PCI9054.
Compared with prior art, the beneficial effects of the utility model
A kind of graphic system adopting parallel data to process of the present utility model is by adopting four graphics processing units, wherein three graphics processing units carry out preliminary process, another one graphics processing unit is reprocessed according to the result of other three graphics processing units, obtain final result, by four graphics processing unit collaborative works, improve process performance and the treatment effeciency of image processor.
Accompanying drawing explanation
Fig. 1 is a kind of graphic system module frame chart adopting parallel data to process shown in an embodiment of the present utility model.
Fig. 2 is a kind of graphic system structure chart adopting parallel data to process in an embodiment of the present utility model.
Detailed description of the invention
Below in conjunction with detailed description of the invention, this utility model is described in further detail.But this should not being interpreted as, the scope of the above-mentioned theme of this utility model is only limitted to below example, and all technology realized based on this utility model content belong to scope of the present utility model.
Embodiment 1:
Fig. 1 is a kind of graphic system module frame chart adopting parallel data to process shown in an embodiment of the present utility model, including the first processing unit, the second processing unit, the 3rd processing unit, fourth processing unit, image collecting device；
Described image collecting device connects described first processing unit, described second processing unit and described 3rd processing unit by CompactPCI EBI, for the target image information collected is separately sent to described first processing unit, described second processing unit and the 3rd processing unit；
nullDescribed first processing unit、Described second processing unit and described 3rd processing unit are all connected with described fourth processing unit，Described first processing unit is configured with the first predetermined image and processes program，The first result is obtained for described target image information being carried out process according to described first predetermined image process program，And the first result is sent to described fourth processing unit，Described second processing unit is configured with the second predetermined image and processes program，The second result is obtained for described target image information being carried out process according to described second predetermined image process program，And the second result is sent to described fourth processing unit，Described 3rd processing unit is configured with the 3rd predetermined image and processes program，The 3rd result is obtained for described target image information being carried out process according to described 3rd predetermined image process program，And the 3rd result is sent to described fourth processing unit；
Described fourth processing unit, for described first result, described second result are processed with described 3rd result, obtains fourth process result, and described fourth process result is exported.
Concrete, described first predetermined image processes program, the second predetermined image processes program, the 3rd predetermined image processes program and is prior art, and described fourth processing unit is also processed by program, and this program falls within prior art, does not repeat them here.
In a specific embodiment, referring to Fig. 2, described first processing unit, the second processing unit, the 3rd processing unit and fourth processing unit all include a fpga chip, two dsp chips, described fpga chip connects said two dsp chip, and the fpga chip of described first processing unit, the fpga chip of described second processing unit and the fpga chip of described 3rd processing unit are all connected with the fpga chip of the connection of described CompactPCI EBI and described fourth processing unit respectively
Concrete, described image collector is set to thermal camera.
Concrete, the model of described FPGA is XC5VLX50.
Concrete, the model of described DSP is TMS320C6414.
Concrete, the model of described CompactPCI Bus Interface Chip is PCI9054.
A kind of graphic system adopting parallel data to process of the present utility model is by adopting four graphics processing units, wherein three graphics processing units carry out preliminary process, another one graphics processing unit is reprocessed according to the result of other three graphics processing units, obtain final result, by four graphics processing unit collaborative works, improve process performance and the treatment effeciency of image processor.
Above in conjunction with accompanying drawing, detailed description of the invention of the present utility model is described in detail, but this utility model is not restricted to above-mentioned embodiment, without departing from the spirit and scope situation of claims hereof, those skilled in the art may be made that various amendment or remodeling.
Claims (6)
1. the graphic system adopting parallel data to process, it is characterised in that include the first processing unit, the second processing unit, the 3rd processing unit, fourth processing unit, image collecting device；
Described image collecting device connects described first processing unit, described second processing unit and described 3rd processing unit by CompactPCI EBI, for the target image information collected is separately sent to described first processing unit, described second processing unit and the 3rd processing unit；
nullDescribed first processing unit、Described second processing unit and described 3rd processing unit are all connected with described fourth processing unit，Described first processing unit is configured with the first predetermined image and processes program，The first result is obtained for described target image information being carried out process according to described first predetermined image process program，And the first result is sent to described fourth processing unit，Described second processing unit is configured with the second predetermined image and processes program，The second result is obtained for described target image information being carried out process according to described second predetermined image process program，And the second result is sent to described fourth processing unit，Described 3rd processing unit is configured with the 3rd predetermined image and processes program，The 3rd result is obtained for described target image information being carried out process according to described 3rd predetermined image process program，And the 3rd result is sent to described fourth processing unit；
Described fourth processing unit, for described first result, described second result are processed with described 3rd result, obtains fourth process result, and described fourth process result is exported.
2. a kind of graphic system adopting parallel data to process according to claim 1, it is characterized in that, described first processing unit, the second processing unit, the 3rd processing unit and fourth processing unit all include a fpga chip, two dsp chips, described fpga chip connects said two dsp chip, and the fpga chip of described first processing unit, the fpga chip of described second processing unit and the fpga chip of described 3rd processing unit are all connected with the fpga chip of the connection of described CompactPCI EBI and described fourth processing unit respectively.
3. a kind of graphic system adopting parallel data to process according to claim 2, it is characterised in that described image collector is set to thermal camera.
4. a kind of graphic system adopting parallel data to process according to claim 2, it is characterised in that the model of described FPGA is XC5VLX50.
5. a kind of graphic system adopting parallel data to process according to claim 2, it is characterised in that the model of described DSP is TMS320C6414.
6. a kind of graphic system adopting parallel data to process according to claim 2, it is characterised in that the model of described CompactPCI Bus Interface Chip is PCI9054.
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| CN201620173762.6U CN205388775U (en) | 2016-03-07 | 2016-03-07 | Adopt parallel data processing's figure processing system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111861852A (en) * | 2019-04-30 | 2020-10-30 | 百度时代网络技术（北京）有限公司 | Method and device for processing image and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111861852A (en) * | 2019-04-30 | 2020-10-30 | 百度时代网络技术（北京）有限公司 | Method and device for processing image and electronic equipment |
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