CN101548376B - 具有多个逻辑元件的一次性可编程逻辑位 - Google Patents
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- 230000015654 memory Effects 0.000 claims abstract description 165
- 238000000034 method Methods 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000006870 function Effects 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 206010061307 Neck deformity Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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Abstract
一种具有逻辑位的存储器单元,所述逻辑位具有提供第一一次性可编程(OTP)存储器元件输出的第一OTP存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。逻辑运算器耦合到所述第一OTP存储器元件输出和所述第二OTP存储器元件输出,且提供所述存储器单元的二进制存储器输出。在特定实施例中,所述第一OTP存储器元件是与所述第二OTP存储器元件不同类型的OTP存储器。
Description
技术领域
本发明大体上涉及集成电路,且更确切地说,涉及并入有一次性可编程逻辑存储器的集成电路。
背景技术
一次性可编程(OTP)存储器元件用于集成电路(IC)中以提供非易失性存储器(NVM)。当IC断开时,NVM中的数据不会丢失。举例来说,NVM允许IC制造商将批号和安全数据存储在IC上,且可用于许多其它应用。一般称为熔丝和反熔丝的装置是OTP存储器元件的实例。
其它类型的装置(例如,快闪存储器)也用于提供IC中的NVM;然而,将快闪存储器并入CMOS IC中添加了大量成本,因为通常需要额外的处理步骤。存在许多类型的熔丝,例如多晶硅熔丝、金属熔丝、触点熔丝和通道熔丝(via fuse),其与标准的CMOS处理兼容。然而,与类似大小的快闪存储器相比,高密度OTP存储器通常较不可靠且具有较低的编程良率。因此,需要以更好的可靠性和良率提供OTP存储器元件。
发明内容
一种具有逻辑位的存储器单元,所述逻辑位具有提供第一一次性可编程(OTP)存储器元件输出的第一OTP存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。逻辑运算器耦合到所述第一OTP存储器元件输出和所述第二OTP存储器元件输出,且提供所述存储器单元的存储器输出。在特定实施例中,所述第一OTP存储器元件是与所述第二OTP存储器元件不同类型的OTP存储器。
附图说明
图1是根据本发明的一实施例具有存储器元件的IC的图。
图2是根据本发明的一实施例的存储器单元的电路图。
图3是根据一实施例具有两种不同类型OTP装置的存储器元件的平面图。
图4展示根据一实施例用于OTP类型逻辑位的编程条件。
图5是根据一实施例的FPGA的平面图。
图6是根据本发明的一实施例操作存储器单元的方法的流程图。
具体实施方式
图1是根据本发明的一实施例具有逻辑位102的IC 100的图。逻辑位102是存储器单元104的一部分,其在输出106处提供一数据。所述数据例如是二进制“1”或“0”逻辑值,且通常由IC的其它电路(未图示)读取。OTP存储器领域的技术人员熟悉存储器单元104的额外部分(例如,读出放大器和锁存器(见图2)),且出于说明的简明和清楚起见而将其省略。
逻辑位102具有两个OTP存储器元件108、110,例如两个熔丝。在特定实施例中,第一OTP存储器元件108是第一类型的熔丝,且第二OTP存储器元件110是第二类型的熔丝。举例来说,第一OTP存储器元件是基于多晶硅的熔丝(“多晶硅熔丝”),且第二OTP存储器元件是薄膜金属熔丝,或第一OTP存储器元件是窄多晶硅熔丝,且第二OTP存储器元件是宽多晶硅熔丝。术语熔丝的“类型”用于表示第一类型的OTP存储器元件有意不同于第二类型的元件。在替代实施例中,第一OTP存储器元件是第一类型的熔丝,且第二OTP存储器元件是与第一类型的熔丝相同类型的熔丝。尽管在单个逻辑位中提供两个OTP存储器元件会消耗IC芯片的较多面积,但所得NVM的改进的良率和可靠性使得具有冗余OTP存储器元件的逻辑单元是合意的。
一般来说,不同类型的熔丝在编程过程期间以不同方式编程。在给定编程过程中(例如,在约3.3V的编程电压下将10mA的电流施加到熔丝并持续约500微秒到约1200微秒),熔丝元件从相对低电阻条件(通常约100欧姆到约300欧姆)转换为相对高电阻条件(通常约10千欧姆到大于约100兆欧姆)。需要最终(经编程的)电阻与初始(未编程的)电阻充分不同,以容易地在经编程条件与未编程条件之间进行区分,当熔丝用作存储器元件时,所述经编程条件与未编程条件表示不同的逻辑状态。存储器阵列中的熔丝元件将具有未编程电阻和经编程电阻两者的分布,其源自制造工艺中和编程过程中的物理变化。即,熔丝链接将具有将影响初始和最终电阻以及可编程性的宽度、厚度和传导性上的轻微变化。甚至来自熔丝链接的热耗散也可将向经编程电阻添加变化。通常针对一种类型的熔丝优化编程过程,但过程变化可能影响编程结果(最终的电阻率分布(读出电流分布)和良率)。举例来说,较弱编程的熔丝(例如,具有约1千欧姆的编程电阻的熔丝)可能通过编程验证,但随着时间变得更具传导性,从而导致可靠性故障。在单个逻辑位102中提供两个OTP存储器元件108、110改进了基于OTP的芯片上存储器的良率(尤其是编程良率)和可靠性。虽然在一逻辑位中使用相同类型的OTP存储器元件获得优点,但在单个逻辑位中使用两种不同类型的OTP存储器元件尤其合意,因为此布置为制造工艺和编程过程两者提供更宽的裕度。
将OTP存储器元件108和110相应的输出109和111提供到逻辑运算器(“门”)112,其在此实例中是OR门(或门)。逻辑运算器112提供存储器单元104的逻辑输出106。举例来说,如果OTP存储器元件108和110中的任一个被编程到逻辑“1”状态,那么存储器单元(输出106)将指示存储器单元104的逻辑值“1”。在许多情况下,第二OTP存储器元件是冗余的,原因在于,如果第一OTP存储器元件被成功编程,那么第二OTP存储器元件不会影响逻辑位的值。然而,如果第一OTP存储器元件在编程或读出(读取)时失败,那么合适操作的第二OTP存储器元件确保逻辑位提供正确值。在典型应用中,基于OTP的NVM存储器阵列中的大多数或全部逻辑位包括第一和第二(即,冗余)OTP存储器元件两者。在示范性操作中,OTP存储器元件108、110两者均被编程。在一个实施例中,使用相同的编程过程将两者编程。在第一OTP存储器元件是第一类型且第二OTP存储器元件是第二类型的实施例中,此方法尤其合意,其中OTP存储器元件的类型已被选择以在编程过程期间提供第一类型或第二类型OTP存储器元件中的至少一个的高编程良率。举例来说,当用于这两种类型装置的编程窗口(见图4)重叠时,可使用此类技术;然而,这并不是必要的。在另一实施例中,在与第二类型OTP存储器元件相同的电压和电流下编程一种类型的OTP存储器元件,但将编程信号施加到不同类型的OTP存储器元件并持续不同的时长。
举例来说,如果正常制造变化产生第一类型OTP存储器元件的对于一定数目的逻辑位脱离规范的编程电阻率,那么在未成功编程第一类型时选择可能被成功编程的第二类型OTP存储器元件增强了逻辑位的编程良率。在特定实例中,第一OTP存储器元件是具有相对窄且短的颈部(可熔链接)的第一类型多晶硅熔丝,且第二类型是具有相对宽且长的颈部的多晶硅熔丝。在特定实施例中,第一类型熔丝具有比第二类型熔丝上的颈部窄至少30%的颈部。
可在一个编程条件(例如,第一编程持续时间)下最佳地编程宽熔丝,而可在不同的编程条件(例如,第二编程持续时间)下最佳地编程窄熔丝。两种类型OTP装置的组合提供一个逻辑位。虽然编程条件将以与其它熔丝不同的方式自然地编程某些熔丝,但在单个逻辑位中提供冗余OTP存储器元件增强了逻辑位的编程良率和可靠性。
在一替代实施例中,使用第一编程过程来编程第一OTP存储器元件108,且使用第二编程过程(技术或序列)来编程第二OTP存储器元件110。与每一逻辑位仅具有单个OTP存储器元件的常规OTP存储器阵列相比,所得的基于OTP的存储器阵列具有较高的编程良率和改进的可靠性和读出裕度。
图2是根据本发明的一实施例的存储器单元200的电路图。每一逻辑位具有单个OTP存储器元件的存储器单元在此项技术中是众所周知的;因此,仅提供对存储器单元和其操作的简要描述。存储器单元200具有两个OTP存储器元件108和110,例如熔丝或反熔丝。在特定实施例中,第一OTP存储器元件108是第一类型,且第二OTP存储器元件110是第二类型。编程启用晶体管202和204分别为在相关联的编程垫206和208处供应的编程电流提供电流路径。将编程电压Vfs施加到编程垫206和208,且通过将编程信号Vpp施加到其栅极端子并持续选定时间周期Tpgm而接通编程晶体管202和204。编程晶体管202、204和Vpp可经选择以在编程期间通过熔丝元件提供所需的编程电流。
如此项技术中众所周知的,在编程了OTP存储器元件108和110之后,使用读出启用晶体管210、212、214、216来读出OTP存储器元件的逻辑状态(电阻率)。由相关联的锁存器218和220俘获每一OTP存储器元件的所读出的逻辑状态,且将OTP存储器元件108和110的输出(逻辑状态)109和111提供到OR门112。如果OTP存储器元件中的一个或两个指示逻辑“1”状态,那么存储器单元200的输出106是“1”。当然,所属领域的技术人员将了解,此实例中所选择的逻辑值和功能仅是示范性的,且替代地使用其它值和功能。举例来说,替代地,两个OTP存储器元件都是反熔丝装置,且逻辑运算器是“或非”门,或OTP存储器元件中的一个是熔丝,且另一个是反熔丝,其中在其与OR运算器之间具有反相器,或用“与非”运算器来取代所述OR运算器。
图3是根据一实施例具有两种不同类型OTP装置302、304的逻辑位300的平面图。第一OTP装置302是具有阳极308、阴极310和熔丝颈部312的窄多晶硅熔丝,所述熔丝颈部312具有宽度314和长度315。第二OTP装置304是具有第二阳极316、第二阴极318和第二熔丝颈部320的宽多晶硅熔丝,所述熔丝颈部320具有第二宽度322和第二长度323。术语“窄”和“宽”意味着第二熔丝颈部320被设计成比第一熔丝颈部312选择性地宽(即,宽度322大于宽度314)。在特定实施例中,第一颈部312为约80nm宽且约800nm长,且第二颈部320为约120nm宽且约1.2微米长,以保持相同的电阻平方(“R平方”)值,其为每一类型熔丝提供基本上相同的未编程电阻,从而可使用相同的编程电流。通常逐个地编程熔丝。如OTP熔丝编程领域中已知的,由编程晶体管提供编程电流,且将编程电流切换到熔丝。提供具有基本上相同的未编程电阻的两种不同类型OTP装置在所述装置中的每一个正被编程时从编程晶体管汲取类似的电流。此做法使得在编程这两种类型的熔丝时能使用共同的、稳定的电流源。需要准确地控制用于编程熔丝的电流。可针对每种类型熔丝单独地优化其它编程参数(例如,编程电流的持续时间)。相对容易准确控制和改变电流的持续时间。
使用标准的CMOS制造工艺将第一多晶硅熔丝302和第二多晶硅熔丝304制造在具有逻辑位的IC中。即,不需要尚不是CMOS IC制造技术的一部分的材料或工艺步骤。这是合意的,因为其无需在IC制造序列中添加额外工艺便可在IC上提供基于OTP的NVM。在一个实例中,多晶硅熔丝类似于CMOS IC中的栅极结构。熔丝颈部被制造在常规上被称作栅极介电层(其在特定实例中是STI氧化物层)的层上。熔丝颈部具有形成在栅极介电层上的p+掺杂多晶硅层,且硅化物(例如,硅化镍)的层形成在多晶硅上。氮化硅层形成在硅化物上。在编程期间,传导性硅化物元件以从阴极到阳极的电子流动进行电迁移,且元件的硅化物将在阳极侧累积。因此,很少或没有硅化物保留在熔丝颈部的位置中,且现在熔丝颈部具有高电阻,这将导致焦耳加热。来自此焦耳加热的高温将多晶硅熔丝颈部内部的掺杂剂物质(例如,硼离子)耗散到熔丝的阳极侧和阴极侧。随后,熔丝自淬灭且逐渐冷却,从而被编程到非常高的电阻。
图4展示根据一实施例的OTP型逻辑位的编程条件。第一编程过程窗口400展示提供第一类型(类型1)OTP存储器元件(例如,多晶硅熔丝)的可靠编程的编程电流和电压条件。第二编程过程窗口402展示提供第二类型(类型2)OTP存储器元件(例如,第二类型多晶硅熔丝)的可靠编程的编程电流和电压条件。第一和第二编程过程窗口重叠,从而形成重叠过程窗口404(由虚线界定)。编程条件(例如,由406处的电流和电压界定的编程条件)应可靠地编程类型1和类型2OTP存储器元件两者。在替代实施例中,选定的OTP存储器元件的编程过程窗口不重叠。应注意,在替代实施例中,为了实现更大的可靠性,可使用两个以上OTP存储器元件。
如果编程电压漂移高至(例如)点408,那么即便可能不会可靠地编程类型1OTP存储器元件,但仍将可靠地编程类型2OTP存储器元件。如果编程电压漂移低至(例如)点410,那么即便可能不会可靠地编程类型2OTP存储器元件,但仍将可靠地编程类型1OTP存储器元件。由第一和第二编程过程窗口400、402的实线外部周边412界定具有类型1和类型2OTP存储器元件两者的逻辑位的编程过程窗口。预期在此编程过程窗口412内任何位置出现的编程条件将编程类型1或类型2OTP存储器元件中的至少一个,且在某些例子中,可靠地编程所述两者。
因此,在比仅具有一种类型OTP存储器元件的常规逻辑位大的编程条件范围上可靠地编程根据实施例的逻辑位。
其它编程参数可用于类似地说明具有不同类型OTP存储器元件的逻辑位在更广范围的编程和OTP存储器元件制造工艺变化上提供改进的编程良率。
使用65nm CMOS制造工艺用两种不同类型的多晶硅熔丝来制造测试芯片。第一编程过程用于编程第一类型的多晶硅熔丝,且第二编程过程用于编程第二类型的多晶硅熔丝。针对每种类型熔丝优化两种类型编程过程。评估测试芯片的编程质量(编程电阻)。从这些测试芯片获得的数据展示逻辑位的更佳编程可靠性和编程良率。
图5是根据本发明的一实施例的集成电路500的平面图。集成电路是FPGA(现场可编程门阵列),其在若干功能区块(例如,RAM和逻辑)中包括CMOS部分,且是使用CMOS制造工艺制造的。具有多个根据本发明的一个或一个以上实施例的OTP存储器元件的逻辑位并入在IC的若干功能区块中的任一个中,例如存储器区块、逻辑区块、I/O区块、时钟电路、收发器或其它功能区块;在许多功能区块内;或在FPGA 500的物理部分或区段内。具有根据本发明的实施例的冗余(双)OTP存储器元件(例如,熔丝)的逻辑位在FPGA中是尤其合意的,因为其提供可靠的、安全的芯片上NVM以用于多种用途。举例来说,其可用于组件识别,或避免必须从外部源将存储在芯片上NVM中的数据下载到IC,这可能耗时且可能被拦截。在另一实例应用中,根据一实施例的芯片上OTP NVM可用于解密(例如,通过存储一个或一个以上解密密钥)从外部源传送到FPGA的位流,例如数据或配置文件。举例来说,未加密的配置位流可在传输期间被拦截。可通过加密配置位流并使用FPGA上的基于OTP的NVM来解密所述配置位流,而实现FPGA中的设计安全性。将芯片上加密/解密密钥存储在OTP NMV中需要相对少的存储空间,且因此消耗IC上的很少空间。尽管双OTP存储器元件存储器阵列比单OTP存储器元件存储器阵列消耗更多的芯片面积,但此代价较小,且可赢得增强的可制造性和可靠性。双OTP存储器元件存储器的另一实例使用是存储较少数目的位(通常为100位或更少)以提供数字调谐功能,例如调谐芯片上放大器或振荡器。本发明的实施例提供容易制造、可靠的芯片上NVM,且在低密度存储应用中引发的尺寸代价极小。所述NVM在断电时保留其信息,从而消除了对备用电池组或对FPGA的其它连续功率供应的需要。
FPGA架构包括较大数目的不同可编程瓦片,其包括多千兆位收发器(MGT 501)、可配置逻辑区块(CLB 502)、随机存取存储器区块(BRAM 503)、输入/输出区块(IOB 504)、配置和计时逻辑(CONFIG/CLOCKS 505)、数字信号处理区块(DSP 506)、专用输入/输出区块(I/O 507)(例如,配置端口和时钟端口),以及其它可编程逻辑508,例如数字时钟管理器、模拟到数字转换器、系统监视逻辑等等。某些FPGA还包括专用处理器区块(PROC 510)。在某些FPGA中,每一可编程瓦片包括可编程互连元件(INT 511),其具有去往和来自每一邻近瓦片中的对应互连元件的标准化连接。因此,可编程互连元件一起实施用于所说明的FPGA的可编程互连结构。可编程互连元件(INT511)还包括去往和来自同一瓦片内的可编程逻辑元件的连接,如在图5的顶部处所包括的实例所展示。举例来说,CLB 502可包括可配置逻辑元件(CLE512),所述可配置逻辑元件可经编程以实施用户逻辑以及单个可编程互连元件(INT 511)。除了一个或一个以上可编程互连元件之外,BRAM 503还可包括BRAM逻辑元件(BRL 513)。通常,包括在瓦片中的互连元件的数目取决于瓦片的高度。在所描绘的实施例中,BRAM瓦片具有与四个CLB相同的高度,但也可使用其它数目(例如,五个)。除了适当数目的可编程互连元件之外,DSP瓦片506还可包括DSP逻辑元件(DSPL 514)。除了可编程互连元件(INT511)的一个例子之外,IOB 504例如可包括输入/输出逻辑元件(IOL 515)的两个例子。所属领域的技术人员将明白,例如连接到I/O逻辑元件515的实际I/O垫是使用层叠在各种所说明的逻辑区块上方的金属来制造的,且通常不限于输入/输出逻辑元件515的区域。在所描绘的实施例中,电路小片中心附近的柱状区域(图5中展示为阴影)用于配置、时钟和其它控制逻辑。
利用图5中所说明的架构的某些FPGA包括额外的逻辑区块,其分裂构成FPGA的大部分的规则柱状结构。所述额外的逻辑区块可为可编程区块和/或专用逻辑。举例来说,图5中所示的处理器区块PROC 510横越若干列的CLB和BRAM。
应注意,图5意在仅说明示范性FPGA架构。列中的逻辑区块的数目、列的相对宽度、列的数目和次序、包括在列中的逻辑区块的类型、逻辑区块的相对大小以及图5的顶部处所包括的互连/逻辑实施方案纯粹是示范性的。举例来说,在实际的FPGA中,每当出现CLB时,通常包括CLB的一个以上邻近列,以促进用户逻辑的有效实施。
图6是根据本发明的一实施例操作存储器单元的方法600的流程图。将第一编程条件施加到逻辑位中的第一一次性可编程(“OTP”)存储器元件(步骤602)。将第二编程条件施加到逻辑位中的第二OTP存储器元件(步骤604)。
在特定实施例中,第一编程条件(例如,编程电压、编程电流和电流脉冲持续时间)与第二编程条件相同。在替代实施例中,第一编程条件经优化以用于编程第一OTP存储器元件,且第二编程条件经优化以用于编程第二OTP存储器元件。在特定实施例中,第一编程条件具有第一编程过程窗口,且第二编程条件具有第二编程过程窗口。第一编程过程窗口至少部分与第二编程过程窗口重叠,以形成用于逻辑位的重叠编程过程窗口。
来自逻辑位中的第一OTP存储器元件的第一存储器元件输出和来自逻辑位中的第二OTP存储器元件的第二存储器元件输出耦合到存储器单元的逻辑运算器(步骤606),且逻辑运算器经操作(步骤608)以根据第一存储器元件输出、第二存储器元件输出和逻辑运算器而从存储器单元提供逻辑输出。在特定实施例中,第一和第二OTP存储器元件是熔丝,且逻辑运算器是OR门。在特定实施例中,来自存储器单元的逻辑输出是解密密钥的一部分。在其它实施例中,来自存储器单元的逻辑输出用于解密现场可编程门阵列的配置位流。在替代实施例中,来自存储器单元的逻辑输出提供FPGA的组件识别。
虽然已结合特定实施例描述了本发明,但所属领域的技术人员将清楚这些实施例的变化。因此,所附权利要求书的精神和范围不应限于上文描述。
Claims (9)
1.一种存储器单元,其包含:
单一逻辑位,其具有
第一类型的第一一次性可编程OTP存储器元件,其提供第一OTP存储器元件输出,和
第二类型的第二OTP存储器元件,其提供第二OTP存储器元件输出;以及
逻辑运算器,其耦合到所述第一OTP存储器元件输出和所述第二OTP存储器元件输出,且提供所述存储器单元的存储器输出;
其中所述第一类型是第一熔丝类型及所述第二类型是第二熔丝类型,且所述第一类型不同于所述第二类型。
2.根据权利要求1所述的存储器单元,其中所述第一OTP存储器元件是第一熔丝,所述第二OTP存储器元件是第二熔丝,且所述逻辑运算器是OR门。
3.根据权利要求1所述的存储器单元,其中所述第一熔丝类型具有第一编程过程窗口,且所述第二熔丝类型具有第二编程过程窗口,所述第一编程过程窗口至少部分与所述第二编程过程窗口重叠,以提供逻辑位编程过程窗口。
4.根据权利要求2所述的存储器单元,其中所述第一熔丝是多晶硅熔丝,且所述第二熔丝选自由金属熔丝、触点熔丝和通道熔丝组成的群组。
5.根据权利要求2所述的存储器单元,其中所述第一熔丝是具有第一熔丝颈部的第一多晶硅熔丝,所述第一熔丝颈部具有第一熔丝颈部宽度,且所述第二熔丝是具有第二熔丝颈部的第二多晶硅熔丝,所述第二熔丝颈部具有第二熔丝颈部宽度,所述第二熔丝颈部宽度比所述第一熔丝颈部宽度选择性地宽。
6.根据权利要求1所述的存储器单元,其中所述第一OTP存储器元件是反熔丝,且所述第二OTP存储器元件选自由熔丝和反熔丝组成的群组。
7.根据权利要求1所述的存储器单元,其中所述第一OTP存储器元件和所述第二OTP存储器元件是使用互补金属氧化物半导体CMOS制造工艺来制造的。
8.根据权利要求1所述的存储器单元,其中所述单一逻辑位是解密密钥的一部分。
9.根据权利要求1所述的存储器单元,其中所述单一逻辑位提供集成电路的组件识别。
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US11/588,775 US7567449B2 (en) | 2006-10-27 | 2006-10-27 | One-time-programmable logic bit with multiple logic elements |
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2006
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2007
- 2007-10-25 CN CN200780040013XA patent/CN101548376B/zh active Active
- 2007-10-25 JP JP2009533407A patent/JP4999017B2/ja active Active
- 2007-10-25 CA CA2666120A patent/CA2666120C/en active Active
- 2007-10-25 WO PCT/US2007/022657 patent/WO2008057257A2/en active Application Filing
- 2007-10-25 EP EP07839793A patent/EP2076921A2/en not_active Ceased
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Also Published As
Publication number | Publication date |
---|---|
HK1132377A1 (en) | 2010-02-19 |
WO2008057257A2 (en) | 2008-05-15 |
WO2008057257A3 (en) | 2008-07-10 |
JP2010507255A (ja) | 2010-03-04 |
CA2666120A1 (en) | 2008-05-15 |
CA2666120C (en) | 2010-09-14 |
CN101548376A (zh) | 2009-09-30 |
EP2076921A2 (en) | 2009-07-08 |
US7567449B2 (en) | 2009-07-28 |
JP4999017B2 (ja) | 2012-08-15 |
US20080101146A1 (en) | 2008-05-01 |
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