CN101540329A - Thin film transistor substrate and manufacturing process thereof - Google Patents
Thin film transistor substrate and manufacturing process thereof Download PDFInfo
- Publication number
- CN101540329A CN101540329A CN200810066125A CN200810066125A CN101540329A CN 101540329 A CN101540329 A CN 101540329A CN 200810066125 A CN200810066125 A CN 200810066125A CN 200810066125 A CN200810066125 A CN 200810066125A CN 101540329 A CN101540329 A CN 101540329A
- Authority
- CN
- China
- Prior art keywords
- film transistor
- scan line
- thin film
- hole
- base plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention relates to a thin film transistor substrate and a manufacturing process thereof. The thin film transistor substrate comprises a plurality of first scanning beams, second scanning beams, data wires, first pixel electrodes, second pixel electrodes, first thin film transistors and second thin film transistors. The first scanning beams are parallel with each other, the second scanning beams are parallel with the first scanning beams as well as insulated and overlapped with the first scanning beams; and the data wires are vertically insulated and crossed with the first scanning beams and the second scanning beams. Grids of the first thin film transistors are connected to the first scanning beams, source electrodes are connected to the data wires, and drain electrodes are connected to the first pixel electrodes; and grids of the second thin film transistors are connected to the second scanning beams, source electrodes are connected to the data wires, and drain electrodes are connected to the second pixel electrodes. The thin film transistor substrate has a high aperture opening ratio.
Description
Technical field
The present invention relates to a kind of thin film transistor base plate and manufacturing process thereof.
Background technology
Display panels generally includes a thin film transistor base plate, a colored filter substrate and is clipped in liquid crystal layer between these two substrates, it is by applying voltage respectively to these two substrates, control therebetween that liquid crystal molecule reverses and realizes passing through or not passing through of light, thereby reach the purpose of demonstration.The liquid crystal drive mode of tradition display panels is a nematic mode, yet its angular field of view is narrow,, when observing picture from different perspectives, will observe different display effects that is.
For solving the narrower problem in nematic mode display panels visual angle, industry proposes a kind of four territory vertical alignment-type liquid crystal display panels, by opposite flank a plurality of "＜" shape projection and groove are set at interval at these two substrates, each pixel cell is divided into four zones, each regional liquid crystal molecule has a fixed orientation, thereby the liquid crystal molecular orientation in the whole pixel cell disperses, and then enlarges the overall viewing angle of this pixel cell, improves the viewing angle characteristic of display panels.
Yet, because long axis of liquid crystal molecule is different with the optical index of minor axis, will produce color offset phenomenon when observing four territory vertical alignment-type liquid crystal display panels from different perspectives, influence display quality.For improving the color offset phenomenon of four territory vertical alignment-type liquid crystal display panels, industry proposes again a pixel cell is divided into two sub-pixel unit, each sub-pixel unit is divided into four zones, offer two operating voltages that sub-pixel unit is different by two thin-film transistors respectively, thereby eight territories of realizing vertical alignment-type liquid crystal display panel show, improve color offset phenomenon.
Seeing also Fig. 1, is a kind of part plan schematic diagram of prior art thin film transistor base plate.This thin film transistor base plate 100 comprises many first scan lines 118, many second scan lines 119, many data wires 138, a plurality of the first film transistor 101, a plurality of second thin-film transistor 103, a plurality of first pixel electrode 154, a plurality of second pixel electrode 155, a plurality of first through hole 144 and a plurality of second through holes 145.
These many first scan lines 118 are parallel to each other with these many second scan lines 119 and setting at interval successively.These many data wires 138 and this first scan line 118 and 119 vertically insulated intersecting of second scan line.This first film transistor 101 is positioned at the intersection of this first scan line 118 and this data wire 138, and it comprises a first grid 116, one first source electrode 134 and one first drain electrode 135.This first grid 116 is connected to this first scan line 118; This first source electrode 134 is connected to this data wire 138; This first drain electrode 135 is connected to this first pixel electrode 154 by this first through hole 144.This second thin-film transistor 103 is positioned at the intersection of this second scan line 119 and this data wire 138, and it comprises a second grid 117, one second source electrode 136 and one second drain electrode 137.This second grid 117 is connected to this second scan line 119; This second source electrode 136 is connected to this data wire 138; This second drain electrode 137 is connected to this second pixel electrode 155 by this second through hole 145.
See also Fig. 2 and Fig. 3, Fig. 2 is the generalized section of thin film transistor base plate 100 shown in Figure 1 along the II-II direction, and Fig. 3 is the manufacturing process flow diagram of thin film transistor base plate 100 shown in Figure 1.The manufacturing process of this thin film transistor base plate 100 mainly comprises five road masks, and concrete steps are as follows:
Step S11: form first grid, second grid, first scan line and second scan line;
One substrate of glass 111 is provided, form a gate metal layer and one first photoresist layer thereon in regular turn, expose with this first photoresist layer of one first mask alignment, again this first photoresist layer is developed, thereby form a predetermined photoresist pattern.This gate metal layer is carried out etching, to remove not by the part of grid pole metal level of this photoresist pattern covers, and then form this first grid 116, this second grid 117, this first scan line 118 and second scan line 119, remove this first photoresist layer.
Step S12: form gate insulator and semiconductor channel layer;
On this first grid 116, second grid 117, this first scan line 118 and second scan line 119, form a gate insulator 121, semi-conductor layer and one second photoresist layer in regular turn.This semiconductor layer comprises that one is positioned at amorphous silicon layer and on this gate insulator and is positioned at heavily doped amorphous silicon layer on this amorphous silicon layer.Provide this second photoresist layer of one second mask alignment to expose, again the second photoresist layer after the exposure is developed, thereby form a predetermined photoresist pattern.This semiconductor layer is carried out etching, and then form this semiconductor channel layer 126, remove this second photoresist layer.
Step S13: the slit that forms first source electrode, first drain electrode, second source electrode, second source electrode, data wire and semiconductor channel layer;
On this gate insulator 121 and this semiconductor channel layer 126, form one source/drain metal layer and one the 3rd photoresist layer in regular turn.Provide one the 3rd mask alignment the 3rd photoresist layer to expose, again the 3rd photoresist layer after the exposure is developed, thereby form a predetermined photoresist pattern.Successively this source/drain metal layer and semiconductor channel layer 126 are carried out etching, and then form the slit 139 of this first source electrode 134, first drain electrode, 135, second source electrode 136, second source electrode 137, data wire 138 and semiconductor channel layer 126, remove the 3rd photoresist layer.
Step S14: form passivation layer, first through hole and second through hole;
On the slit 139 of this gate insulator 121, this first source electrode 134, first drain electrode, 135, second source electrode 136, second drain electrode 137, data wire 138 and semiconductor channel layer 126, form a passivation layer 141 and one the 4th photoresist layer in regular turn.Provide one the 4th mask alignment the 4th photoresist layer to expose, again the 4th photoresist layer after the exposure is developed, thereby form a predetermined photoresist pattern.This passivation layer 141 is carried out etching, and then form this first through hole 144 that runs through this passivation layer 141 and second through hole 145, remove the 4th photoresist layer.
Step S15: form first pixel electrode and second pixel electrode;
On this passivation layer 141, this first through hole 144 and second through hole 145, form a transparency conducting layer and one the 5th photoresist layer in regular turn.Provide one the 5th mask alignment the 5th photoresist layer to expose, again the 5th photoresist layer after the exposure is developed, thereby form a predetermined photoresist pattern.This transparency conducting layer is carried out etching, and then form this first pixel electrode 154 and second pixel electrode 155, remove the 5th photoresist layer.
Yet, the thin film transistor base plate 100 that obtains by above-mentioned manufacturing process, it comprises many first scan lines 118 and second scan line 119, this first scan line 118 and second scan line, 119 area occupied are bigger, cause adopting the display panels aperture opening ratio of this thin film transistor base plate 100 less, influence the display effect of this display panels.
Summary of the invention
For solving the lower problem of prior art thin film transistor base plate aperture opening ratio, be necessary the thin film transistor base plate that provides a kind of aperture opening ratio higher.
For solving the lower problem of thin film transistor base plate aperture opening ratio that prior art thin film transistor base plate manufacturing process obtains, be necessary to provide a kind of manufacturing process that can obtain than the thin film transistor base plate of high aperture.
A kind of thin film transistor base plate, it comprise many first scan lines that are parallel to each other, many be parallel to this first scan line and with this first scan line insulate second scan line, many and this first scan line and the vertically insulated crossing data wire of second scan line, a plurality of first pixel electrode, a plurality of second pixel electrode, a plurality of the first film transistor and a plurality of second thin-film transistor of overlapping setting.The transistorized grid of this first film is connected to this first scan line, and source electrode is connected to this data wire, and drain electrode is connected to this first pixel electrode; The grid of this second thin-film transistor is connected to this second scan line, and source electrode is connected to this data wire, and drain electrode is connected to this second pixel electrode.
A kind of manufacturing process of above-mentioned thin film transistor base plate, it comprises the steps: to provide a substrate, forms this first grid, second grid and first scan line in this substrate; On this first grid, second grid and first scan line, form a gate insulator; On this gate insulator, form the semiconductor channel layer in regular turn; On this semiconductor channel layer, form this first source electrode, second source electrode, first drain electrode, second drain electrode and the data wire; On this first source electrode, second source electrode, first drain electrode, second drain electrode and data wire, form a passivation layer; On this passivation layer, form first pixel electrode, second pixel electrode and many second scan lines overlapping with this first scan line.
Compared with prior art, by the thin film transistor base plate that above-mentioned manufacturing process obtains, its two scan lines are overlapping, thereby these two scan line area occupied are less, use the display panels aperture opening ratio of this thin film transistor base plate higher.In addition, the manufacturing process of this thin film transistor base plate is five road mask manufacturing process, does not also increase the mask number of manufacturing process when obtaining than the thin film transistor base plate of high aperture.
Description of drawings
Fig. 1 is a kind of part plan schematic diagram of prior art thin film transistor base plate.
Fig. 2 is the generalized section of thin film transistor base plate shown in Figure 1 along the II-II direction.
Fig. 3 is the manufacturing process flow diagram of thin film transistor base plate shown in Figure 1.
Fig. 4 is the part plan schematic diagram of thin film transistor base plate one better embodiment of the present invention.
Fig. 5 is the generalized section of thin film transistor base plate shown in Figure 4 along the V-V direction.
Fig. 6 is the manufacturing process flow diagram of thin film transistor base plate shown in Figure 4.
Fig. 7 is each step schematic diagram of the manufacturing process of thin film transistor base plate shown in Figure 4 to Figure 17.
Embodiment
Consulting Fig. 4, is the part plan schematic diagram of thin film transistor base plate one better embodiment of the present invention.This thin film transistor base plate 200 comprises many first scan lines 218, many second scan lines 259, many data wires 238, a plurality of the first film transistor 201, a plurality of second thin-film transistor 203, a plurality of first pixel electrode 254, a plurality of second pixel electrode 255, a plurality of first through hole 244, a plurality of second through hole 245 and a plurality of third through-holes 246.
These many first scan lines 218 are parallel to each other, and these many second scan lines 259 are parallel to this first scan line 218, and two-phase corresponding scanning line 218, the 259 insulation overlapping setting corresponding one by one with this first scan line 218 of this second scan line 259.Wherein, this second scan line 259 be positioned at this first scan line 218 directly over, and the width of this second scan line 259 is big and this first scan line 218 is covered fully than the width of this first scan line 218.The material of this first scan line 218 is a metal, as: aluminium (Al) is metal, molybdenum (Mo), chromium (Cr), tantalum (Ta) or copper (Cu).The material of this second scan line 259 is a transparency conducting layer, as: indium tin oxide (Indium Tin Oxide, ITO) or indium-zinc oxide (Indium ZincOxide, IZO).
These many data wires 238 are parallel to each other and are vertically insulated crossing with this first scan line 218, these many data wires 238 and this first scan line, 218 crossing a plurality of rectangular areas (indicating) of defining.Wherein, each rectangular area comprises a first film transistor 201, one second thin-film transistor 203, one first pixel electrode 254 and one second pixel electrode 255.
This first film transistor 201 is positioned at the intersection of this first scan line 218 and this data wire 238, and it comprises a first grid 216, one first source electrode 234 and one first drain electrode 235.This first grid 216 is connected to this first scan line 218; This first source electrode 234 is connected to this data wire 238; This first drain electrode 235 is connected to this first pixel electrode 254 by this first through hole 244.
This second thin-film transistor 203 is positioned at the intersection of this second scan line 259 and this data wire 238, and it comprises a second grid 217, one second source electrode 236 and one second drain electrode 237.There is an overlapping region (not indicating) in this second grid 217 with this second scan line 259, and this third through-hole 246 is arranged on this overlapping region.This second grid is connected to this second scan line 259 by this third through-hole 246; This second source electrode 236 is connected to this data wire 238; This second drain electrode 237 is connected to this second pixel electrode 255 by this second through hole 245.
See also Fig. 5 to Figure 17, Fig. 5 is the generalized section of this thin film transistor base plate 200 along the V-V direction, and Fig. 6 is the manufacturing process flow diagram of this thin film transistor base plate 200, and Fig. 7 is each step schematic diagram of the manufacturing process of this thin film transistor base plate 200 to Figure 17.The manufacturing process of this thin film transistor base plate 200 mainly comprises five road masks, and concrete steps are as follows:
Step S21: form first grid, second grid and first scan line;
See also Fig. 7 and Fig. 8, a substrate of glass 211 is provided, form a gate metal layer 213 and one first photoresist layer 215 thereon in regular turn.Wherein, this gate metal layer 213 can be a single layer structure, also can be a sandwich construction, and its material can be aluminum-based metal, molybdenum, chromium, tantalum or copper.
Provide this first photoresist layer 215 of one first mask alignment to expose, again the first photoresist layer 215 after the exposure is developed, thereby form a predetermined photoresist pattern.This gate metal layer 213 is carried out etching, removing, and then form this first grid 216, this second grid 217 and this first scan line 218, remove this first photoresist layer 215 not by the part of grid pole metal level 213 of this photoresist pattern covers.Wherein, this first grid 216 is connected to this first scan line 218.
Step S22: form gate insulator and semiconductor channel layer;
See also Fig. 9 and Figure 10, deposited silicon nitride (SiNx) film on this first grid 216, second grid 217 and this first scan line 218, thus form a gate insulator 221; On this gate insulator 221, form semi-conductor layer 223 and one second photoresist layer 225 more in regular turn in regular turn.Wherein, this semiconductor layer 223 comprises that one is positioned at amorphous silicon layer on this gate insulator 221 (figure does not show) and and is positioned at heavily doped amorphous silicon layer (scheming not show) on this amorphous silicon layer.
Provide this second photoresist layer 225 of one second mask alignment to expose, again the second photoresist layer 225 after the exposure is developed, thereby form a predetermined photoresist pattern.This semiconductor layer 223 is carried out etching, removing, and then form this semiconductor channel layer 226, remove this second photoresist layer 225 not by the part semiconductor layer 223 of this photoresist pattern covers.
Step S23: the slit that forms first source electrode, first drain electrode, second source electrode, second source electrode, data wire and semiconductor channel layer;
See also Figure 11, Figure 12 and Figure 13, on this gate insulator 221 and this semiconductor channel layer 226, form one source/drain metal layer 231 and one the 3rd photoresist layer 233 in regular turn.Provide one the 3rd mask alignment the 3rd photoresist layer 233 to expose, again the 3rd photoresist layer 233 after the exposure is developed, thereby form a predetermined photoresist pattern.This source/drain metal layer 231 is carried out etching, and then form this first source electrode 234, first drain electrode 235, second source electrode 236, second source electrode 237 and the data wire 238.Further adopt HCl and SF
6Mist as etching gas this semiconductor channel layer 226 is carried out etching, form the slit 239 of this semiconductor channel layer 226, remove the 3rd photoresist layer 233.Wherein, this first source electrode 234 is connected to this data wire 238; Second source electrode 236 is connected to this data wire 238.
Step S24: form passivation layer, first through hole, second through hole and third through-hole;
See also Figure 14 and Figure 15, on the slit 239 of this gate insulator 221, this first source electrode 234, first drain electrode, 235, second source electrode 236, second drain electrode 237, data wire 238 and semiconductor channel layer 226, form a passivation layer 241 and one the 4th photoresist layer 243 in regular turn.Provide one the 4th mask alignment the 4th photoresist layer 243 to expose, again the 4th photoresist layer 243 after the exposure is developed, thereby form a predetermined photoresist pattern.This passivation layer 241 is carried out etching, and then form first through hole 244, second through hole 245 and third through-hole 246 that this runs through this passivation layer 241, remove the 4th photoresist layer 243.Wherein, 244 pairs of this first through holes should first drain electrode 235, and 245 pairs of this second through holes should second drain electrode 237, and 246 pairs of this third through-holes should first grid 217.
Step S25: form second scan line, first pixel electrode and second pixel electrode;
See also Figure 16 and Figure 17, on this passivation layer 241, this first through hole 244, second through hole 245 and third through-hole 246, form a transparency conducting layer 251 and one the 5th photoresist layer 253 in regular turn.Provide one the 5th mask alignment the 5th photoresist layer 253 to expose, again the 5th photoresist layer 253 after the exposure is developed, thereby form a predetermined photoresist pattern.This transparency conducting layer 251 is carried out etching, and then form this first pixel electrode 254, second pixel electrode 255 and, remove the 5th photoresist layer 253 one by one to should first scan line 218 and second scan line 259 overlapping with this first scan line 218.Wherein, this first pixel electrode 254 is connected to this first drain electrode 235 by this first through hole 244, this second pixel electrode 255 is connected to this second drain electrode 237 by this second through hole 245, this second scan line 259 is connected to this first grid 217 by this third through-hole 246, and this second scan line 259 is positioned at directly over this first scan line 218, and this first scan line 259 is covered fully.
Compared with prior art, the thin film transistor base plate 200 that obtains by above-mentioned manufacturing process, its first scan line 218 and second scan line overlapping 259, thereby this first scan line 218 and second scan line, 259 area occupied are less, use the display panels aperture opening ratio of this thin film transistor base plate 200 higher.In addition, the manufacturing process of this thin film transistor base plate 200 is five road mask manufacturing process, does not also increase the mask number of manufacturing process in the thin film transistor base plate 200 that obtains than high aperture.
It is described that thin film transistor base plate of the present invention is not limited to above-mentioned execution mode, as: in the thin film transistor base plate 200 of first execution mode, the material of this second scan line 259 also can be metal; This first scan line 218 and second scan line 259 also can be overlapped; This first scan line 218 also can equate with the width of second scan line 259, and this second scan line 259 comprises an extension, and this extension and this second grid 317 comprise this overlapping region.
In addition, thin film transistor base plate 200 of the present invention also can be applicable to traditional display panels, and two adjacent scan lines are overlapping, to increase aperture opening ratio.
Claims (10)
1. thin film transistor base plate, it comprises that many first scan lines that are parallel to each other, many are parallel to second scan line of this first scan line, many and this first scan line and the vertically insulated crossing data wire of second scan line, a plurality of first pixel electrode, a plurality of second pixel electrode, a plurality of the first film transistor and a plurality of second thin-film transistor, the transistorized grid of this first film is connected to this first scan line, source electrode is connected to this data wire, and drain electrode is connected to this first pixel electrode; The grid of this second thin-film transistor is connected to this second scan line, and source electrode is connected to this data wire, and drain electrode is connected to this second pixel electrode, it is characterized in that: the overlapping setting of insulating of this second scan line and first scan line.
2. thin film transistor base plate as claimed in claim 1, it is characterized in that: this thin film transistor base plate further comprises a plurality of first through holes, a plurality of second through hole and a plurality of third through-hole, this the first film transistor drain is to be connected to this first pixel electrode by this first through hole, the drain electrode of this second thin-film transistor is to be connected to this second pixel electrode by this second through hole, and the grid of this second thin-film transistor is to be connected to this second scan line by this third through-hole.
3. thin film transistor base plate as claimed in claim 2 is characterized in that: this first through hole, second through hole and third through-hole are to form in same mask manufacturing process.
4. thin film transistor base plate as claimed in claim 2 is characterized in that: there is an overlapping region in the grid of this second scan line and this second thin-film transistor, and this third through-hole is positioned at this overlapping region.
5. thin film transistor base plate as claimed in claim 1, it is characterized in that: the material of this second scan line, this first pixel electrode and second pixel electrode is a transparency conducting layer, and this first pixel electrode, second pixel electrode and this second scan line are to form in same mask manufacturing process.
6. the manufacturing process of thin film transistor base plate as claimed in claim 1, it comprises the steps:
A., one substrate is provided, in this substrate, forms this first grid, second grid and first scan line;
B. on this first grid, second grid and first scan line, form a gate insulator; On this gate insulator, form the semiconductor channel layer in regular turn;
C. on this semiconductor channel layer, form this first source electrode, second source electrode, first drain electrode, second drain electrode and the data wire;
D. on this first source electrode, second source electrode, first drain electrode, second drain electrode and data wire, form a passivation layer; With
E. on this passivation layer, form first pixel electrode, second pixel electrode and many second scan lines overlapping with this first scan line.
7. the manufacturing process of thin film transistor base plate as claimed in claim 6, it is characterized in that: further comprise in this steps d forming a plurality of first through holes, second through hole and the third through-hole that runs through this passivation layer, corresponding first drain electrode of this first through hole, this second through hole to should second drain electrode, this third through-hole is to should second grid.
8. the manufacturing process of thin film transistor base plate as claimed in claim 7, it is characterized in that: this first through hole, second through hole and third through-hole are to form in same mask manufacturing process.
9. the manufacturing process of thin film transistor base plate as claimed in claim 6, it is characterized in that: among this step e, this first pixel electrode, second pixel electrode and this second scan line are to form in same mask manufacturing process.
10. the manufacturing process of thin film transistor base plate as claimed in claim 6, it is characterized in that: the material of this first pixel electrode, second pixel electrode and this second scan line all is a transparency conducting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100661259A CN101540329B (en) | 2008-03-19 | 2008-03-19 | Thin film transistor substrate and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100661259A CN101540329B (en) | 2008-03-19 | 2008-03-19 | Thin film transistor substrate and manufacturing process thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101540329A true CN101540329A (en) | 2009-09-23 |
| CN101540329B CN101540329B (en) | 2012-06-27 |
Family
ID=41123422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100661259A Expired - Fee Related CN101540329B (en) | 2008-03-19 | 2008-03-19 | Thin film transistor substrate and manufacturing process thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101540329B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103048838A (en) * | 2012-12-13 | 2013-04-17 | 北京京东方光电科技有限公司 | Array substrate, liquid crystal display panel and driving method |
| CN103116238A (en) * | 2013-02-05 | 2013-05-22 | 北京京东方光电科技有限公司 | Array substrate and liquid crystal display panel |
| CN103217846A (en) * | 2013-04-23 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103616785A (en) * | 2013-11-08 | 2014-03-05 | 友达光电股份有限公司 | Pixel array |
| CN105185295A (en) * | 2015-08-24 | 2015-12-23 | 友达光电股份有限公司 | Pixel array |
| WO2023151107A1 (en) * | 2022-02-10 | 2023-08-17 | 武汉华星光电技术有限公司 | Display panel |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5994174A (en) * | 1997-09-29 | 1999-11-30 | The Regents Of The University Of California | Method of fabrication of display pixels driven by silicon thin film transistors |
| KR100670051B1 (en) * | 1999-12-01 | 2007-01-16 | 삼성전자주식회사 | A thin film transistor array panel and a manufacturing method thereof |
| WO2001082273A1 (en) * | 2000-04-21 | 2001-11-01 | Seiko Epson Corporation | Electrooptical device |
| CN1848433A (en) * | 2005-04-11 | 2006-10-18 | 精工爱普生株式会社 | Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus |
| CN101131519A (en) * | 2006-08-24 | 2008-02-27 | 精工爱普生株式会社 | Circuit board for electro-optical device, electro-optical device, and electronic apparatus |
-
2008
- 2008-03-19 CN CN2008100661259A patent/CN101540329B/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103048838B (en) * | 2012-12-13 | 2015-04-15 | 北京京东方光电科技有限公司 | Array substrate, liquid crystal display panel and driving method |
| CN103048838A (en) * | 2012-12-13 | 2013-04-17 | 北京京东方光电科技有限公司 | Array substrate, liquid crystal display panel and driving method |
| CN103116238A (en) * | 2013-02-05 | 2013-05-22 | 北京京东方光电科技有限公司 | Array substrate and liquid crystal display panel |
| US9323122B2 (en) | 2013-02-05 | 2016-04-26 | Beijing Boe Optoelectronics Technology Co., Ltd. | Array substrate and liquid crystal display panel comprising dual gate lines having TFT and pixel connection between the gate lines |
| WO2014121574A1 (en) * | 2013-02-05 | 2014-08-14 | 北京京东方光电科技有限公司 | Array substrate and liquid crystal display panel |
| CN103116238B (en) * | 2013-02-05 | 2015-09-09 | 北京京东方光电科技有限公司 | A kind of array base palte and display panels |
| KR101486646B1 (en) | 2013-02-05 | 2015-01-26 | 베이징 비오이 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | Array substrate and liquid crystal display panel |
| CN103217846B (en) * | 2013-04-23 | 2015-12-02 | 京东方科技集团股份有限公司 | Array base palte and display device |
| WO2014172966A1 (en) * | 2013-04-23 | 2014-10-30 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103217846A (en) * | 2013-04-23 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate and display device |
| US9385144B2 (en) | 2013-04-23 | 2016-07-05 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| CN103616785A (en) * | 2013-11-08 | 2014-03-05 | 友达光电股份有限公司 | Pixel array |
| CN103616785B (en) * | 2013-11-08 | 2016-04-20 | 友达光电股份有限公司 | Pixel array |
| CN105185295A (en) * | 2015-08-24 | 2015-12-23 | 友达光电股份有限公司 | Pixel array |
| WO2023151107A1 (en) * | 2022-02-10 | 2023-08-17 | 武汉华星光电技术有限公司 | Display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101540329B (en) | 2012-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8767158B2 (en) | Array substrate, liquid crystal panel, liquid crystal display and driving method thereof | |
| CN201788341U (en) | Array substrate, liquid crystal panel and liquid crystal display | |
| CN102033376B (en) | Fringe field switching mode liquid crystal display device and method of fabricating the same | |
| CN103365011B (en) | The array base palte of fringe field switching mode LCD | |
| CN102243401B (en) | Liquid crystal display device | |
| CN107479287B (en) | Array substrate and manufacturing method thereof | |
| CN102937767B (en) | The method for making of array base palte, display device and array base palte | |
| JP6621284B2 (en) | Display device | |
| CN100538488C (en) | I n plane switching mode liquid crystal display device and manufacture method thereof | |
| CN104049429A (en) | Pixel structure and manufacturing method thereof | |
| CN105159001A (en) | Array substrate, manufacturing method thereof, display panel and display device | |
| WO2017054394A1 (en) | Array substrate and manufacturing method therefor, and display device | |
| KR101622655B1 (en) | Liquid crystal display device and method of fabricating the same | |
| CN101540329B (en) | Thin film transistor substrate and manufacturing process thereof | |
| CN104007591A (en) | Pixel structure and manufacturing method thereof | |
| CN101241278A (en) | Fringe field switching mode liquid crystal display device | |
| CN101526705B (en) | Liquid crystal display panel, thin film transistor substrate and manufacturing process thereof | |
| CN102088025A (en) | Thin film transistor substrate and method of manufacturing the same | |
| CN104049430A (en) | Array substrate, display device and manufacturing method of array substrate | |
| CN101308299B (en) | Liquid crystal display device and fabricating method thereof | |
| CN104007574A (en) | Array substrate, display device and manufacturing method of display device | |
| CN103901686A (en) | Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same | |
| KR20120129746A (en) | Thin Film Transistor Substrate Having Oxide Semiconductor and Manufacturing Method Thereof | |
| CN110687730A (en) | Thin film transistor array substrate and display panel | |
| KR20080002186A (en) | Array substrate for liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: QIMEI ELECTRONIC CO LTD Free format text: FORMER OWNER: INNOLUX DISPLAY CO., LTD. Effective date: 20120306 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20120306 Address after: 518109 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 1, floor 4, Applicant after: Qunkang Technology (Shenzhen) Co., Ltd. Co-applicant after: Chimei Optoelectronics Co., Ltd. Address before: 518109 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 1, floor 4, Applicant before: Qunkang Technology (Shenzhen) Co., Ltd. Co-applicant before: Innolux Display Group |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120627 Termination date: 20180319 |