CN101533783A - 薄型四侧扁平无引脚封装方法 - Google Patents
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Abstract
一种薄型四侧扁平无引脚封装方法,包括如下步骤:采用第一涂覆物质(塑封料)涂覆晶圆的第一表面(背面),形成连续的覆盖层;将晶圆切割成若干个分立的半导体晶粒,每一个分立的半导体晶粒的表面都具有从上述连续覆盖层中切割下来的覆盖层;将若干个分立的半导体晶粒的覆盖层贴装在框架上粘性膜的表面上;焊线(引线键合)之后,采用第二涂覆物质(塑封料)涂覆粘性表面上方暴露的表面,第二涂覆物质将贴装在粘性表面的半导体晶粒包拢在一起,形成一个整块的塑封体;切割上述整块的塑封体,得到若干个独立的封装完毕的半导体晶粒(具有完整功能的器件)。本发明的优点在于,全部的封装工艺对被封装的芯片的结构并无特殊的要求,因此是一种具有普适性的封装方法,并且采用该方法封装得到的器件厚度非常薄,有利于提高芯片的散热效率。
Description
【技术领域】
本发明涉及半导体封装领域,尤其涉及薄型四侧扁平无引脚封装方法。
【背景技术】
在日常生活中,消费者对诸如个人电话、个人数字助理以及音乐播放器的可靠性、体积以及价格都要求越来越高。例如,消费者需要他们的个人电话超薄并且可靠。这需要封装后的器件体积更小、缺陷更少。另外,这些对外型小巧的需求还可能需要具有从封装结构中向外散热的电子元件。
四侧扁平无引脚封装是现有技术中一种常见的封装方法。该方法是采用一个引线框架和一个晶粒的标准封装方法。这种方法不仅对器件的厚度有限制,而且在实施过程中可能会引入另外的工艺步骤,这些额外的工艺步骤可能成为潜在的工艺缺陷的来源,也可能会增加额外的封装制造费用。目前的四侧扁平无引脚封装的散热也存在限制,因此需要在印刷电路板(PCB)或衬底上具有额外的空间,以用于散热。
【发明内容】
本发明所要解决的技术问题是,提供一种具有普适性的、可以提高芯片散热效率的薄型四侧扁平无引脚封装方法。
为了解决上述技术问题,本发明提供了一种薄型四侧扁平无引脚封装方法,包括如下步骤:采用第一涂覆物质涂覆晶圆的第一表面(背面),形成连续的覆盖层;将晶圆切割成若干个分立的半导体晶粒,每一个分立的半导体晶粒的表面都具有从上述连续覆盖层中切割下来的覆盖层;将若干个分立的半导体晶粒的覆盖层贴装在一个粘性表面(框架贴膜的表面)上;采用第二涂覆物质涂覆粘性表面上方暴露的表面,第二涂覆物质将贴装在粘性表面的半导体晶粒和框架包拢在一起,形成一个整块的塑封体;切割上述整块的塑封体,得到若干个独立的封装完毕的半导体晶粒。
所述粘性表面贴有引线框架,将分立的半导体晶粒的覆盖层贴装在贴装表面上的步骤包括分别将每一个半导体晶粒单独置于引线框架的框体内。
所述技术方案进一步包括如下步骤:采用引线键合的方法将分立半导体晶粒表面的导电触点同对应的引线框架上的导电引脚相连接,所述引线框架与分立半导体晶粒覆盖层均贴装在粘性表面上。
所述涂覆粘性表面上方暴露的表面的步骤包括涂覆暴露的分立半导体晶粒表面与引线框架,所述引线框架的一部分与分立半导体晶粒表面覆盖层的一部分被贴装在粘性表面上,上述被贴装的部分是不暴露出来的。
所述第一涂覆物质与第二涂覆物质的材料可以是相同的。
所述第二涂覆物质与第一涂覆物质的一部分相融合。
所述第二涂覆物质与第一涂覆物质的一部分粘附在一起。
本发明还提供了另一种薄型四侧扁平无引脚封装方法,包括如下步骤:将晶圆的第一表面(正面)与第一粘性表面(蓝膜表面)贴装在一起;在晶圆的第二表面(背面)生长金属层,使晶圆的表面成为金属;通过晶圆的划片槽切割晶圆,从而形成分立的半导体晶粒,每一个分立的半导体晶粒均具有由上一步骤所形成的金属表面;将分立半导体晶粒的金属表面同第二粘性表面(框架贴膜的表面)贴装在一起,从而使金属表面不再暴露在外面;涂覆第二粘性表面上方暴露的表面,形成一个整块的塑封体;切割上述整块的塑封体,得到若干个独立的封装完毕的半导体晶粒。
所述技术方案进一步包括如下步骤:在所述晶圆的第二表面上进行切割,从而形成凹槽;所述之生长金属层的步骤可以在第二表面上形成一个可辨认的沟道,从而提供了一个可以用来进行对准操作的标志。
所述技术方案进一步包括如下步骤:在所述通过晶圆的划片槽切割晶圆的步骤之前,沿着晶圆第二表面的切割槽切割晶圆,从而形成一个高度小于晶圆厚度的第一切割槽。
所述对晶圆的第二次切割产生的第二切割槽的宽度小于第一切割槽的宽度,从而在切割的位置形成台阶。
所述第一粘性表面由第一晶圆贴膜(蓝膜)提供,第一晶圆贴膜具有一定的厚度,所述对晶圆进行切割时,也对第一晶圆贴膜厚度方向的一部分进行切割。
所述引线框架与第二粘贴表面贴装在一起,所述将分立半导体晶粒的金属表面粘贴在第二粘性表面包括分别将每一个半导体晶粒单独置于引线框架的框体内。
所述涂覆第二粘性表面上方暴露的表面的步骤,包括涂覆暴露的分立半导体晶粒表面与引线框架,所述引线框架的一部分与分立半导体晶粒的金属表面的一部分被贴装在粘性表面上,上述被贴装的部分是不暴露出来的。
所述技术方案进一步包括在通过划片槽划片的步骤之后,再次贴装分立的半导体晶粒,所述再次贴装包括如下步骤:在通过划片槽划片之后,将金属表面同第三粘性表面(新的蓝膜)贴装在一起;从晶圆的第一表面移除第一粘性表面。
所述贴装分立半导体晶粒的金属表面的步骤中,包括从第三粘性表面上选取分立的半导体晶粒。
所述技术方案进一步包括如下步骤:采用引线键合的方法将分立半导体晶粒表面的导电触点同对应的引线框架上的导电引脚相连接,所述引线框架与分立半导体晶粒金属表面均贴装在粘性表面上,这一粘性表面由引线框架自身的预贴膜提供,所述引线框架贴装在粘性表面上操作是在引线框架生产时完成的。
本发明的优点在于,全部的封装工艺对被封装的芯片的结构并无特殊的要求,因此是一种具有普适性的封装方法,并且采用该方法封装得到的器件厚度非常薄,有利于提高芯片的散热效率。
【附图说明】
附图1所示为本发明所述之薄型四侧扁平无引脚封装方法具体实施方式的工艺流程图;
附图2至附图8为本发明所述之薄型四侧扁平无引脚封装方法具体实施方式的实施步骤示意图;
附图9所示为本发明所述之薄型四侧扁平无引脚封装方法的另一个具体实施方式的工艺流程图;
附图10至附图19为本发明所述之薄型四侧扁平无引脚封装方法的另一个具体实施方式的实施步骤示意图。
【具体实施方式】
下面结合附图对本发明所述之薄型四侧扁平无引脚封装方法的具体实施方式做详细的叙述。
附图1所示为本发明所述之薄型四侧扁平无引脚封装方法具体实施方式的工艺流程图。步骤S10,采用第一涂覆物质涂覆晶圆的第一表面,形成连续的覆盖层;步骤S11,将晶圆切割成分立的半导体晶粒,每一个分立的半导体晶粒的表面都具有从上述连续覆盖层中切割下来的覆盖层;步骤S12,将分立的半导体晶粒的覆盖层贴装在一个粘性表面上;步骤S13,采用引线键合的方法将分立半导体晶粒表面的导电触点同对应的引线框架上的导电引脚相连接;步骤S14,采用第二涂覆物质涂覆粘性表面上方暴露的表面,第二涂覆物质将贴装在粘性表面的半导体晶粒和框架包拢在一起,形成一个整块的塑封体;步骤S15,去除塑封体表面的贴膜;步骤S16,切割上述整块的塑封体,得到独立的封装完毕的半导体晶粒。
附图2至附图8为本发明所述之薄型四侧扁平无引脚封装方法具体实施方式的实施步骤示意图。
附图2,参考步骤S10,采用第一涂覆物质涂覆晶圆101的第一表面,形成连续的覆盖层。此步骤在所述晶圆101的第一表面附着一涂覆物质,以形成具有一定厚度的第一连续覆盖层108。
附图3,参考步骤S11,将晶圆101切割成分立的半导体晶粒139、140和113,每一个分立的半导体晶粒的表面都具有从上述连续覆盖层108中切割下来的覆盖层141、142和114。所述切割在晶圆的第二表面进行,将该晶圆101切割为分立的半导体晶粒139、140和113。此步骤中,所述晶圆101可以被粘附于第一贴膜115上,所述切割操作也将第一贴膜115的一部分切断。
附图4,参考步骤S13,将分立的半导体晶粒139、140的覆盖层141、142贴装在一个粘性表面143上。所述粘性表面143贴有引线框架116,此步骤进一步包括分别将每一个半导体晶粒单独置于引线框架116的框体145与144之内。此步骤中,所述分立的半导体晶粒139、140的覆盖层141、142可以被粘附于第二贴膜121上。
附图5,参考步骤S14,采用引线键合的方法将分立半导体晶粒139、140表面的导电触点同对应的引线框架116上的导电引脚相连接。采用引线122将分立的半导体晶粒139表面的第一导电触点同引线框架116上的第一导电引脚相连接。为了清楚起见,引线123、124和125也在图中示出。采用引线123将分立的半导体晶粒139表面的第二导电触点同引线框架116上的第二导电引脚相连接。与引线122和123相类似地,采用引线124和125将另一个分立的半导体晶粒140表面的导电触点同引线框架116上的其他导电引脚相连接。
附图6,参考步骤S15,采用第二涂覆物质涂覆粘性表面143上方暴露的表面,第二涂覆物质将贴装在粘性表面的半导体晶粒139、140包拢在一起,形成一个整块的塑封体。上述第二涂覆物质形成了第二涂覆层133。该整块的塑封体可包括第二涂覆层133、第一涂覆层108、分立的半导体晶粒139、140,以及引线框架116的部分。所述步骤S15可以将分立的半导体晶粒139、140,以及引线框架116的裸露部分覆盖起来。引线框架116的一部分和分立半导体晶粒139、140的部分覆盖层141和142被贴装于第二贴膜121的粘性表面143上,因此,这些区域免予裸露。第一涂覆物质和第二涂覆物质的材料可以是相同的。第二涂覆物质可以与分立半导体晶粒139和140表面的第一涂覆物质的裸露部分相融合。第二涂覆物质可以附着于分立半导体晶粒139和140表面的第一涂覆物质的裸露部分上。例如,位置126和127是环绕分立半导体晶粒139的区域,该区域内可能会发生两种涂覆物质的融合和粘附。为了清楚起见,环绕另一半导体晶粒的区域128和129在附图6也被表示出来。
附图7,参考步骤S15,去除塑封体表面的贴膜。所述贴膜包括第二贴膜121。此步骤可省略。
附图8,参考步骤S16,切割上述整块的塑封体,得到独立的封装完毕的半导体晶粒130和131。在器件139和140之间,通过位置132切割该塑封体,形成独立的封装完毕的半导体晶粒130和131。
下面结合附图对本发明所述之薄型四侧扁平无引脚封装方法的另一个具体实施方式做详细说明。
如附图9所示为本发明所述之薄型四侧扁平无引脚封装方法的另一个具体实施方式的工艺流程图。步骤S20,将晶圆的第一表面与第一粘性表面贴装在一起;步骤S21,在所述晶圆的第二表面上进行切割,从而形成凹槽;步骤S22,在晶圆的第二表面生长金属层,使晶圆的表面成为金属;步骤S23,沿着晶圆第二表面的切割槽切割晶圆;步骤S24,通过晶圆的划片槽切割晶圆,从而形成分立的半导体晶粒,每一个分立的半导体晶粒均具有由上一步骤所形成的金属表面;步骤S25,将金属表面同第三粘性表面贴装在一起,从晶圆的第一表面移除第一粘性表面;步骤S26,将分立半导体晶粒的金属表面同第二粘性表面贴装在一起,从而使金属表面不再暴露在外面;步骤S27,采用引线键合的方法将分立半导体晶粒表面的导电触点同对应的引线框架上的导电引脚相连接;步骤S28,涂覆第二粘性表面上方暴露的表面,形成一个整块的塑封体;步骤S29,切割上述整块的塑封体,得到若干个独立的封装完毕的半导体晶粒。
附图10至附图19为本发明所述之薄型四侧扁平无引脚封装方法的另一个具体实施方式的实施步骤示意图。
附图10,参考步骤S20,将晶圆201的第一表面与第一粘性表面贴装在一起。所述第一粘性表面可以为第一贴膜212的粘性表面。所述第一贴膜212为专用于晶圆的贴膜(蓝膜)。
附图11,参考步骤S21,在晶圆201的第二表面上进行切割,从而形成凹槽216和217。所述切割可以是沿着晶圆表面的若干条划片槽进行。凹槽216和217提供了位于晶圆背面的、在生长金属层后可用于后续工艺进行对准操作的信息。
附图12,参考步骤S22,在晶圆201的第二表面生长金属层,使晶圆201的表面成为金属。所述之生长金属层的步骤可以在晶圆201的第二表面形成一个可辨认的沟道221和222,从而提供了一个可以用来进行对准操作的表面。
附图13,参考步骤S23,沿着晶圆201第二表面的切割槽切割晶圆。沿晶圆201背面上的若干条划片槽进行切割,形成具有一高度和一宽度的切口切割槽223和224。切口223和224的位置可以在凹槽216和217的中心,覆盖了凹槽216和217。
切口223和224可以比凹槽216和217更宽并且更深。切口223和224可以具有比凹槽216和217大的高度,但该高度要小于整个晶圆的总厚度,包括金属层,以免该切割穿透整个晶圆。所述步骤可以包括根据可辨认的沟道221和222对晶圆进行对准操作,以用于切割晶圆201。
附图14,参考步骤S24,通过晶圆的划片槽切割晶圆,从而形成分立的半导体晶粒225、226和227,每一个分立的半导体晶粒均具有由上一步骤所形成的金属表面。此图仅示出了半导体晶粒226的完整结构,半导体晶粒225和227与226的结构类似,在此图中并未完全表示出来。225和227通过晶圆201的背面的若干条划片槽进行切割。该切割形成分立的半导体晶粒225、226和227。每个半导体晶粒相应的具有晶圆201的金属表面的一部分218、219以及220。此步骤形成了切口228和229。切口228可以具有比切口223小的宽度。切口223和切口228在宽度上的差距在晶粒225、226和227的侧面形成了台阶状的结构。该台阶可有助于保护半导体晶粒225、226和227在后续的步骤执行完毕后仍在封装体内,不会滑脱。此步骤可能会部分切穿晶圆的第一贴膜212,但不会切穿整个第一贴膜212。
附图15,参考步骤S25,将金属表面同第三粘性表面贴装在一起,从晶圆的第一表面移除第一粘性表面。在第三贴膜213上贴装金属层218、219以及220,并且从晶圆201的另一面移除第一贴膜212。该步骤将晶圆第一贴膜212上的分立半导体晶粒225、226以及227转移到贴膜213上,准备进行晶粒的贴装步骤S26。
附图16,参考步骤S26,将分立半导体晶粒225、226和227的金属表面同第二粘性表面贴装在一起,从而使金属表面不再暴露在外面。所述第二粘性表面由第二贴膜214提供。分立半导体晶粒225、226和227从第三贴膜213表面选取,置于第二贴膜214的粘性表面上。贴膜214的粘性表面可以贴装有引线框架230。分别将半导体晶粒225、226和22单独置于引线框架230的框体内。
附图17,参考步骤S27,采用引线键合的方法将分立半导体晶粒225、226和227表面的导电触点同对应的引线框架230上的导电引脚相连接。所述引线框架230与分立半导体晶粒225、226和227的金属表面均贴装在粘性表面上。此步骤与上一个具体实施方式中的步骤S13相似,图5中的标号139、140、122、123、124以及125分别对应于图17中的标号226、227、233、234、235以及236。
附图18,参考步骤S28,涂覆第二粘性表面上方暴露的表面,形成一个整块的塑封体。使用涂覆物质涂覆第二贴膜214的粘性表面上的裸露区域,形成一个整块的塑封体247。该整块的塑封体247可以包括涂覆物质、金属层的一部分、分立半导体晶粒226和227、以及引线框架230的一部分。此步骤还可以进一步包括涂覆暴露的分立半导体晶粒226和227的表面与引线框架230,所述引线框架230的一部分与分立半导体晶粒226和227的金属表面的一部分被贴装在粘性表面上,上述被贴装的部分是不暴露出来的。分立半导体晶粒226和227侧面的台阶有助于帮助该分立半导体晶粒一直保持在该涂覆物质内,不会滑脱。
附图19,参考步骤S29,切割上述整块的塑封体247,得到若干个独立的封装完毕的半导体晶粒238和239。通过半导体晶粒226和227之间的位置240切割引线框架230,以形成若干个独立的封装完毕的半导体晶粒238和239。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (17)
1.一种薄型四侧扁平无引脚封装方法,其特征在于,包括如下步骤:
采用第一涂覆物质涂覆晶圆的第一表面,即背面,形成连续的覆盖层;
将晶圆切割成若干个分立的半导体晶粒,每一个分立的半导体晶粒的表面都具有从上述连续覆盖层中切割下来的覆盖层;
将若干个分立的半导体晶粒的覆盖层贴装在一个粘性膜的表面上;
采用第二涂覆物质涂覆粘性表面上方暴露的表面,第二涂覆物质将贴装在粘性表面的半导体晶粒包拢在一起,形成一个整块的封装体;
切割上述整块的封装体,得到若干个独立的封装完毕的半导体晶粒。
2.根据权利要求1所述的薄型四侧扁平无引脚封装方法,其特征在于,所述粘性表面贴有引线框架,将分立的半导体晶粒的覆盖层贴装在贴装表面上的步骤包括分别将每一个半导体晶粒单独置于引线框架的框体内。
3.根据权利要求1所述的薄型四侧扁平无引脚封装方法,其特征在于,进一步包括如下步骤:
采用引线键合的方法将分立半导体晶粒表面的导电触点同对应的引线框架上的导电引脚相连接,所述引线框架与分立半导体晶粒覆盖层均贴装在粘性膜上。
4.根据权利要求1所述的薄型四侧无引脚封装方法,其特征在于,所述涂覆粘性表面上方暴露的表面的步骤包括涂覆暴露的分立半导体晶粒表面与引线框架,所述引线框架的一部分与分立半导体晶粒表面覆盖层的一部分被贴装在粘性表面上,上述被贴装的部分是不暴露出来的。
5.根据权利要求1所述的薄型四侧扁平无引脚封装方法,其特征在于,所述第一涂覆物质与第二涂覆物质的材料是相同的。
6.根据权利要求1所述的薄型四侧扁平无引脚封装方法,其特征在于,所述第二涂覆物质与第一涂覆物质的一部分相融合。
7.根据权利要求1所述的薄型四侧扁平无引脚封装方法,其特征在于,所述第二涂覆物质与第一涂覆物质的一部分粘附在一起。
8.一种薄型四侧扁平无引脚封装方法,其特征在于,包括如下步骤:
将晶圆的第一表面,即正面,与第一粘性表面,即蓝膜,贴装在一起;
在晶圆的第二表面,即背面,生长金属层,使晶圆的表面成为金属;
通过晶圆的划片槽切割晶圆,从而形成分立的半导体晶粒,每一个分立的半导体晶粒均具有由上一步骤所形成的金属表面;
将分立半导体晶粒的金属表面同第二粘性表面,即框架上粘性膜表面,贴装在一起,从而使金属表面不再暴露在外面;
引线键合;
涂覆第二粘性表面上方暴露的表面,形成一个整块的塑封体;
切割上述整块的塑封体,得到若干个独立的封装完毕的半导体晶粒。
9.根据权利要求8所述的薄型四侧扁平无引脚封装方法,其特征在于,进一步包括如下步骤:
在所述晶圆的第二表面上进行切割,从而形成凹槽;
所述之生长金属层的步骤可以在第二表面上形成一个可辨认的沟道,从而提供了一个用来进行对准操作的表面。
10.根据权利要求8所述的薄型四侧扁平无引脚封装方法,其特征在于,进一步包括如下步骤:
在所述通过晶圆的划片槽切割晶圆的步骤之前,沿着晶圆第二表面的切割槽切割晶圆,从而形成一个高度小于晶圆厚度的第一切割槽。
11.根据权利要求10所述的方形扁平无引脚封装方法,其特征在于,所述对晶圆的第二次切割产生的第二切割槽的宽度小于第一切割槽的宽度,从而在切割的位置形成台阶。
12.根据权利要求8所述的薄型四侧扁平无引脚封装方法,其特征在于,所述第一粘性表面由第一晶圆贴膜提供,第一晶圆贴膜具有一定的厚度,所述对晶圆进行切割时,也对第一晶圆贴膜的一部分进行切割。
13.根据权利要求8所述的薄型四侧扁平无引脚封装方法,其特征在于,所述引线框架与第二粘贴表面贴装在一起,所述将分立半导体晶粒的金属表面粘贴在第二粘性表面包括分别将每一个半导体晶粒单独置于引线框架的框体内。
14.根据权利要求13所述的薄型四侧扁平无引脚封装方法,其特征在于,所述涂覆第二粘性表面上方暴露的表面的步骤,包括涂覆暴露的分立半导体晶粒表面与引线框架,所述引线框架的一部分与分立半导体晶粒的金属表面的一部分被贴装在粘性表面上,上述被贴装的部分是不暴露出来的。
15.根据权利要求8所述的薄型四侧扁平无引脚封装方法,其特征在于,进一步包括在通过划片槽划片的步骤之后,再次贴装分立的半导体晶粒,所述再次贴装包括如下步骤:
在通过划片槽划片之后,将金属表面同第三粘性表面贴装在一起;
从晶圆的第一表面移除第一粘性表面。
16.根据权利要求15所述的薄型四侧扁平无引脚封装方法,其特征在于,所述贴装分立半导体晶粒的金属表面的步骤中,包括从第三粘性表面上选取分立的半导体晶粒。
17.根据权利要求8所述的薄型四侧扁平无引脚封装方法,其特征在于,所述引线键合步骤详细如下:
采用引线键合的方法将分立半导体晶粒表面的导电触点同对应的引线框架上的导电引脚相连接,所述引线框架与分立半导体晶粒金属表面均贴装在粘性表面上,这一粘性表面由引线框架自身的预贴膜提供,所述引线框架贴装在粘性表面上操作是在引线框架生产时完成的。
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US12/109,635 US7713784B2 (en) | 2008-03-13 | 2008-04-25 | Thin quad flat package with no leads (QFN) fabrication methods |
US12/728,914 US8008128B2 (en) | 2008-03-13 | 2010-03-22 | Thin quad flat package with no leads (QFN) fabrication methods |
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CN102064117A (zh) * | 2010-11-19 | 2011-05-18 | 上海凯虹电子有限公司 | 小尺寸芯片的封装方法 |
CN103824783A (zh) * | 2012-10-01 | 2014-05-28 | Nxp股份有限公司 | 包封晶片级芯片规模(wlcsp)基座封装 |
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CN102299083B (zh) | 2010-06-23 | 2015-11-25 | 飞思卡尔半导体公司 | 薄半导体封装及其制造方法 |
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CN103972073B (zh) * | 2014-04-18 | 2016-12-07 | 丽智电子(昆山)有限公司 | 芯片背面及侧面涂布保护材料的方法 |
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CN102064117A (zh) * | 2010-11-19 | 2011-05-18 | 上海凯虹电子有限公司 | 小尺寸芯片的封装方法 |
CN102064117B (zh) * | 2010-11-19 | 2013-09-11 | 上海凯虹电子有限公司 | 小尺寸芯片的封装方法 |
CN103824783A (zh) * | 2012-10-01 | 2014-05-28 | Nxp股份有限公司 | 包封晶片级芯片规模(wlcsp)基座封装 |
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US20090233401A1 (en) | 2009-09-17 |
US8008128B2 (en) | 2011-08-30 |
US7713784B2 (en) | 2010-05-11 |
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US20100178733A1 (en) | 2010-07-15 |
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