CN101484995B - 用于完整传动系的芯片模块 - Google Patents
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- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000004891 communication Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 15
- 238000003466 welding Methods 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000012858 resilient material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
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Abstract
公开了一种芯片模块(300)。它包括电路基板(50)、包括安装在电路基板上的功率晶体管的半导体管芯(60(a)、60(b))、以及无源电子元件(80)。无源电子元件与半导体管芯电连通,并与半导体管芯热连通。
Description
发明背景
功率模块是可购得的。虽然这些功率模块是有效的,但是可作许多改进。例如,降低常规模块的覆盖区域是合乎需要的。常规功率模块包含许多电子元件,包括功率MOSFET(金属氧化物半导体场效应晶体管)、控制集成电路(IC)、电容器、电阻器和电感器。随着对更小、更多功能的电子器件的需求增大,需要降低这些功率模块的覆盖面积和总尺寸。
此外,常规功率模块包含功率晶体管。功率晶体管可产生非常大量的热,且功率晶体管的工作范围可取决于其散热的能力。虽然改进的散热可通过将带散热片的热沉附连到功率晶体管来实现,但是热沉是昂贵且占地的。将大的、带散热片的热沉添加到功率模块会增大功率模块的尺寸和成本。
提供可为功率变换器(或其他类型的电气应用)集成各个部件的改进的芯片模块是合乎需要的。由芯片模块占据的空间可被最小化,且芯片模块比常规功率模块具有更好的散热特性和功率密度特性。
本发明各实施例单独地或共同地解决这些问题及其它问题。
发明概要
本发明各实施例涉及芯片模块、用于形成芯片模块的方法、以及包括芯片模块的电组件。
本发明的一个实施例涉及芯片模块。芯片模块包括电路基板、包括安装在电路基板上的功率晶体管的半导体管芯、以及与半导体管芯电连通的无源电子元件。无源电子元件可以是具有线圈的电感器,且可与半导体管芯热连通。无源电子元件可堆叠在功率晶体管的顶部,以使无源电子元件可在功率模块中既作热沉又作电子元件。通过提供此安排,由芯片模块占据的空间被最小化,此外芯片模块的散热和功率密度特性相比常规功率模块被改进。
本发明的另一实施例涉及用于形成芯片模块的方法。该方法包括获得电路基板、将包括功率晶体管的半导体管芯安装在电路基板,以及使无源电子元件电耦合到半导体管芯。电耦合的无源电子元件与半导体管芯热连通,且可为功率晶体管起热沉的作用。
本发明的另一实施例涉及芯片模块。芯片模块包括电路基板、安装在电路基板上的半导体管芯、以及包括堆叠在半导体管芯上的线圈的电子元件。电子元件与半导体管芯电和热连通。线圈可为功率晶体管起热沉的作用。
本发明其他实施例涉及包括上述芯片模块的电组件。
以下参考附图和详细描述更详细地描述本发明的这些及其它实施例。
附图简述
图1示出根据本发明的实施例的安装在母板上的芯片模块的侧视图。
图2示出BGA型半导体管芯封装的侧面剖视图。
图3示出图2所示的半导体管芯封装的顶部透视图。
图4示出根据本发明实施例的芯片模块的立体图。
图5示出可使用根据本发明实施例的芯片模块实现的示例性电路。
在附图中,相同的附图标记指示相同的元件,此外在附图中,有些部件可不按比例绘制。为便于说明,有些部件可比其他部件更大地示出。
详细描述
根据本发明实施例的芯片模块可包括多个电部件。电部件可形成整个电气系统的基本部分或可构成整个电系统。例如,同步降压转换器中的传动系(power train)可被集成到单个模块。例如,根据本发明实施例的芯片模块可包括BGA(球栅阵列)MOSFET封装、驱动器(或控制器IC或控制器系统)、电感器、电阻器和电容器(例如旁路电容器和自举电容器)。
在示例性芯片模块中,芯片模块可具有与电感器的水平尺寸基本相同的水平尺寸,且可以仅稍高于电感器的高度。电感器可在芯片模块中为MOSFET起热沉的作用,同时还在降压转换器中起功能电部件的作用。
如在此所使用的,术语“芯片模块”或“模块”可指可安装到母板等上的电部件的单个的分立集合。
图1示出包括安装在母板10上的芯片模块300的电组件500。母板10可以是标准印刷电路板等。
芯片模块300可形成诸如同步降压转换器之类的更复杂系统的至少一部分。虽然在此申请中详细描述了同步降压转换器,但是本发明各实施例可被用于其他电应用而不限于同步降压转换器。根据本发明各实施例的电组件还可与包括个人计算机、服务器、移动计算和通信设备等的任何数量的电气设备一起使用。
在图1中,为简化说明,示出一个芯片模块300。然而可以理解其他模块和器件(未示出)也可被安装在母板10以形成其他类型的电组件。
图1所示的芯片模块300包括可具有一个或多个芯片封装60(a)、60(b)的多层电路基板50,以及一个或多个安装在其上的无源部件30。如图1所示,芯片封装60(a)、60(b)可包含能使它们连接到基板50的第一表面的焊接结构60(a)-1、60(b)-1(例如第一组焊接结构)。弹性绝缘层90被置于芯片封装60(a)、60(b)、以及一个或多个无源部件30上。
电感器80在弹性绝缘层90上。在此示例中,电感器80可包括外壳和置于外壳内的线圈(未示出)。线圈使用诸如导线、引脚等之类的电连接器电耦合到多层电路基板50(并因而至管芯封装60(a)、60(b))。以下参考图4更详细地描述这些电连接器。
再次参考图1,附加的焊接结构40(例如第二组焊接结构)位于多层电路基板50的第二表面下方并与其接触。它们使多层电路基板50电和机械连接到母板10。在其他各实施例中,其他类型的电连接器(例如引脚、导电柱等)可代替或添加至焊接结构40使用。
焊接结构40可或可不被包括在芯片模块300中。例如,焊接结构40可存在于电路基板50下方,且可在安装到母板10之前在衬底50的第二表面上,且可因此形成芯片模块300的一部分。替换地,焊接结构40可在将芯片模块300安装到母板10之前存在于母板10上,且可因此未必是芯片模块300的一部分。
以下更详细地描述芯片模块300的各个部分。
多层电路基板50可包括任何适当数量的绝缘和导电层。在一些实施例中,多层电路基板50可以是使用常规PCB制造方法制造的印刷电路板(PCB)。
多个电部件被安装在多层电路基板50上。电部件可被封装或不被封装,且可包括诸如功率晶体管(例如功率MOSFET)之类的有源器件和/或一个或多个包括诸如电容器之类的无源器件的无源部件。
如在此所使用的,术语“有源器件”或“有源部件”包括其在经受电流或电压时显示出增益(放大)和/或控制特性的器件或部件,或将输入信号能量通过与来自辅助电源的能量的交互作用转换成输出信号能量的器件。术语“无源器件”包括诸如电感器或电容器之类的不具有放大或控制特性的器件。
在图1中,两个或更多个半导体管芯封装60(a)、60(b)可被安装在电路基板50上。半导体管芯封装60(a)、60(b)可包括功率晶体管管芯封装、控制器IC封装等的任何适当的组合。半导体管芯封装60(a)、60(b)在此示例中可分别包括第一和第二管芯。虽然两个管芯封装60(a)、60(b)在此示例中被示出,但是在其他各实施例中,可以只有一个管芯封装或大于两个管芯封装。
功率晶体管封装可包括含有垂直功率晶体管的半导体管芯。示例性的垂直功率晶体管例如在美国专利No.6,274,905和6,351,018中被描述,这两个专利被转让给本申请的同一受让人且为所有目的它们通过引用被完整结合于此。垂直功率晶体管包括VDMOS晶体管。VDMOS晶体管是具有两个或更多个通过扩散形成的半导体区的MOSFET。它具有源极区、漏极区和栅极。该器件是垂直的,因为源极区和漏极区位于半导体管芯的相反两面。栅极可以是沟槽栅极结构或平面栅极结构,且在与源极区同一表面形成。沟槽栅极结构是优选的,因为沟槽栅极结构相比平面栅极结构较窄并占据较少空间。在运行期间,在VDMOS器件中从源极区流向漏极区的电流与管芯表面基本垂直。在其他实施例中,可使用诸如水平晶体管之类的其他类型的晶体管。在水平晶体管中,电流在管芯内从源极区到漏极区水平地流动。
功率晶体管封装优选是BGA(或球栅阵列)型封装。BGA封装和其他无引线封装是优选的,因为它们由于对下面的电路基板提供更直接的连接(与具有模制壳的有引线芯片封装相比)而很紧凑并最小化杂散电容和电感。BGA型封装可使用具有垂直或水平功率晶体管的半导体管芯。
示例性BGA型封装的侧视剖面图在图2中示出。如图2所示,半导体管芯封装60可具有可以是杯子形状的导电载体100。导电载体100包括含有边缘表面106的外围凸起边缘区,其中该边缘区和底部限定空腔。导电载体100可由铜、铝、或任何其他适当的导电和导热材料制成。在其他实施例中,载体可以采用具有一只或多只脚的导电夹形式,或者甚至是圆锥凸点。
参考图2,半导体管芯102被放置在空腔内,且半导体管芯102的上表面与载体100的边缘区表面106基本共面。管芯附连材料104(例如焊料)被用来使管芯102的背表面附连到由载体100限定的空腔的底部。
焊接结构108(例如焊球)的阵列是在管芯102的上表面和边缘区表面106上。如图3所示,焊接结构108的阵列可包括一个栅极焊接结构108-2G,多个源极焊接结构108-2、以及多个漏极焊接结构108-1。漏极焊接结构108-1围绕源极焊接结构108-2和栅极焊接结构108-2G。此外,漏极焊接结构108-1通过载体100电连接到管芯102的背表面的漏极端子。源极和栅极焊接结构108-2和108-2G分别连接到管芯102的上表面的源极和栅极端子。
从图3显然可见,BGA型封装可类似倒装芯片“倒装”,且然后安装到印刷电路板等。BGA型封装具有薄的外部轮廓,且是小型的。热可从管芯102经由载体100发散,并到外部散热结构(例如上述的电感器)或到外部环境。
虽然BGA型封装是优选的,但是也可使用其他类型的半导体管芯封装。这些封装可包括MLP型封装、或其他低外部轮廓的功率半导体封装。这些封装可以是有引线或无引线的。此外,作为图3中所示实施例的替换,载体100可具有向外凸缘,藉此边缘表面106用外围凸缘区向外延伸(未示出)。
再次参考图1,一个或多个无源部件30也可与被封装管芯60(a)、60(b)一起被安装在电路基板50上。示例性的无源部件可包括诸如电阻器、电容器等的无源器件。
光学弹性绝缘层90存在于半导体管芯封装60(a)、60(b)上。绝缘层90可以是单层形式且是导热的,但可以是电绝缘和/或可具有高弹体性能。它可包括用导热填充物填充的聚合体弹性材料。优选绝缘层材料是可购得的,且在Bergquist公司的商品名为SilpadTM下出售。弹性绝缘层90可被预制成并符合由安装在电路基板50上的各种部件产生的略微不均匀的外形。在其他各实施例中,代替使用预制层,可能在管芯封装60(a)、60(b)上设置导热和绝缘材料,且此后硬化它以凝固它。
电感器80存在于绝缘层90上。电感器80可包括具有铁氧体或铁粉核的布线线圈。电感器80通过导热绝缘层90与功率半导体管芯封装60(a)、60(b)热连通,以使由管芯封装60(a)、60(b)中的管芯生成的热通过电感器80发散。在此示例中,导热绝缘层90与管芯封装60(a)、60(b)以及电感器80接触。这就最大化了从管芯封装60(a)、60(b)到电感器80的热传递。在一些情况下,在工作期间,管芯封装60(a)、60(b)的温度可以约与电感器80的温度相同(例如,小于约5℃的温度差异),以使热被尽可能有效地传送。
虽然详细描述了单个电感器80,但可以理解任何其他相对大的无源电子元件可被堆叠在管芯封装60(a)、60(b)上。例如,变压器线圈等相对较大并具有好的散热特性,所以诸如这些之类的电子元件也可被堆叠在管芯封装60(a)、60(b)上。
相比半导体管芯封装60(a)、60(b),电感器是具有好的导热特性的相对较大的部件。通过将电感器80堆叠在发热半导体管芯封装60(a)、60(b)的顶部,可使这些电部件以最有效的空间配置被排列,同时还有效地使用电感器80的传热特性。因为热被更有效地发散,所以可能将功率半导体管芯封装60(a)、60(b)中的功率晶体管推进到比它们原本能达到的更高的性能级别。例如,通过从半导体管芯封装60(a)、60(b)去除更多的热,就可使更多的电流流经半导体管芯封装60(a)、60(b)中的半导体管芯。
图4示出根据本发明实施例的芯片模块300的立体图。在图1和图4中,相同的附图标记指示相同的元件,且相同元件的描述适用于此。在图4中,电感器80包括线圈80(a)和罩住线圈的外壳80(b)。在此示例中,铁芯(未示出)可存在于线圈80(a)中。侧导体98可被用来使电路基板50与线圈80(a)电耦合。另一侧导体(未示出)可在芯片模块300的相反侧,且可使线圈80(a)连接到电路基板50。外壳80(b)可由诸如铜或铝之类的导热材料制成。
在从图4显然可见,芯片模块300即使包含多个电部件且可有效地散热,它也是非常紧凑的并具有低的外部轮廓。如图4所示,芯片模块300的高度仅略微大于电感器80的高度,而芯片模块300的覆盖面积很小并基本对应于电感器80的水平尺寸。例如,图4所示的芯片模块300的高度可以仅大于电感器80的高度1mm,且芯片模块300的覆盖面积与电感器80的覆盖面积相同。在一些实施例中,芯片模块300可具有小于约1立方英寸、或甚至0.5立方英寸的尺寸,藉此使芯片模块300适用于诸如计算机之类的电子设备。
因为由本发明各实施例提供的有效的部件排列和改进的散热,所以芯片模块的功率密度(即每立方英寸的瓦特数)可以大于常规芯片模块的功率密度的两倍。在一些实施例中,芯片模块可具有小于1立方英寸的尺寸,且可以1.3伏特提供(至少)350瓦特的功率、或以2.6伏特提供(至少)1500瓦特。类似大小但没有上述堆叠电感器布置的芯片模块具有小于这些值约一半的功率密度。
许多图4所示类型的芯片模块可被用在个人计算机的母板等上。它们可被布置在也被安装在母板上的微处理器周围。微处理器在其上可具有风扇或其他常规冷却机制。从风扇流出的空气将进一步冷却芯片模块。
根据本发明各实施例的芯片模块可使用任何适当的装配工艺形成。在一实施例中,一种用于形成芯片模块的方法包括获得电路基板、将包括功率晶体管的半导体管芯安装在电路基板,以及使无源电子元件电耦合到半导体管芯。无源电子元件因此与半导体管芯热连通。
再次参考图1,可首先制造或以其他方式获得电路基板50。包括印刷、蚀刻等的常规印刷电路板技术可被用来形成电路基板50。
一旦获得电路基板50,各种电部件30、60(a)、60(b)可使用焊料、导电粘合剂等安装到电路基板50。如需要,则可预制造和购得电部件。
然后,绝缘层90可被放置在被安装电子元件30、60(a)、60(b)的顶部。压力可被施加到绝缘层90,以使它填充电子元件30、60(a)、60(b)之间的低凹处。
一旦绝缘层90安装到电子元件30、60(a)、60(b)上,电感器80就可被放置在绝缘层90的顶部。一个或多个导线(参见98图4)或其他导体然后可被用来使电感器80中的线圈的端部电耦合到电路基板50。芯片模块300可因此形成。
如果焊料40不是已存在于电路基板50的底面上,则可将它置于其上,然后再将芯片模块300安装到母板10上。替换地,焊料可被放置在母板10上,且芯片模块300可被安装到焊料覆盖的母板10上。
图5示出与同步降压转换器电路相关联的示例性电路。图5所示的所有部件可存在于根据本发明实施例的芯片模块中。电路包括驱动MOSFET M1和M2的栅极的驱动器212。MOSFET M1和M2可被封装在BGA型封装或如上所述的其他类型的封装中。电路也包括含有电容器C1、C2、C3和电阻器R1的多个无源部件。功率电感器224连接到MOSFET M2的漏极和MOSFET M1的源极之间的节点。如上所述,功率电感器224可被堆叠在MOSFET M1和M2的顶部。
虽然详细描述了同步降压转换器,但是根据本发明各实施例的芯片模块可被用在许多不同的最终应用中(推式(push)、挽式(pull)、返驰式转换器等)。这些应用通常使用包括线圈的电子元件(例如电感器、变压器等),以及至少一个开关器件。开关器件是相对薄的,且可被放置在包含线圈的较大电部件的下方。
本发明各实施例具有许多其他优点。第一,模块的总覆盖面积约是同样的分立解决方案的总覆盖面积的一半。第二,本发明各实施例可以40安培按1.5V输出电压提供每立方英寸约650瓦特的功率密度。这在PC竞技场上是空前的功率密度。第三,电感器设置在BGA MOSFET的顶部上将导致在具有空气流动的环境中的更优的热性能。第四,本发明各实施例提供了灵活的设计。不同布局的传动系可以相同方式集成。第五,本发明各实施例可快速满足用户特定需求。第六,本发明各实施例对母板是可回流焊的。第七,本发明各实施例可通过挑选和放置机制被容易地操作。第八,本发明各实施例是可扩展到覆盖3-50安培的范围的模块的大家族,以覆盖在此范围内的所有负载应用。
上述任何实施例和/或其任何特征可与任何其他一个或多个实施例和/或一个或多个特征结合,而不背离本发明的范围。
以上说明书是示例性的而非限制性的。本发明的许多变体对本领域的技术人员在仔细查看本公开后是显而易见的。因此,本发明的范围不应参考以上描述来确定,而相反应当参考所附权利要求以及其全部范围或等效方案来确定。
诸如“上方”、“下方”、“顶部”、“底部”等之类的术语被用来指的是具体实施例,如它们在附图中示出的。这些术语可指或不指实际实施例中的各种元件的绝对位置。
对“一”、“一个”或“该”的叙述旨在表示“一个或多个”,除非有具体地相反指示。
上述所有专利、专利申请、公开和描述为所有目的通过引用完整结合于此。没有一项被视为是现有技术。
Claims (23)
1.一种芯片模块,包括:
电路基板;
包括安装在所述电路基板上的功率晶体管的半导体管芯;以及
堆叠在所述半导体管芯上、并与所述半导体管芯电和热连通的无源电子元件,其中所述无源电子元件被配置为暴露于空气流,因此它驱散由所述半导体管芯所产生的热量。
2.如权利要求1所述的芯片模块,其特征在于,所述无源电子元件是电感器。
3.如权利要求1所述的芯片模块,其特征在于,进一步包括使所述半导体管芯电和机械耦合到所述电路基板的多个焊接结构。
4.如权利要求1所述的芯片模块,其特征在于,所述功率晶体管是功率MOSFET。
5.如权利要求1所述的芯片模块,其特征在于,所述半导体管芯是第一半导体管芯,且所述功率晶体管是第一功率晶体管,且其中所述芯片模块包括第二半导体管芯,其中所述第二半导体管芯包括第二功率晶体管,且其中所述第一和第二半导体管芯存在于球栅阵列(BGA)型半导体管芯封装中。
6.如权利要求5所述的芯片模块,其特征在于,所述芯片模块形成同步降压转换器电路的至少一部分。
7.如权利要求1所述的芯片模块,其特征在于,所述无源电子元件是第一无源电子元件,且其中所述芯片模块包括第二无源电子元件,其中所述第二无源电子元件被安装在所述电路基板上。
8.如权利要求1所述的芯片模块,其特征在于,进一步包括置于所述半导体管芯和所述电路基板的第一表面之间的第一组焊接结构,以及位于所述电路基板的所述第二表面的第二组焊接结构。
9.如权利要求1所述的芯片模块,其特征在于,进一步包括所述无源电子元件和所述半导体管芯之间的弹性、导热材料。
10.一种电组件,包括:
母板;以及
安装在所述母板上的如权利要求1所述的芯片模块。
11.一种用于形成芯片模块的方法,包括:
获得电路基板;
将包括功率晶体管的半导体管芯安装到所述电路基板;以及
使无源电子元件电耦合到所述半导体管芯,其中所述无源电子元件此后与所述半导体管芯热连通并被配置为暴露于空气流,因此它驱散由所述半导体管芯所产生的热量。
12.如权利要求11所述的方法,其特征在于,所述无源电子元件是电感器。
13.如权利要求11所述的方法,其特征在于,将所述半导体管芯安装到所述电路基板包括将所述半导体管芯倒装安装到所述电路基板。
14.如权利要求11所述的方法,其特征在于,所述功率晶体管是功率MOSFET。
15.如权利要求11所述的方法,其特征在于,所述半导体管芯存在于球栅阵列型半导体管芯封装中。
16.如权利要求11所述的方法,其特征在于,进一步包括使用所述模块形成同步降压转换器电路。
17.如权利要求11所述的方法,其特征在于,还包括:
进一步包括在将所述无源电子元件电耦合到所述半导体管芯之前,在所述半导体管芯上设置弹性、导热材料。
18.如权利要求11所述的方法,其特征在于,所述电路基板包括第一表面和第二表面,且其中所述方法进一步包括将一组焊接结构设置在所述第二表面上。
19.一种用于形成电组件的方法,包括:
获得如权利要求1所述的芯片模块;以及
将所述芯片模块安装到母板。
20.如权利要求19所述的方法,其特征在于,所述功率晶体管是功率MOSFET。
21.一种芯片模块,包括:
电路基板;
安装到所述电路基板的半导体管芯;以及
包括堆叠在所述半导体管芯上的线圈、并与所述半导体管芯电和热连通的电子元件,其中所述电子元件被配置为暴露于空气流,因此它驱散由所述半导体管芯所产生的热量。
22.如权利要求21所述的芯片模块,其特征在于,所述半导体管芯包括功率MOSFET且所述电子元件是电感器。
23.如权利要求21所述的芯片模块,其特征在于,进一步包括使所述半导体管芯电和机械耦合到所述电路基板的多个焊接结构。
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US11/427,906 US7656024B2 (en) | 2006-06-30 | 2006-06-30 | Chip module for complete power train |
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CN (1) | CN101484995B (zh) |
DE (1) | DE112007001446T5 (zh) |
TW (1) | TW200802782A (zh) |
WO (1) | WO2008005614A2 (zh) |
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-
2006
- 2006-06-30 US US11/427,906 patent/US7656024B2/en active Active
-
2007
- 2007-04-25 KR KR1020097001168A patent/KR20090034889A/ko not_active Application Discontinuation
- 2007-04-25 WO PCT/US2007/067426 patent/WO2008005614A2/en active Application Filing
- 2007-04-25 CN CN2007800247214A patent/CN101484995B/zh not_active Expired - Fee Related
- 2007-04-25 JP JP2009518413A patent/JP2009543349A/ja not_active Withdrawn
- 2007-04-25 DE DE112007001446T patent/DE112007001446T5/de not_active Withdrawn
- 2007-05-07 TW TW096116095A patent/TW200802782A/zh unknown
-
2009
- 2009-12-14 US US12/637,496 patent/US7875498B2/en active Active
Also Published As
Publication number | Publication date |
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US7656024B2 (en) | 2010-02-02 |
KR20090034889A (ko) | 2009-04-08 |
CN101484995A (zh) | 2009-07-15 |
DE112007001446T5 (de) | 2009-05-07 |
US20080001279A1 (en) | 2008-01-03 |
JP2009543349A (ja) | 2009-12-03 |
WO2008005614A2 (en) | 2008-01-10 |
TW200802782A (en) | 2008-01-01 |
US7875498B2 (en) | 2011-01-25 |
US20100093132A1 (en) | 2010-04-15 |
WO2008005614A3 (en) | 2008-06-19 |
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