CN101484989B - 智能聚合物复合材料对集成电路封装的应用 - Google Patents
智能聚合物复合材料对集成电路封装的应用 Download PDFInfo
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- CN101484989B CN101484989B CN2007800247318A CN200780024731A CN101484989B CN 101484989 B CN101484989 B CN 101484989B CN 2007800247318 A CN2007800247318 A CN 2007800247318A CN 200780024731 A CN200780024731 A CN 200780024731A CN 101484989 B CN101484989 B CN 101484989B
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Abstract
智能聚合物复合材料对于集成电路封装的应用。
Description
技术领域
本发明涉及微电子学领域,更具体地(但非排他地)涉及纳米粒子填充的复合材料对于集成电路封装的应用。
背景技术
集成电路设计的进步产生了更高的工作频率,更多数目的晶体管,以及更小物理体积的装置。这种持续的趋势产生了集成电路和电气连接的面密度(area density)不断增加。至今,这种趋势也导致了功率的增加和热流装置的增加,这种趋势预计将延续到可预见的未来。此外,用于电子封装中的材料通常具有不同的热膨胀系数。由于正常使用、存储和制造情况引起的温度波动,不同的热膨胀系数可导致如材料破裂(内聚破坏)和在邻接材料的区域中的分层(粘合破坏)等机械破坏。除此之外,其他许多原因也可能导致机械破坏,例如在运输到系统或主板集成商、系统或主板装配车间期间遭受到冲击和振动,或交付给终端用户期间遭受到冲击和振动。
例如,焊料凸点常常电子地和机械地将集成电路管芯耦合到封装衬底。此外,封装衬底可由焊料球电子地和机械地连接到印刷电路板。封装衬底可具有与管芯和/或印刷电路板不同的热膨胀系数。当温度发生变化时,由于不同的热膨胀系数,可在焊料球和焊料凸点内产生机械应力(stress)。在某些情形下,焊料球和焊料凸点在热应力下破裂(内聚破坏)。一旦破裂开始,内聚破坏可以一定的速度传播,该速度部分地取决于裂纹的特征尺寸,如裂纹尖端的直径。
一种现有的防止焊料球和焊料凸点破裂的方法包括将固化材料(curable material)分散到焊料球和焊料凸点之间的区域中(“底部填充”)。当使用底部填充时,在其它情况下由焊料球和焊料凸点承担的一些应力将由底部填充材料承担,因此减小焊料球或焊料凸点破裂的可能性。在使用当前可用技术的应用中,如果破裂在底部填充内开始,则破裂可通过底部填充和通过焊料球及焊料凸点传播。底部填充材料一般是脆性的,而破裂一旦开始将很容易地传播。另一种现有技术使用具有增加韧性的底部填充材料以延缓破裂传播。增加底部填充复合材料韧性的一些方法包括将第二相添加到固化复合材料,例如通过使用各种的橡胶添加剂的任一种或向复合材料加载微粒无机填料。虽然脆性的底部填充中的破裂的传播速度将比韧性材料中更快,但即使韧性的底部填充材料中的破裂仍将传播。
在其他情形中,封装中的材料的邻接层由于通过焊料球和焊料凸点传来的机械应力可能分层。类似于内聚破坏,粘合破坏可以部分地取决于分层区域的特征尺寸的速度而传播。特性差的金属-聚合物粘合会加速粘合破坏的传播。部分地处理分层破坏的一种众所周知的方法包括将粘合涂层涂到材料界面。提高聚合物和金属的组合的粘合性的备选的方法包括表面磨粗或加偶联剂,例如硅醚。与裂纹传播相似,分层在界面涂层是脆性时比在界面涂层是韧性时可更容易传播。同样的,虽然在韧性界面涂层中的分层传播可能比在脆性界面涂层要慢,但粘合破坏仍然会传播。
材料破裂和分层还可能在除了由于温度周期变化产生的膨胀和收缩外的情形下发生。破裂和分层破坏可能出现的情况很多,包括如封装在使用期间的动态翘曲,来自温度周期变化的疲劳,还有运输、装配、搬运过程中产生的冲击和振动。
附图简述
图1示出智能聚合物复合材料在对集成电路进行封装中的不同阶段。
图2示出关于在材料之一包含智能聚合物复合材料的集成电路封装中的邻接材料之间的增强的粘合力的可能机制。
图3示出在粘合破坏、内聚破坏、和在不同的成分的邻接材料的区域中用来提高界面粘合力等情况下可移动的纳米粒子在智能聚合物复合材料中的非均匀的分散。
图4示出包含智能聚合物复合材料底部填充的集成电路封装横截面视图。
图5示出在集成电路封装中使用智能聚合物复合材料的方法。
图6示出使用包含智能聚合物复合材料的集成电路封装的系统。
图7示出在现有技术复合材料中包含裂纹的区域中的机械应力的图;
图8示出在智能聚合物复合材料中包含裂纹的区域中的机械应力的图;
图9示出在智能聚合物复合材料涂层中的裂纹尖端张开位移(CTOD)和现有技术聚合物涂层中的CTOD的比较的图。
图10示出对于聚酰亚胺基体中不同大小和数量的纳米粒子填料,在聚酰亚胺和硅之间的接合中的接合抗剪强度(bond shearstrength)的图。
具体实施方式
本文公开使用智能聚合物复合材料的方法,和包括智能聚合物复合材料的设备和系统。
在下列详述中,参照形成本文一部分的附图,其中相似的标号代表相似的部件,遍布这些部件和这些部件中以示例的方式示出其中可实施本发明的具体实施例。在不脱离所提出的实施例的预期的范围的情况下,可利用其他实施例以及可进行结构的和逻辑的改变。也应该注意到,可以运用指示和附注(如上、下、顶、底、基本面、背面等)来方便附图的讨论,但不是旨在限制本发明的实施例的应用。因此,不应以限制的意义理解随后的详细描述,而本发明的实施例的范围是由所附权利要求及其等同物进行限定的。
智能聚合物复合材料
对“填料”的引用是指一种本体材料(bulk material),该材料由在其他材料中结合的或基本上分散遍布于其它材料的单个微粒组成。通常,填料的使用导致结合填料的材料的一种或多种本体材料性质的改变。
对“纳米粒子”的引用是指一种特征长度为大约500纳米(nm)或更少的粒子,相对于更大的微粒子。
对“智能聚合物复合材料”的引用是指一种包含可在聚合物复合材料中移动的纳米粒子填料的聚合物复合材料。在智能聚合物复合材料的一些实施例中,纳米粒子填料会对外部激励有反应,如高能表面、电脉冲、温度变化或磁脉冲的产生。
图1示出智能聚合物复合材料140在对集成电路进行封装中的不同阶段。智能聚合物复合材料140可通过将未修改过的可移动的纳米粒子填料材料100(其中单个纳米粒子102的表面104是未修改过的),或者修改过的可移动的纳米粒子填料材料120(其中单个纳米粒子102的表面106是修改过的)分散遍布于聚合物基体108来形成。形成后,智能聚合物复合材料140可同集成电路封装160中的不同材料110邻接。
热固性材料如环氧树脂、双马来酰亚胺、热固性聚氨酯、三聚氰酸酯(cyanourate ester)、硅酮,或热塑性材料如聚酰亚胺、液晶聚合物或类似材料可形成聚合物基体108。这些材料可以是固态或液态树脂。纳米粒子填料100或120可以是有机的、无机的或金属的。例如,纳米粒子填料100或120材料可以是二氧化硅、氧化铝、氧化锆、二氧化钛(titania)、碳纳米管或上述各项的组合。
智能聚合物复合材料与有机的、无机的(如硅)、或金属的(如铜)材料邻接时,展现了与使用未含纳米粒子填料的聚合物相比较时增强的粘合力。图2示出了关于区域200中的增强的粘合力的可能机制(详图250),其中材料之一包含智能聚合物复合材料。分散有纳米粒子206的聚合物基体202与材料204邻接。邻接材料304的表面粗糙度由脊308和谷310来示出。增强的粘合力将来自于纳米粒子312与脊308和谷310的机械联锁。
备选地,增强的粘合力可部分地由于表面化学性质而发生。例如,即使与含有更大的微尺度填料材料的聚合物复合材料和更大的表面粗糙度之间的粘合力相比,智能聚合物复合材料和具有低表面粗糙度的邻接材料304之间的粘合力可展示增强的粘合力。在本体材料边界处智能聚合物复合材料甚至比那些具有同样的微-(与纳-相对)粒子填料加载的聚合物具有更高的表面能。智能聚合物复合材料更高的表面能可导致增强的粘合力。纳米粒子填料具有更高的表面能(非常高的面容比),这能说明在本体材料边界的智能聚合物复合材料的表面能的全面增加和观测到的粘合力的增强。通过用等离子处理邻接材料能进一步提高粘合力。图10示出对于不同大小和数量的粘土纳米粒子填料,智能聚合物复合材料(带有聚酰亚胺基体)和硅之间的接合中的接合抗剪强度的图1000。
因为与周围的聚合物基体的链松弛长度(chain relaxationlength)有关的纳米粒子的小几何形状,纳米粒子能在智能聚合物复合材料内迁移。纳米粒子移动性可能需要聚合物基体在其玻璃化转变温度之上。如上所述,纳米粒子具有高的面容比,因此有比常规填料更高的表面能。与由聚合物链上的粒子引起的构象张力(conformational strain)协作的高表面能可以是纳米粒子迁移到高能界面背后的驱动力的一些。因为填料和聚合物之间的界面的化学性质可增强或阻碍移动性,纳米粒子填料材料和聚合物基体材料的不同组合可展示不同的纳米粒子移动性。纳米粒子移动性可通过应用例如修改的表面能、温度改变、或电脉冲或磁脉冲的激励而任意触发。例如,纳米粒子能具有能用来触发它们移动性的表面电荷。
纳米粒子填料的移动性可通过修改纳米粒子填料的、聚合物基体的或两者的界面的表面来进一步提高。使用现有功能组(如二氧化硅上的硅醇(silanols on silica))交联填料与基体或将纳米粒子表面与聚合物基体相容能提高纳米粒子的移动性,从而提高智能聚合物复合材料的性能。
图3示出暴露于粘合破坏312、内聚破坏422和智能聚合物复合材料和邻接材料324的区域的聚合物基体304、314、326中的纳米粒子填料308、318、330的示范的浓度。图3的智能聚合物复合材料也包括了微粒子填料306、318、328,例如二氧化硅。聚合物基体304、314、326中的纳米粒子308、318、330的移动性部分地导致高能区域310、320、332中的增加的纳米粒子浓度。
一些智能聚合物复合材料也可自我修复内聚或粘合破坏。纳米粒子,由于它们的尺寸,能修复很小的裂纹。例如,图3示出带有粘合破坏312的组件300和带有内聚破坏的组件340。如上所述,这些破坏区域引起纳米粒子的更高的浓度,从而能钝化裂纹并抑制传播。因为纳米粒子可以比聚合物回转半径小但比裂纹尖端半径大,他们能卡在裂纹尖端。这就阻止了裂纹传播。图7示出在包含裂纹的区域中的现有技术的聚合物材料中的应力场的图700。作为对比,图8示出在包括裂纹的区域中的智能聚合物复合材料中的应力场的图800,其峰值应力明显更低。图8中峰值应力的减小是源自纳米粒子填料对裂纹生长的抑制。图9示出了智能聚合物复合材料(“填充的”)中与现有技术的聚合物(“未填充的”)相比减小的裂纹尖端张开位移的图900。
智能聚合物复合材料应用
智能聚合物复合材料可在用于集成电路的微电子封装中找到成功的应用,集成电路如微处理器、多核微处理器、图形处理器、存储器控制器、ASIC、芯片组和上述各项的组合。例如,集成电路封装可将本体聚合物用于底部填充、模压化合物(mold compound)、非模压化合物的密封剂、电介质层、管芯粘接(die attach)、密封胶或某些组合。备选地,本体聚合物能用作如在底部填充和管芯钝化层之间的邻接材料的区域的涂层,以阻止分层。智能聚合物复合材料可以基本上相似的方式用作这些本体聚合物的代替或附加。
图4示出了封装的多个实施例之一400,其包含集成电路和不同成分的邻接材料的至少一个区域。该实施例可包括通过焊料凸点406的阵列电耦合到集成电路管芯402的封装衬底404。该焊料凸点406的阵列可形成此后由底部填充材料填充的空隙,底部填充材料由含有分散的纳米粒子414的聚合物基体412形成。此外,用热界面材料410热耦合到管芯402的集成散热器408可在实施例中出现。
备选地,集成电路封装可结合应用为对于邻接的、但不同的材料的区域的表面涂层或密封剂的智能聚合物复合材料,以阻碍分层。例如,在管芯粘接邻接管芯的区域提供了多种示范实施例之一,其中可将智能聚合物复合材料用到邻接的、但不同的材料的区域。智能聚合物复合材料的其他用途可包括底部填充、模压化合物、非模压化合物的密封剂、电介质层、管芯粘接、密封胶、应力补偿层或某些组合。在某些使用中,纳米粒子填料仅占到小于智能聚合物复合材料大约20%的重量。
在某些实施例中,裂纹在制造、运输、搬运或正常使用过程中可在智能聚合物复合材料内形成。然而,智能聚合物复合材料内的裂纹可抑制裂纹并阻止裂纹的传播,从而提高封装的可靠性。
图5示出其中封装结合智能聚合物复合材料的使用的封装集成电路的方法。方法500包括修改纳米粒子填料的表面(502),准备聚合物基体(504),以及通过组合纳米粒子填料和聚合物基体形成智能聚合物复合材料(506)。方法还包括结合智能聚合物复合材料(508)和激励纳米粒子移动性(510)。
图6示出多种可能的系统实施例之一的图示。包含集成电路600的封装可包括智能聚合物复合材料。在一个实施例中,包含集成电路600的封装可包括类似于图4所示的智能聚合物复合材料底部填充材料。集成电路可包括微处理器或专用集成电路(ASIC)。备选地,芯片组(如图形、声音和控制芯片组)或存储器中可见的集成电路也可依照本发明的实施例来进行封装。
对于类似于图6中描绘的实施例,如图所示,系统60也可包括主存储器602,图形处理器604,大容量存储装置606,通过总线610彼此耦合输入/输出模块608。存储器602的例子包括但不限于静态随机访问存储器(SRAM)和动态随机访问存储器(DRAM)。大容量存储装置606的例子包括但不限于硬盘驱动器、闪存驱动器、光盘驱动器(CD)、数字通用盘驱动器(DVD)等等。输入/输出模块608的例子包括但不限于键盘、光标控制装置、显示器、网络接口等等。总线610的例子包括但不限于外围设备控制接口(PCI)总线、PCI高速总线、工业标准结构(ISA)总线等等。在不同的实施例中,系统60可以是无线移动电话、个人数字助理、便携PC、平板计算机、笔记本PC、台式计算机、机顶盒、音频/视频控制器、DVD播放器、网络路由器、网络交换装置或服务器。
虽然本文为了描述实施例而示出和描述了具体的实施例,但本领域技术人员将认识到,在不脱离本公开的范围的情况下,计划取得相似目的的广泛的各种代替和/或等效实现可替代已示出和描述的具体实施例。例如,备选实施例可存在于可在管芯和集成散热器之间使用智能聚合物复合材料的层的情况。另一个实施例可在封装衬底和印刷电路板之间应用智能聚合物复合材料。而另一个实施例可存在于智能聚合物复合材料形成芯片级封装上的焊料球的底部填充的情况。
本领域技术人员将轻松认识到,本发明可使用非常广泛的实施例来实现。这个详细的描述旨在涵盖本文讨论的实施例的任何改变或变化。因此,显然意图是,本发明仅由权利要求及其等同物来限制。
Claims (26)
1.一种用于集成电路封装的设备,包括:
集成电路的封装,所述封装还包括一个或多个不同成分的邻接材料的区域,其中所述材料之一包括含有聚合物基体的聚合物材料,所述聚合物基体具有高能区;及
可移动的纳米粒子填料,基本上分散遍布于所述聚合物基体,而在所述高能区中具有增加的浓度。
2.如权利要求1所述的设备,其中所述集成电路还包括包含微处理器、图形处理器、存储器控制器、ASIC、芯片组和上述各项的组合的组中所选的一个。
3.如权利要求1所述的设备,其中所述聚合物基体基本上是由环氧树脂、热固性聚氨酯、三聚氰酸酯、硅酮、聚酰亚胺、丙烯酸脂、双马来酰亚胺、液晶聚合物和上述各项的组合组成的组中所选的一个。
4.如权利要求1所述的设备,还包括通过修改的方式修改包括所述纳米粒子填料和所述聚合物基体的组中的一个或多个的界面的表面。
5.如权利要求1所述的设备,其中所述聚合物基体中的纳米粒子的移动性可通过应用场电位的脉冲部分地激励,所述场电位选自由温度、电、磁和上述各项的组合组成的场电位的组。
6.如权利要求1所述的设备,其中不同成分的邻接材料的区域包括部分地由纳米粒子填充的分层裂纹,所述分层裂纹表示所述高能区。
7.如权利要求1所述的设备,其中聚合物材料内的区域包括部分地由纳米粒子填充的内聚破坏,所述内聚破坏表示所述高能区。
8.如权利要求1所述的设备,其中纳米粒子由选自有机的和无机的纳米粒子的组的纳米级材料组成,所述组由碳纳米管、纳米级二氧化硅、纳米级氧化铝、纳米级二氧化钛、纳米级氧化锆和上述各项的组合组成。
9.如权利要求1所述的设备,其中单个示范的纳米粒子的物理几何形状是选自由球状和片状组成的组中的一个。
10.如权利要求1所述的设备,其中所述纳米粒子填料的重量小于所述聚合物材料20%的重量。
11.如权利要求1所述的设备,其中所述纳米粒子填料的示范纳米粒子的特征长度小于所述聚合物材料的回转半径。
12.如权利要求1所述的设备,其中所述可移动的纳米粒子填料基本上分散遍布于聚合物材料的聚合物基体,所述聚合物材料形成由电介质层、底部填充、管芯粘接、模压化合物、非模压化合物的密封剂、密封胶、应力补偿层、邻接材料的区域的涂层、以及上述各项的组合组成的组中所选的一个。
13.一种用于集成电路封装的方法,包括:
通过将可移动的纳米粒子填料基本上分散遍布于聚合物基体来形成智能聚合物复合材料,其中所述聚合物基体具有高能区,并且其中所述可移动的纳米粒子填料在所述高能区具有增加的浓度;以及
将所述智能聚合物复合材料包括在集成电路封装中。
14.如权利要求13所述的方法,其中所述集成电路包括微处理器。
15.如权利要求13所述的方法,其中所述聚合物基体基本上是由环氧树脂、热固性聚氨酯、三聚氰酸酯、硅酮、聚酰亚胺、丙烯酸脂、双马来酰亚胺、液晶聚合物和上述各项的组合组成的组中所选的一个。
16.如权利要求13所述的方法,还包括通过修改的方式修改包括所述纳米粒子填料和所述聚合物基体的组中的一个或多个的界面的表面。
17.如权利要求13所述的方法,其中所述聚合物基体中的纳米粒子移动性可通过应用场电位的脉冲部分地激励,所述场电位选自由温度、电、磁和上述各项的组合组成的场电位的组。
18.如权利要求13所述的方法,其中纳米粒子由选自有机的和无机的纳米粒子的组的纳米级材料组成,所述组由碳纳米管、纳米级二氧化硅、纳米级氧化铝、纳米级二氧化钛、纳米级氧化锆和上述各项的组合组成。
19.如权利要求13所述的方法,其中所述可移动的纳米粒子填料基本上分散遍布于聚合物材料的聚合物基体,所述聚合物材料形成由电介质层、底部填充、管芯粘接、模压化合物、非模压化合物的密封剂、密封胶、应力补偿层、邻接材料的区域的涂层、以及上述各项组合组成的组中所选的一个。
20.一种用于集成电路封装的系统,包括:
集成电路的封装,所述封装还包括一个或多个不同成分的邻接材料的区域,其中所述材料之一包括其中具有高能区的智能聚合物复合材料;
基本上分散遍布于所述智能聚合物复合材料的可移动的纳米粒子填料,而在所述高能区具有增加的纳米粒子填料的浓度;以及
耦合到所述封装的大容量存储装置。
21.如权利要求20所述的系统,还包括:
耦合到所述集成电路的动态随机访问存储器;以及
耦合到所述集成电路的输入/输出接口。
22.如权利要求21所述的系统,其中所述输入/输出接口包括网络接口。
23.如权利要求20所述的系统,其中所述集成电路是处理器。
24.如权利要求23所述的系统,其中所述系统是由机顶盒、数字通用盘播放器、服务器、个人计算机、个人数字助理、蜂窝电话、网络交换装置和上述各项的组合组成的组中所选的一个。
25.如权利要求20所述的系统,其中所述纳米粒子填料部分地填充包括在所述封装中的材料中的裂纹。
26.如权利要求20所述的系统,其中所述智能聚合物复合材料形成由电介质层、底部填充、管芯粘接、模压化合物、非模压化合物的密封剂、密封胶、应力补偿层、邻接材料的区域的涂层、以及上述各项组合组成的组中所选的一个。
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US8243391B2 (en) | 2008-09-26 | 2012-08-14 | Hitachi Global Storage Technologies, Netherlands B.V. | Slider and suspension composite fiber solder joints |
US20100295173A1 (en) * | 2009-05-21 | 2010-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite Underfill and Semiconductor Package |
TWI550017B (zh) * | 2009-09-14 | 2016-09-21 | 納美仕有限公司 | 高密度互連覆晶用之底部填充料 |
JP5532419B2 (ja) * | 2010-06-17 | 2014-06-25 | 富士電機株式会社 | 絶縁材、金属ベース基板および半導体モジュール並びにこれらの製造方法 |
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US8920919B2 (en) | 2012-09-24 | 2014-12-30 | Intel Corporation | Thermal interface material composition including polymeric matrix and carbon filler |
US9230921B2 (en) | 2013-10-08 | 2016-01-05 | Globalfoundries Inc. | Self-healing crack stop structure |
US20150125646A1 (en) | 2013-11-05 | 2015-05-07 | Espci Innov | Self-Healing Thermally Conductive Polymer Materials |
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US7025607B1 (en) * | 2005-01-10 | 2006-04-11 | Endicott Interconnect Technologies, Inc. | Capacitor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate |
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