CN101459063A - Manufacturing method for transistor shallow junction - Google Patents

Manufacturing method for transistor shallow junction Download PDF

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Publication number
CN101459063A
CN101459063A CNA2007100944319A CN200710094431A CN101459063A CN 101459063 A CN101459063 A CN 101459063A CN A2007100944319 A CNA2007100944319 A CN A2007100944319A CN 200710094431 A CN200710094431 A CN 200710094431A CN 101459063 A CN101459063 A CN 101459063A
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China
Prior art keywords
ion
time
junction
shallow junction
injection
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Pending
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CNA2007100944319A
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Chinese (zh)
Inventor
钱文生
刘俊文
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CNA2007100944319A priority Critical patent/CN101459063A/en
Publication of CN101459063A publication Critical patent/CN101459063A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a preparing method for a shallow junction of a transistor, which can be realized by twice ion implantations, wherein one of the ion implantations is N type ion implantation and the other is P type ion implantation, the required junction depth can be obtained by respectively controlling energy and dose of the twice ion implantations, thereby bringing convenience to control the junction depth of the transistor, which can meet requirements upon various junction depths and particularly can realize ultra-shallow junctions.

Description

The manufacture method of transistor shallow junction
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of transistor shallow junction manufacture method.
Background technology
Along with the continuous development of semiconductor technology, characteristic size is more and more littler, requires more and more littler to transistorized junction depth (Junction Depth).At present, generally all be to realize more and more littler junction depth by the energy that reduces the ion injection of source leakage (Sourceand Drain) district.But ion injects and can produce the tail effect, thereby make the control of junction depth cannot reach the state of absolute ideal, and the injection of the ion of ultra-low calorie can cause the effect that some are bad again, such as low-yield down, bigger reflection can take place at silicon face in the ion that injects, so a part of ion source-drain area of just failing to inject.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of manufacture method of transistor shallow junction, can conveniently carry out the control of junction depth, and then realizes the making of junction depth for the following super shallow junction of about 100nm.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of transistor shallow junction, may further comprise the steps:
The ion injection first time is carried out in the position that needs to form shallow junction on silicon;
The ion injection second time is carried out in the position that needs to form shallow junction on silicon;
And described first time, ion injected and ion injects for the second time once be that P type ion injects, and another time is the injection of N type ion.
The present invention is owing to adopted technique scheme, has such beneficial effect, promptly inject by carrying out two secondary ions, wherein once be that N type ion injects, another time is that P type ion injects, and the energy and the dosage that inject by this two secondary ion of control respectively, obtain needed junction depth, thereby made things convenient for control, can satisfy the requirement of various junction depth, especially can realize super shallow junction the transistor junction depth.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is for making the schematic flow sheet of shallow junction according to the present invention;
Fig. 2 a is the injection ion concentration-depth distribution curve synoptic diagram of an example when making shallow junction in the prior art;
Fig. 2 b is the injection ion concentration-depth distribution curve synoptic diagram of an example when making shallow junction according to the present invention.
Embodiment
In semiconductor fabrication, when needs formed P type knot or N type knot, in one embodiment, as shown in Figure 1, the present invention can make shallow junction by the following method:
At first, the ion injection first time is carried out in the position that needs to form shallow junction on silicon, and at this moment the ion that is injected can be that P type ion also can be a N type ion;
Then, the ion injection second time is carried out in the position that needs to form shallow junction on silicon, if ion injection for the first time is P type ion, the then current ion that injects then should be a N type ion; And if the N type ion that injects for the first time, the then current ion that injects then should be a P type ion.
Inject for above-mentioned two secondary ions, what realize if desired is P type knot, then should guarantee the energy of the energy of P type ion injection less than the injection of N type ion; Otherwise what realize if desired is N type knot, then should guarantee the energy of the energy of N type ion injection less than the injection of P type ion.
In addition, by said process as can be known, two secondary ions are infused in the degree of depth that concentration exists together mutually in the silicon and are junction depth (i.e. the intersection point place that two secondary ions inject in ion concentration-depth distribution curve synoptic diagram), therefore, by controlling energy and the dosage that above-mentioned two secondary ions inject respectively, can realize desired various junction depth in the present invention; And, by comparison diagram 2a (junction depth of being realized is 500 dusts) and two examples of Fig. 2 b (junction depth of being realized is 300 dusts) as can be seen, the junction depth that twice ion injection method finally obtained is much all more shallow than only injecting the getable junction depth of institute by primary ions traditionally, therefore, the method for injecting by above-mentioned two secondary ions can realize super shallow junction easily.
After forming shallow junction, just can carry out the successive process of semiconductor device manufacturing.

Claims (3)

1, a kind of manufacture method of transistor shallow junction is characterized in that, may further comprise the steps:
The ion injection first time is carried out in the position that needs to form shallow junction on silicon;
The ion injection second time is carried out in the position that needs to form shallow junction on silicon;
And described first time, ion injected and ion injects for the second time once be that P type ion injects, and another time is the injection of N type ion.
2, according to the manufacture method of the described transistor shallow junction of claim 1, it is characterized in that, described first time ion inject and the second time ion be infused in the degree of depth that silicon concentration exists together mutually and be junction depth.
According to the manufacture method of the described transistor shallow junction of claim 2, it is characterized in that 3, the energy and the dosage of the described ion injection first time and ion injection for the second time depend on the junction depth that will obtain.
CNA2007100944319A 2007-12-11 2007-12-11 Manufacturing method for transistor shallow junction Pending CN101459063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA2007100944319A CN101459063A (en) 2007-12-11 2007-12-11 Manufacturing method for transistor shallow junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2007100944319A CN101459063A (en) 2007-12-11 2007-12-11 Manufacturing method for transistor shallow junction

Publications (1)

Publication Number Publication Date
CN101459063A true CN101459063A (en) 2009-06-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007100944319A Pending CN101459063A (en) 2007-12-11 2007-12-11 Manufacturing method for transistor shallow junction

Country Status (1)

Country Link
CN (1) CN101459063A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227114A (en) * 2013-04-08 2013-07-31 上海华力微电子有限公司 Method for forming ultra-shallow junction plane

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227114A (en) * 2013-04-08 2013-07-31 上海华力微电子有限公司 Method for forming ultra-shallow junction plane
CN103227114B (en) * 2013-04-08 2015-12-09 上海华力微电子有限公司 A kind of method forming ultra-shallow junctions

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Open date: 20090617