CN101459078A

CN101459078A - Producing method for shallow junction in transistor device

Info

Publication number: CN101459078A
Application number: CNA2007100944304A
Authority: CN
Inventors: 钱文生; 刘俊文
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-12-11
Filing date: 2007-12-11
Publication date: 2009-06-17

Abstract

The invention discloses a method of manufacturing shallow junctions for transistors, which includes steps of forming source/drain region recesses, forming source/drain regions composed of polysilicon on silicon oxide inside the source/drain region recesses, thereby realizing well controlling junction depth of the source/drain regions of the transistor, realizing fabrication of ultra shallow junction, and greatly reducing junction capacitance of the source/drain regions.

Description

Producing method for shallow junction in the transistor device

Technical field

The present invention relates to semiconductor device and make the field, relate in particular to producing method for shallow junction in a kind of transistor device.

Background technology

Along with the continuous development of semiconductor technology, transistorized characteristic size is constantly dwindled, and requires transistorized junction depth also along with constantly dwindling, even requires to reach super shallow junction.The technology that realization at present constantly reduces junction depth is (as the device of Fig. 1) realized by the energy that continuous reduction ion injects, but the injection of ultra-low calorie can cause some problems, simultaneously since ion inject intrinsic tail effect, make that the realization of super shallow junction is relatively more difficult.When realizing super shallow junction, also wish to reduce transistorized junction capacitance.

Summary of the invention

The technical problem to be solved in the present invention provides producing method for shallow junction in a kind of transistor device, can realize that junction depth is the making of the following super shallow junction of about 100nm, and can reduce transistorized junction capacitance.

For solving the problems of the technologies described above, the invention provides producing method for shallow junction in a kind of transistor device, comprising:

On silicon substrate, form grid, and form side wall in the both sides of described grid;

Etching is carried out in the position that described silicon substrate top is positioned at the grid curb wall both sides, forms the source-drain area groove;

Deposit layer of silicon dioxide layer carries out etching to described silicon dioxide layer then on silicon chip, makes only to remain with silicon dioxide layer in described source-drain area groove;

Deposit one deck polysilicon again on silicon chip carries out etching to described polysilicon then, makes to have only on the silicon dioxide layer in the described source-drain area groove to remain with polysilicon, the source-drain area of transistor formed;

Described source-drain area is carried out ion inject the line activating of going forward side by side.

The present invention is owing to adopted technique scheme, has such beneficial effect, promptly by on silicon substrate, forming the source-drain area groove, in described source-drain area groove, form the source-drain area of the polysilicon formation that is positioned on the silicon dioxide then, thereby realized finely to get oxide-semiconductor control transistors source-drain area junction depth, realize the making of junction depth, and realized can be from reducing the purpose of source-drain area junction capacitance to a great extent for the super shallow junction below about 100nm.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the sectional structure chart according to the device of prior art making;

Fig. 2 is the schematic flow sheet according to an embodiment of the method for the invention;

Fig. 3 a-3d is for making the sectional structure chart of shallow junction according to Fig. 2.

Embodiment

In one embodiment, as shown in Figure 2, producing method for shallow junction may further comprise the steps in the transistor device of the present invention:

At first, shown in Fig. 3 a, on silicon substrate, form grid, and form side wall in the both sides of described grid.

Secondly, shown in Fig. 3 b, etching is carried out in the position that described silicon substrate top is positioned at the grid curb wall both sides, forms the source-drain area groove, wherein the degree of depth of the groove of institute's etching depends on the degree of depth of the shallow junction that will realize, is the summation of the thickness of the silicon dioxide layer of subsequent deposition and polysilicon.

The 3rd step, deposit layer of silicon dioxide layer on silicon chip, and the thickness of this silicon dioxide layer should be less than the degree of depth of described source-drain area groove, depend primarily on the junction capacitance that will realize, use known photoetching technique then, described silicon dioxide layer is carried out etching, make only to remain with silicon dioxide layer in described source-drain area groove, cross-section structure at this moment is shown in Fig. 3 c.

In the 4th step, deposit one deck polysilicon again on silicon chip uses known photoetching technique then, described polysilicon is carried out etching, make to have only on the interior silicon dioxide layer of described source-drain area groove to remain with polysilicon, the source-drain area of transistor formed, cross-section structure at this moment is shown in Fig. 3 d.Wherein, the thickness of described polysilicon depends on the degree of depth of the shallow junction that will realize.

The 5th step, choose described source-drain area by a light shield, then described source-drain area is carried out ion and inject, the line activating of going forward side by side, thus finally finish the making of shallow junction of the present invention.Identical to the requirement that will inject ion and prior art source requiring of leaking that ion injects, the type of for example injecting ion depends on the type of device that will realize, for example for nmos pass transistor, the ion that is injected can be phosphonium ion or arsenic ion etc.; For the PMOS transistor, the ion that is injected can be boron ion or boron difluoride etc.The dosage of the ion that injects and energy then depend on the various performance requirements of the device that will realize.As mentioned above, because source-drain area is to be made of the polysilicon that is formed on the silicon dioxide, and the ion that injects can't spread at silicon dioxide layer, therefore the ion in this step injects and can not produce the tail effect, thereby make that the realization of super shallow junction is relatively easy, only need are that the thickness of super shallow junction of required realization is just passable by the THICKNESS CONTROL with polysilicon.

From above-mentioned steps as can be seen, owing to be used for to control as the thickness of the polysilicon of source-drain area, therefore realized the junction depth in Controlling Source drain region preferably, thereby realize the making of super shallow junction, and make the junction capacitance of source-drain area mainly become by said method to mainly contain by polysilicon by the junction capacitance of original PN junction, the junction capacitance that capacity plate antenna constituted that silicon dioxide and silicon substrate form, thickness owing to silicon dioxide in this capacity plate antenna is thicker in addition, and its thickness can control, thereby realized reducing the purpose of source-drain area junction capacitance.

Claims

1, producing method for shallow junction in a kind of transistor device is characterized in that, comprising:

2, according to producing method for shallow junction in the described transistor device of claim 1, it is characterized in that the thickness of described polysilicon depends on the degree of depth of the shallow junction that will realize.