CN101458911B - Data driving device and liquid crystal display device using the same - Google Patents

Data driving device and liquid crystal display device using the same Download PDF

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Publication number
CN101458911B
CN101458911B CN2008101869907A CN200810186990A CN101458911B CN 101458911 B CN101458911 B CN 101458911B CN 2008101869907 A CN2008101869907 A CN 2008101869907A CN 200810186990 A CN200810186990 A CN 200810186990A CN 101458911 B CN101458911 B CN 101458911B
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gray
scale voltage
generating unit
voltage generating
voltage
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CN101458911A (en
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李周洪
宋鸿声
闵雄基
孙勇气
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LG Display Co Ltd
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LG Display Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0666—Adjustment of display parameters for control of colour parameters, e.g. colour temperature
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A gray scale voltage generator includes a voltage dividing resistor string to generate blue (B), red (R), and green (G) gamma voltage signals, the voltage dividing resistor string including a B gamma voltage signal generating section, a R/G gamma voltage generating section, and a common (COM) gamma voltage generating section to individually control a B gray scale voltage and a R/G gray scale voltage to maintain a constant color temperature.

Description

The liquid crystal display of data driven unit and this data driven unit of use
Technical field
The present invention relates to the liquid crystal display of data driven unit and this data driven unit of use, more particularly, relate to the data driven unit of the colour temperature that can compensate the intensity-based level and the liquid crystal display of this data driven unit of use.
Background technology
The application requires the right of priority of the korean patent application No.P2007-129739 of submission on Dec 13rd, 2007, and this sentences the mode of quoting as proof and incorporates its full content into, just as carried out complete elaboration at this.
In general, liquid crystal display is by showing desired image to being formed on the intensity that the liquid crystal material with anisotropy specific inductive capacity between two substrates applies electric field and regulate this electric field with the transmittance of regulating this liquid crystal material.The liquid crystal display of this routine is based in red (R), green (G) and blue (B) data-signal each, comes display gray scale according to the transmittance of red point, green point and Bluepoint.If the red, green and blue data-signal is identical, then identical gray-scale voltage is used for this red, green and blue data-signal.That is, even known red point, green point have different electro-optical characteristics with Bluepoint, also identical gray-scale voltage is used for whole three kinds of colors, thus the problem that causes colour temperature to change with gray level.Colour temperature is recently determined according to the combination of the brightness of the red point, green point and the Bluepoint that form pixel.Yet, when gray level increases or reduce, can not control separately the gray-scale voltage for the red, green and blue data-signal, cause thus colour temperature inhomogeneous in upper and lower gray level region, as shown in Figure 1.
Summary of the invention
Therefore, the present invention relates to the liquid crystal display of a kind of data driven unit and this data driven unit of use, it can overcome one or more problem of bringing because of limitation and the shortcoming of correlation technique basically.
An object of the present invention is to provide a kind of data driven unit and the liquid crystal display that uses this data driven unit that can compensate the colour temperature of intensity-based level.
Supplementary features of the present invention and advantage will be described in the following description and will partly manifest from describe, and perhaps can understand by practice of the present invention.Can realize and obtain purpose of the present invention and other advantages by the structure that particularly points out in written instructions and claim and the accompanying drawing.
In order to realize these and other advantages, according to purpose of the present invention, description as concrete and broad sense, a kind of gray-scale voltage maker comprises: the divider resistance string, it generates blue (B) gamma voltage signal, red (R) gamma voltage signal and green (G) gamma voltage signal, and described divider resistance string comprises: B gamma voltage signal generating unit; R/G gamma voltage generating unit; And public (COM) gamma voltage generating unit, it controls B gray-scale voltage and R/G gray-scale voltage individually to keep constant colour temperature.
On the other hand, a kind of data driven unit for liquid crystal display comprises: control circuit, and it carries out relaying to red (R) data-signal, green (G) data-signal and indigo plant (B) data-signal; The gray-scale voltage maker, it generates gray-scale voltage; Digital processing unit, it latchs described R data-signal, described G data-signal and described B data-signal; And analog processor, it will be converted to from the R data-signal that has latched, G data-signal and the B data-signal that described digital processing unit provides the picture signal that will show in described liquid crystal display, described gray-scale voltage maker comprises: the divider resistance string, it generates R gamma voltage signal, G gamma voltage signal and B gamma voltage signal, and described divider resistance string comprises: B gamma voltage signal generating unit; R/G gamma voltage generating unit; And public (COM) gamma voltage generating unit, it controls B gray-scale voltage and R/G gray-scale voltage individually to keep constant colour temperature.
Should be appreciated that above-mentioned general description and following detailed description are exemplary and explanat, and aim to provide the further explanation of the present invention for required protection.
Description of drawings
Accompanying drawing is included in this manual to provide a further understanding of the present invention, and is attached in this instructions and consists of the part of this instructions, and accompanying drawing shows embodiments of the present invention, and is used from instructions one and explains principle of the present invention.In the accompanying drawing:
Fig. 1 is the figure of the colour temperature of intensity-based level in the illustration correlation technique;
Fig. 2 is the block diagram of structure that schematically shows the data driven unit of first embodiment of the invention;
Fig. 3 is the schematic circuit of exemplary gray scale voltage generator of the data driven unit of first embodiment of the invention shown in Figure 2;
Fig. 4 is the schematic circuit of another representative configuration of gray-scale voltage maker shown in Figure 2;
Fig. 5 is the schematic block diagram of exemplary digital/analog converter shown in Figure 2;
Fig. 6 A be in illustration the first embodiment of the present invention with schematic block diagram based on the example path of the corresponding data of 2 reversing mode of level of the first and second polarity control signals and picture signal;
Fig. 6 B be in illustration the first embodiment of the present invention with the schematic block diagram through the example path of the corresponding data of 2 reversing mode of level of counter-rotating and picture signal based on the first and second polarity control signals;
Fig. 6 C be in illustration the first embodiment of the present invention with schematic block diagram based on the example path of the corresponding data of 1 reversing mode of level of the first and second polarity control signals and picture signal;
Fig. 6 D be in illustration the first embodiment of the present invention with the schematic block diagram through the example path of the corresponding data of 1 reversing mode of level of counter-rotating and picture signal based on the first and second polarity control signals;
Fig. 7 is the figure of the exemplary colour temperature of intensity-based level in the data driven unit of illustration first embodiment of the invention and the liquid crystal display;
Fig. 8 is the schematic circuit of the exemplary gray scale voltage generator of data driven unit second embodiment of the invention;
Fig. 9 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 3rd embodiment of the present invention;
Figure 10 is the schematic circuit of exemplary resistor selector switch shown in Figure 9;
Figure 11 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 4th embodiment of the present invention;
Figure 12 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 5th embodiment of the present invention;
Figure 13 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 6th embodiment of the present invention;
Figure 14 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 7th embodiment of the present invention;
Figure 15 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 8th embodiment of the present invention;
Figure 16 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 9th embodiment of the present invention;
Figure 17 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the tenth embodiment of the present invention;
Figure 18 is the block diagram that schematically shows according to the structure of the data driven unit of the 11 embodiment of the present invention;
Figure 19 is the schematic circuit of exemplary gray scale voltage generator shown in Figure 180;
Figure 20 is the schematic circuit of another representative configuration of gray-scale voltage maker shown in Figure 180;
Figure 21 is the schematic block diagram of exemplary digital/analog converter shown in Figure 180;
Figure 22 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 12 embodiment of the present invention;
Figure 23 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 13 embodiment of the present invention;
Figure 24 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 14 embodiment of the present invention;
Figure 25 is the schematic circuit according to the exemplary gray scale voltage generator of the data driven unit of the 15 embodiment of the present invention; And
Figure 26 is the block diagram that schematically shows liquid crystal display according to an illustrative embodiment of the invention.
Embodiment
The below will describe preferred implementation of the present invention in detail, and example has gone out its example in the accompanying drawings.In possible situation, identical label represents identical or like in whole accompanying drawing.Below in the description of this invention, do not repeat the known function that is incorporated into this and the detailed description of structure.
Fig. 2 is the block diagram of structure that schematically shows the data driven unit of first embodiment of the invention.As shown in Figure 2, the data driven unit 100 of first embodiment of the invention comprises: the controll block 110 to provide red, green and blue data-signal (R, G, B) to it and data controlling signal DCS to carry out relaying from the outside is provided; Be used for generating the gray-scale voltage maker 120 of three looks public gray-scale voltage CV, bluish grey degree step voltage PBV and NBV and red/green gray-scale voltage PRGV and NRGV; The digital processing unit 130 that the data-signal R, the G that provide from controll block 110 and B latched in response to the data controlling signal EN1, the SSC that provide from controll block 110 and SOE is provided; And be used for utilizing gray-scale voltage CV, PBV, NBV, PRGV and NRGV that the analog processor 140 of the picture signal VData with data polarity corresponding with the first and second polarity control signal POL1 that provide from controll block 110 and POL2 will be provided from the latch data RData that digital processing unit 130 provides.
Controll block 110 recovers to provide from the outside N position red, green and blue data-signal R, G and B to it by the data-interface scheme, so that they are corresponding to the data-interface scheme, and red, green and blue data-signal R, G and the B that recovers is offered digital processing unit 130.Controll block 110 is also utilized from the outside and is provided to its data controlling signal DCS control figure processor 130 and each the analog processor 140, and this data controlling signal DCS comprises source initial pulse SSP, source shift clock SSC, source output enable signal SOE and the first and second polarity control signal POL1 and POL2.
As shown in Figure 3, gray-scale voltage maker 120 comprises the first to the 3rd divider resistance string 122,124 and 126.The first divider resistance string 122 comprises the first resistor RR1 that is connected to driving voltage source VDD and is connected in series in first between the first resistor RR1 and the ground voltage supplies VSS to g voltage grading resistor R_1 to R_g.According to utilizing resistor to carry out the voltage that dividing potential drop generates the first divider resistance string 122 is divided into the first district 122a, Second Region 122b and public area 122c.
The first district 122a comprise the first resistor RR1 and be connected to the first resistor RR1 first to e voltage grading resistor R_1 to R_e.(wherein, k1 is the natural number less than j/2) offers respectively the middle dividing potential drop node of the first district 122a to k1 benchmark gamma voltage GMA_1 to GMA_k1 with first in the middle of j the benchmark gamma voltage GMA_j (wherein, j is natural number).For example, the first benchmark gamma voltage GMA_1 can be offered the dividing potential drop node (between RR1 and the R_1) of the generation i gray-scale voltage PBV_i in the middle of the dividing potential drop node of the first district 122a, and the second benchmark gamma voltage GMA_2 can be offered the dividing potential drop node (between R_1 and the R_2) of generation (i-1) the gray-scale voltage PBV_i-1 in the middle of the dividing potential drop node of the first district 122a.And, k1 benchmark gamma voltage GMA_k1 is offered the dividing potential drop node (between R_e-1 and the R_e) of the generation h gray-scale voltage PBV_h in the middle of the dividing potential drop node of the first district 122a.Here, i is 0 to 2 NWherein, N is the figure place (for example, when the figure place of data-signal was 8, i was 255) of data-signal, h less than the natural number of i (for example is, when the figure place of data-signal was 8, h can be 223), and k1 can according in electro-optical characteristic, gamma characteristic and the color temperature characteristic of liquid crystal at least one be configured to less than j/2 natural number (for example, when j=18, k1 can be 2 or 3).The first district 122a provides to analog processor 140 and comprises gray-scale voltage PBV_x on the positive basket of the x of i to h gray-scale voltage PBV_i to PBV_h, described i to h gray-scale voltage PBV_i to PBV_h by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of the first resistor RR1 in the e voltage grading resistor R_e.
Public area 122c comprises that e is to f voltage grading resistor R_e to R_f.(wherein, k2 is less than the natural number of j greater than j/2) offers respectively the middle dividing potential drop node of public area 122c to (k2-1) benchmark gamma voltage GMA_k1+1 to GMA_k2-1 with (k1+1) in the middle of j the benchmark gamma voltage GMA_j.(k1+1) has rule or irregular voltage difference with respect to adjacent benchmark gamma voltage to (k2-1) benchmark gamma voltage GMA_k1+1 to GMA_k2-1 according to electro-optical characteristic, color temperature characteristic and the gamma characteristic of liquid crystal, and is provided for respectively corresponding dividing potential drop node among the 122c of public area.For example, (j/2) benchmark gamma voltage GMA_j/2 is offered the dividing potential drop node of generation the 0th positive three looks public gray-scale voltage PCV_0 in the middle of the dividing potential drop node of public area 122c, and (j/2-1) benchmark gamma voltage GMA_j/2-1 can be offered the dividing potential drop node of generation the first positive three looks public gray-scale voltage PCV_1 (not shown) in the middle of the dividing potential drop node of public area 122c.(k1+1) has rule or the irregular voltage difference with respect to adjacent benchmark gamma voltage to (j/2-2) benchmark gamma voltage GMA_k1+1 to GMA_j/2-2, and is provided for respectively the central dividing potential drop node of generation the 3rd to (h-1) positive three looks public gray-scale voltage PCV_3 (not shown) to PCV_h-1 of dividing potential drop node of public area 122c.(j/2+1) benchmark gamma voltage GMA_j/2+1 is offered the dividing potential drop node of generation the 0th negative three looks public gray-scale voltage NCV_0 in the middle of the dividing potential drop node of public area 122c, and (j/2+2) benchmark gamma voltage GMA_j/2+2 is offered the dividing potential drop node of generation the first negative three looks public gray-scale voltage NCV_1 (not shown) in the middle of the dividing potential drop node of public area 122c.(j/2+3) has rule or the irregular voltage difference with respect to adjacent benchmark gamma voltage to (k2-1) benchmark gamma voltage GMA_j/2+3 to the GMA_k2-1 (not shown), and is provided for respectively the central dividing potential drop node of generation the 3rd to (h-1) negative three looks public gray-scale voltage NCV_3 (not shown) to NCV_h-1 of dividing potential drop node of public area 122c.
This common area 122c supplies to the analog processor 140 includes a first (h-1) positive gray scale voltage PCV_h-1 to 0, including the positive gray scale voltage PCV_0 into y positive three-color common gray scale voltages PCV_y and includes a first 0 negative gray scale voltages NCV_0 to (h-1) negative gray scale voltage NCV_h-1, including the number y negative three-color common gray scale voltages NCV_y, said first (h-1) positive gray scale voltage PCV_h-1 to the 0th positive gray scale voltages are formed by PCV_0 e to f in the first voltage-dividing resistors R_e to R_f each of the two adjacent resistors dividing nodes of the correspondence between the generated dividing said first negative gray scale voltages NCV_0 0 to (h-1) negative gray scale voltage NCV_h-1 are formed by e to f in the first voltage-dividing resistors R_e to R_f each of the two adjacent correspondence between the resistor divider dividing the generated node.For example, when the figure place of data-signal was 8, public area 122c generated and comprises the 0th to the 222nd positive gray-scale voltage PCV_0 to 223 positive three looks public gray-scale voltage PCV_y of PCV_222 and comprise that the 0th to the 222nd negative gray-scale voltage NCV_0 is to 223 negative three looks public gray-scale voltage NCV_y of NCV_222.
Perhaps, can be connected between the dividing potential drop node that generates the 0th positive three looks public gray-scale voltage PCV_0 and the dividing potential drop node that generates the 0th negative three looks public gray-scale voltage NCV_0 by at least one is illusory (dummy) resistor (not shown).
Second Region 122b comprises that the f that is connected in series is to g voltage grading resistor R_f to R_g.K2 in the middle of j the benchmark gamma voltage GMA_j is offered respectively the middle dividing potential drop node of Second Region 122b to j benchmark gamma voltage GMA_k2 to GMA_j.For example, k2 benchmark gamma voltage GMA_k2 is offered the dividing potential drop node (between R_f and the R_f+1) of the generation h gray-scale voltage NBV_h in the middle of the dividing potential drop node of Second Region 122b, and (j-1) benchmark gamma voltage GMA_j-1 can be offered the dividing potential drop node (between R_g-2 and the R_g-1) of generation (i-1) the gray-scale voltage NBV_i-1 in the middle of the dividing potential drop node of Second Region 122b.J benchmark gamma voltage GMA_j can be offered the dividing potential drop node (between R_g-1 and the R_g) of the generation i gray-scale voltage NBV_i in the middle of the dividing potential drop node of Second Region 122b.Here, k2 can be arranged to greater than j/2 less than the natural number of j according in electro-optical characteristic, gamma characteristic and the color temperature characteristic of liquid crystal at least one.For example, k2 can be j-1 or j-2.
Second Region 122b provides to analog processor 140 and comprises h gray-scale voltage NBV_h gray-scale voltage NBV_x on the x of i gray-scale voltage NBV_i the negative basket, described h gray-scale voltage NBV_h to i gray-scale voltage NBV_i by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of f in to g voltage grading resistor R_f to R_g.Here, x the upper gray-scale voltage NBV_x of negative indigo plant has and x the positive blue upward voltage level of the voltage level symmetry of gray-scale voltage PBV_x with respect to the common electric voltage (not shown).
The second divider resistance string 124 comprise the second resistor RR2 between the public area 122c that is connected in series in driving voltage source VDD and the first divider resistance string 122 and have different resistance first to (e-1) at prime/green voltage grading resistor Rr_1 is to Rr_e-1, so that they are connected in parallel to the first district 122a of the first divider resistance string 122.Perhaps, first to (e-1) at prime/some in the Rr_e-1 of green voltage grading resistor Rr_1 can have same resistance.
The second resistor RR2 is connected to driving voltage source VDD.This second resistor RR2 has the large resistance of resistance than the first resistor RR1 of the first divider resistance string 122, the x in just distinguishing with optimization red/green gray-scale voltage PRGV_x.
First to (e-1) at prime/green voltage grading resistor Rr_1 is connected in series between the e voltage grading resistor R_e of the second resistor RR2 and the first divider resistance string 122 to Rr_e-1.Here, the second divider resistance string 124 is except the resistance of the second resistor RR2, and remainder has the structure identical with the structure of the first district 122a of the first divider resistance string 122.Thereby, first to (e-1) at prime/green voltage grading resistor Rr_1 in the Rr_e-1 each have with the first district 122a that is arranged on the first divider resistance string 122 in first to (e-1) voltage grading resistor R_1 to the identical resistance of the corresponding resistance of R_e-1.
One or more positive external voltage PEVi and PEVi-1 and k1 benchmark gamma voltage GMA_k1 are offered the middle dividing potential drop node of the second divider resistance string 124.For example, the i positive gray level external voltage PEVi corresponding with i gray-scale voltage PRGV_i can be offered the dividing potential drop node (between RR2 and the Rr_1) of the generation i gray-scale voltage PRGV_i in the middle of the dividing potential drop node of the second divider resistance string 124, and (i-1) corresponding with (i-1) gray-scale voltage PRGV_i-1 positive gray level external voltage PEVi-1 can be offered the dividing potential drop node (between Rr_1 and the Rr_2) of generation (i-1) the gray-scale voltage PRGV_i-1 in the middle of the dividing potential drop node of the second divider resistance string 124.K1 benchmark gamma voltage GMA-k1 is offered the dividing potential drop node (between Rr_e-1 and the Rr_e) of the generation h gray-scale voltage PRGV_h in the middle of the dividing potential drop node of the second divider resistance string 124.Except positive gray level external voltage (for example, PEVi and PEVi-1) in addition, benchmark gamma voltage (for example, GMA_1 and GMA_2) can also be offered respectively the dividing potential drop node.
The second divider resistance string 124 to analog processor 140 provide comprise i gray-scale voltage PRGV_i to the x of h gray-scale voltage PRGV_h at prime/green on gray-scale voltage PRGV_x, described i gray-scale voltage PRGV_i to h gray-scale voltage PRGV_h by be respectively formed at the second resistor RR2 to the (e-1) at prime/corresponding dividing potential drop node between per two adjacent resistor among the green voltage grading resistor Rr_e-1 carries out dividing potential drop and generates.
The 3rd divider resistance string 126 comprise the 3rd resistor RR3 between the public area 122c that is connected in series in the first divider resistance string 122 and the ground voltage supplies VSS and have different resistance first to (e-1) negative red/green voltage grading resistor Rr_f+2 is to Rr_g, so that they are connected in parallel to the Second Region 122b of the first divider resistance string 122.Perhaps, first to (e-1) negative red/some in the Rr_g of green voltage grading resistor Rr_f+2 can have same resistance.
The 3rd resistor RR3 is connected to the f resistor R_f of the first divider resistance string 122.The 3rd resistor RR3 has the little resistance of resistance than (f+1) voltage grading resistor R_f+1 of the first divider resistance string 122, with the x in the optimization minus zone red/green gray-scale voltage NRGV_x.
First bears red/green voltage grading resistor Rr_f+2 to (e-1) is connected in series between the 3rd resistor RR3 and the ground voltage supplies VSS to Rr_g.Here, the 3rd divider resistance string 126 is except the resistance of the 3rd resistor RR3, and remainder has the structure identical with the structure of the Second Region 122b of the first divider resistance string 122.Thereby, first to (e-1) negative red/green voltage grading resistor Rr_f+2 in the Rr_g each have with the Second Region 122b that is arranged on the first divider resistance string 122 in (f+2) to g voltage grading resistor R_f+2 to the identical resistance of the corresponding resistance of R_g.
K2 benchmark gamma voltage GMA_k2 and one or more negative external voltage NEVi-1 and NEVi are offered the middle dividing potential drop node of the 3rd divider resistance string 126.For example, k2 benchmark gamma voltage GMA-k2 is offered the dividing potential drop node (between RR3 and the R_f) of the generation h gray-scale voltage NRGV_h in the middle of the dividing potential drop node of the 3rd divider resistance string 126, and (i-1) that will be corresponding with (i-1) gray-scale voltage NRGV_i-1 negative gray level external voltage NEVi-1 offers the dividing potential drop node (between Rr_g-2 and the Rr_g-1) of generation (i-1) the gray-scale voltage NRGV_i-1 in the middle of the dividing potential drop node of the 3rd divider resistance string 126.The negative gray level external voltage NEVi of i that will be corresponding with i gray-scale voltage NRGV_i offers the dividing potential drop node (between Rr_g-1 and the Rr_g) of the generation i gray-scale voltage NRGV_i in the middle of the dividing potential drop node of the 3rd divider resistance string 126.Except bearing gray level external voltage (for example, NEVi-1 and NEVi) in addition, benchmark gamma voltage (for example, GMA_j-1 and GMA_j) can also be offered respectively the dividing potential drop node.
The 3rd divider resistance string 126 to analog processor 140 provide comprise h gray-scale voltage NRGV_h to the x of i gray-scale voltage NRGV_i negative red/green on gray-scale voltage NRGV_x, described h gray-scale voltage NRGV_h carries out dividing potential drop to i gray-scale voltage NRGV_i by the corresponding dividing potential drop node between per two adjacent resistor in being respectively formed at the 3rd resistor RR3 to the (e-1) voltage grading resistor Rr_g and generates.
Perhaps, as shown in Figure 4, the second resistor RR2 of the second divider resistance string 124 can be connected in the middle of the dividing potential drop node of the first divider resistance string 122 the positive gray-scale voltage PBV_i of generation i (namely, positive voltage of white) dividing potential drop node (between RR1 and the R_1), but not be connected to driving voltage source VDD.Equally, the g voltage grading resistor Rr_g of the 3rd divider resistance string 126 can be connected in the middle of the dividing potential drop node of the first divider resistance string 122 the negative gray-scale voltage NBV_i of generation i (namely, negative voltage of white) dividing potential drop node (between R_g-1 and the R_g), but not be connected to ground voltage supplies VSS.
Gray-scale voltage maker 120 utilizes the first divider resistance string 122 to generate gray-scale voltage PBV_x and NBV_x and positive and negative three looks public gray-scale voltage CV on the positive and negative basket, and utilize the second and the 3rd divider resistance string 124 and 126 generate positive and negatives red/green upper gray-scale voltage PRGV_x and NRGV_x.In order to compensate colour temperature, among the positive blue upper gray-scale voltage PBV_x each has than each the voltage level of the high predetermined value of voltage level among at prime/green upper gray-scale voltage PRGV_x, and among the negative blue upper gray-scale voltage NBV_x each has than each the voltage level of the low predetermined value of voltage level among negative red/green upper gray-scale voltage NRGV_x.
Offering first of gray-scale voltage maker 120 cushions by the gamma impact damper 125 that is built in the data driven unit 100 to GMA_j to j benchmark gamma voltage GMA_1, to the external unit of data driven unit 100 outsides (for example, data pcb) output, and then again offer gray-scale voltage maker 120.Like this, when using a plurality of data driven unit 100, before providing gamma voltage to corresponding data drive unit 100, for the first deviation compensation gamma voltage to j benchmark gamma voltage GMA_1 to GMA_j.
Digital processing unit 130 comprises shift register 132 and latchs section 134.Shift register 132 in response to source shift clock SSC sequentially be shifted with from the first corresponding enable signal EN1 of the source initial pulse SSP of controll block 110, to generate sampled signal Sam and the sampled signal Sam that generates is offered the section of latching 134.Shift register 132 is bidirectional shift registers.Shift register 132 also generates forward direction carry signal Car (EN2) or backward carry signal Car (EN1), then it is offered outside different data driven units as source initial pulse SSP by controll block 110.
Latch section 134 and latch the red, green and blue data-signal R, the G that provide from controll block 110 and each the B in response to the sampled signal Sam that provides from shift register 132.Then, latch section 134 and in response to source output enable signal SOE the data RData that latchs is offered analog processor 140.Latch section 134 and sequentially latch red, green and blue data-signal R, G and the B corresponding with the output channel number of data driven unit 100.That is, latch section 134 and sequentially latch the data-signal R of first passage to the data-signal B of last passage, and then export simultaneously latch data signal R, G and the B of all passages in response to source output enable signal SOE.
Analog processor 140 comprises digital-to-analog (D/A) converter 142 and output buffer part 144.D/A converter 142 comprises a plurality of data mux blocks that respectively have 12 passages, as shown in Figure 5.Each data mux block all comprises data converter 200, this data converter 200 be used for utilizing on x the positive and negative basket that provides from gray-scale voltage maker 120 gray-scale voltage PBV_x and NBV_x, a y positive and negative three looks public gray-scale voltage PCV_y and NCV_y and x positive and negative red/green upper gray-scale voltage PRGV_x and NRGV_x, the red, green and blue data RData that has latched that inputs to it is converted to respectively red, green and blue picture signal Vdata.Each data mux block also comprises data routing controller 300 and image signal path controller 400, this data routing controller 300 is used for controlling from the first to the 12 input channel Cm-11 to Cm (wherein based on the first and second polarity control signal POL1 and POL2, m is 12 multiple) red to latching of data converter 200, the path of each among the green and blue data RData, and this image signal path controller 400 is used for controlling from data converter 200 to exporting the red of buffer part 144 based on the first and second polarity control signal POL1 and POL2, the path of each among the green and blue images signal Vdata.
Data converter 200 comprises the first to the 12 demoder D1 to D12, and this first to the 12 demoder D1 is included as just (P) demoder and negative (N) demoder that arranges corresponding to 2 reversing mode of level to D12.Here, the first to the 12 demoder D1 to D12 by (P) demoder just, negative (N) demoder, negative (N) demoder and the order repeated arrangement of (P) demoder just.
The first, x at prime/green upper gray-scale voltage PRGV_x and y the positive three looks public gray-scale voltage PCV_y that provides from gray-scale voltage maker 120 is provided each among the 4th, the 5th and the 8th demoder D1, D4, D5 and the D8, will latch red or green data RData and be converted at prime or green picture signal VData.
The second, x negative red/green upper gray-scale voltage NRGV_x and y the negative three looks public gray-scale voltage NCV_y that provides from gray-scale voltage maker 120 is provided each among the 7th, the tenth and the 11 demoder D2, D7, D10 and the D11, will latch red or green data RData and be converted to negative red or green picture signal VData.
X positive blue upper gray-scale voltage PBV_x and y the positive three looks public gray-scale voltage PCV_y that provides from gray-scale voltage maker 120 is provided among the 9th and the 12 demoder D9 and the D12 each, will latch blue data RData and be converted to positive blue images signal VData.
X negative blue upper gray-scale voltage NBV_x and y the negative three looks public gray-scale voltage NCV_y that provides from gray-scale voltage maker 120 is provided among the 3rd and the 6th demoder D3 and the D6 each, will latch blue data RData and be converted to negative blue images signal VData.
Data routing controller 300 based on the first and second polarity control signal POL1 and POL2 control from the first to the 12 input channel Cm-11 to Cm to data converter 200 latch each path the red, green and blue data RData so that the polarity of picture signal is corresponding to 1 of level or 2 reversing mode of level.For this reason, data routing controller 300 comprises the first and second data routing controllers 310 and 320.
The first data routing controller 310 comprises that the first to the tenth data routing selector switch S1 is to S10.The first data routing selector switch S1 comprises the first switch S 1a and second switch S1b, this first switch S 1a is used for latching blue data RData in response to what the second polarity control signal POL2 output offered the 3rd or the 12 input channel Cm-9 or Cm, and this second switch S1b is used for latching blue data RData in response to what the second polarity control signal POL2 output offered the 9th or the 3rd input channel Cm-3 or Cm-9.The first switch S 1a select in response to the first logic state of the second polarity control signal POL2 and export the 3rd input channel Cm-9 latch blue data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 12 input channel Cm latch blue data RData.Second switch S1b select in response to the first logic state of the second polarity control signal POL2 and export the 9th input channel Cm-3 latch blue data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 3rd input channel Cm-9 latch blue data RData.
The second data routing selector switch S2 comprises the first switch S 2a and second switch S2b, this first switch S 2a be used in response to the second polarity control signal POL2 output offer the 4th input channel Cm-8 latch red data RData or offer the 11 input channel Cm-1 latch green data RData, and this second switch S2b be used in response to the second polarity control signal POL2 output offer the tenth input channel Cm-2 latch red data RData or offer the 4th input channel Cm-8 latch red data RData.The first switch S 2a select in response to the first logic state of the second polarity control signal POL2 and export the 4th input channel Cm-8 latch red data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 11 input channel Cm-1 latch green data RData.Second switch S2b select in response to the first logic state of the second polarity control signal POL2 and export the tenth input channel Cm-2 latch red data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 4th input channel Cm-8 latch red data RData.
The 3rd data routing selector switch S3 select in response to the first logic state of the second polarity control signal POL2 and export the 11 input channel Cm-1 latch green data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the tenth input channel Cm-2 latch red data RData.
The 4th data routing selector switch S4 select in response to the first logic state of the second polarity control signal POL2 and export the 12 input channel Cm latch blue data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 9th input channel Cm-3 latch blue data RData.
The 5th data routing selector switch S5 comprises the first switch S 5a and second switch S5b, this first switch S 5a be used in response to the second polarity control signal POL2 output offer the 7th input channel Cm-5 latch red data RData or offer the 8th input channel Cm-4 latch green data RData, and this second switch S5b be used in response to the second polarity control signal POL2 output offer the 8th input channel Cm-4 latch green data RData or offer the 7th input channel Cm-5 latch red data RData.The first switch S 5a select in response to the first logic state of the second polarity control signal POL2 and export the 7th input channel Cm-5 latch red data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 8th input channel Cm-4 latch green data RData.Second switch S5b select in response to the first logic state of the second polarity control signal POL2 and export the 8th input channel Cm-4 latch green data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 7th input channel Cm-5 latch red data RData.
The 6th data routing selector switch S6 comprises the first switch S 6a and second switch S6b, this first switch S 6a be used in response to the second polarity control signal POL2 export the 8th input channel Cm-4 latch green data RData or the 7th input channel Cm-5 latch red data RData, and this second switch S6b be used in response to the second polarity control signal POL2 export the 7th input channel Cm-5 latch red data RData or the 8th input channel Cm-4 latch green data RData.The first switch S 6a select in response to the first logic state of the second polarity control signal POL2 and export the 8th input channel Cm-4 latch green data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 7th input channel Cm-5 latch red data RData.Second switch S6b select in response to the first logic state of the second polarity control signal POL2 and export the 7th input channel Cm-5 latch red data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 8th input channel Cm-4 latch green data RData.
The 7th data routing selector switch S7 select in response to the first logic state of the second polarity control signal POL2 and export the 3rd input channel Cm-9 latch blue data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 6th input channel Cm-6 latch blue data RData.
The 8th data routing selector switch S8 select in response to the first logic state of the second polarity control signal POL2 and export the 4th input channel Cm-8 latch red data RData, and select and output offers the 5th input channel Cm-7 latchs green data RData in response to the second logic state of the second polarity control signal POL2.
The 9th data routing selector switch S9 comprises the first switch S 9a and second switch S9b, this first switch S 9a be used in response to the second polarity control signal POL2 export the 11 input channel Cm-1 latch green data RData or the 4th input channel Cm-8 latch red data RData, and this second switch S9b be used in response to the second polarity control signal POL2 export the 5th input channel Cm-7 latch green data RData or the 11 input channel Cm-1 latch green data RData.The first switch S 9a select in response to the first logic state of the second polarity control signal POL2 and export the 11 input channel Cm-1 latch green data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 4th input channel Cm-8 latch red data RData.Second switch S9b select in response to the first logic state of the second polarity control signal POL2 and export the 5th input channel Cm-7 latch green data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 11 input channel Cm-1 latch green data RData.
The tenth data routing selector switch S10 comprises the first switch S 10a and second switch S10b, this first switch S 10a be used in response to the second polarity control signal POL2 export the 12 input channel Cm latch blue data RData or the 3rd input channel Cm-9 latch blue data RData, and this second switch S10b be used in response to the second polarity control signal POL2 export the 6th input channel Cm-6 latch blue data RData or the 12 input channel Cm latch blue data RData.The first switch S 10a select in response to the first logic state of the second polarity control signal POL2 and export the 12 input channel Cm latch blue data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 3rd input channel Cm-9 latch blue data RData.Second switch S10b select in response to the first logic state of the second polarity control signal POL2 and export the 6th input channel Cm-6 latch blue data RData, and in response to the second logic state of the second polarity control signal POL2 select and export the 12 input channel Cm latch blue data RData.
The second data routing controller 320 comprises that the first to the 12 data selector M1 is to M12.The first data selector M1 latchs red data RData to what the first demoder D1 provided the first input channel Cm-11 when the first polarity control signal POL1 is in the first logic state, the second input channel Cm-10's latch green data RData and provide to the first demoder D1 when the first polarity control signal POL1 is in the second logic state.
The second data selector M2 latchs green data RData to what the second demoder D2 provided the second input channel Cm-10 when the first polarity control signal POL1 is in the first logic state, the first input channel Cm-11's latch red data RData and provide to the second demoder D2 when the first polarity control signal POL1 is in the second logic state.
The 3rd data selector M3 latchs blue data RData to what the 3rd or the 12 input channel Cm-9 that provides from the first switch S 1a of the first data routing selector switch S1 or Cm be provided the 3rd demoder D3 when the first polarity control signal POL1 is in the first logic state, the 9th or the 3rd input channel Cm-3 that provides from the second switch S1b of the first data routing selector switch S1 or Cm-9's latch blue data RData and provide to the 3rd demoder D3 when the first polarity control signal POL1 is in the second logic state.
The 4th data selector M4 when the first polarity control signal POL1 is in the first logic state to the 4th decoder D4 provide the 4th input channel Cm-8 that provides from the first switch S 2a of the second data path selector S2 latch red data RData or the 11 input channel Cm-1 latch green data RData, and when the first polarity control signal POL1 is in the second logic state to the 4th decoder D4 provide the tenth input channel Cm-2 that provides from the second switch S2b of the second data path selector S2 latch red data RData or the 4th input channel Cm-8 latch red data RData.
The 5th data selector M5 latchs green data RData to what the 5th demoder D5 provided the 5th input channel Cm-7 when the first polarity control signal POL1 is in the first logic state, and when the first polarity control signal POL1 is in the second logic state to the 5th demoder D5 provide the 11 input channel Cm-1 that provides from the 3rd data routing selector switch S3 latch green data RData or the tenth input channel Cm-2 latch red data RData.
The 6th data selector M6 latchs blue data RData to what the 6th demoder D6 provided the 6th input channel Cm-6 when the first polarity control signal POL1 is in the first logic state, the 12 or the 9th input channel Cm that provides from the 4th data routing selector switch S4 or Cm-3's latch blue data RData and provide to the 6th demoder D6 when the first polarity control signal POL1 is in the second logic state.
The 7th data selector M7 when the first polarity control signal POL1 is in the first logic state to the 7th decoder D7 provide the 7th input channel Cm-5 that provides from the first switch S 5a of the 5th data path selector S5 latch red data RData or the 8th input channel Cm-4 latch green data RData, and when the first polarity control signal POL1 is in the second logic state to the 7th decoder D7 provide the 8th input channel Cm-4 that provides from the second switch S5b of the 5th data path selector S5 latch green data RData or the 7th input channel Cm-5 latch red data RData.
The 8th data selector M8 when the first polarity control signal POL1 is in the first logic state to the 8th decoder D8 provide the 8th input channel Cm-4 that provides from the first switch S 6a of the 6th data path selector S6 latch green data RData or the 7th input channel Cm-5 latch red data RData, and when the first polarity control signal POL1 is in the second logic state to the 8th decoder D8 provide the 7th input channel Cm-5 that provides from the second switch S6b of the 6th data path selector S6 latch red data RData or the 8th input channel Cm-4 latch green data RData.
The 9th data selector M9 latchs blue data RData to what the 9th demoder D9 provided the 9th input channel Cm-3 when the first polarity control signal POL1 is in the first logic state, the 3rd or the 6th input channel Cm-9 that provides from the 7th data routing selector switch S7 or Cm-6's latch blue data RData and provide to the 9th demoder D9 when the first polarity control signal POL1 is in the second logic state.
The tenth data selector M10 latchs red data RData to what the tenth demoder D10 provided the tenth input channel Cm-2 when the first polarity control signal POL1 is in the first logic state, and when the first polarity control signal POL1 is in the second logic state to the tenth demoder D10 provide the 4th input channel Cm-8 that provides from the 8th data routing selector switch S8 latch red data RData or the 5th input channel Cm-7 latch green data RData.
The 11 data selector M11 when the first polarity control signal POL1 is in the first logic state to the 11 decoder D11 provide the 11 input channel Cm-1 that provides from the first switch S 9a of the 9th data path selector S9 latch green data RData or the 4th input channel Cm-8 latch red data RData, the 5th or the 11 input channel Cm-7 that provides from the second switch S9b of the 9th data path selector S9 or Cm-1's latch green data RData and to the 11 decoder D11, provide when the first polarity control signal POL1 is in the second logic state.
The 12 data selector M12 latchs blue data RData to what the 12 or the 3rd input channel Cm that provides from the first switch S 10a of the tenth data routing selector switch S10 or Cm-9 be provided the 12 demoder D12 when the first polarity control signal POL1 is in the first logic state, the 6th or the 12 input channel Cm-6 that provides from the second switch S10b of the tenth data routing selector switch S10 or Cm's latch blue data RData and provide to the 12 demoder D12 when the first polarity control signal POL1 is in the second logic state.
The path of image signal path controller 400 each the picture signal Vdata from data converter 200 to output buffer part 144 based on the first and second polarity control signal POL1 and POL2 control is so that the polarity of picture signal VData is corresponding to 1 of level or 2 reversing mode.For this reason, image signal path controller 400 comprises the first and second image signal path controllers 410 and 420.
The first image signal path controller 410 comprises that the first to the tenth image signal path selector switch s1 is to s10.The first image signal path selector switch s1 comprises the first switch s1a and second switch s1b, this first switch s1a is used in response to the blue images signal VData of the second polarity control signal POL2 output from the 3rd or the 12 demoder D3 or D12, and this second switch s1b is used in response to the blue images signal VData of the second polarity control signal POL2 output from the 9th or the 3rd demoder D9 or D3.The first switch s1a selects and exports the negative blue images signal VData that provides from the 3rd demoder D3 in response to the first logic state of the second polarity control signal POL2, and selects and export the positive blue images signal VData that provides from the 12 demoder D12 in response to the second logic state of the second polarity control signal POL2.Second switch s1b selects and exports the positive blue images signal VData that provides from the 9th demoder D9 in response to the first logic state of the second polarity control signal POL2, and selects and export the negative blue images signal VData that provides from the 3rd demoder D3 in response to the second logic state of the second polarity control signal POL2.
The second image signal path selector switch s2 comprises the first switch s2a and second switch s2b, this first switch s2a is used in response to the second polarity control signal POL2 output from the red picture signal VData of the 4th demoder D4 or from the green picture signal VData of the 11 demoder D11, and this second switch s2b is used in response to the second polarity control signal POL2 output from the red picture signal VData of the tenth demoder D10 or from the red picture signal VData of the 4th demoder D4.The first switch s2a selects and exports the picture signal VData at prime that provides from the 4th demoder D4 in response to the first logic state of the second polarity control signal POL2, and selects and export the green picture signal VData that provides from the 11 demoder D11 in response to the second logic state of the second polarity control signal POL2.Second switch s2b selects and exports the red picture signal VData that provides from the tenth demoder D10 in response to the first logic state of the second polarity control signal POL2, and selects and export the red picture signal VData that provides from the 4th demoder D4 in response to the second logic state of the second polarity control signal POL2.
The 3rd image signal path selector switch s3 selects and exports the negative green picture signal VData that provides from the 11 demoder D11 in response to the first logic state of the second polarity control signal POL2, and selects and export the negative red picture signal VData that provides from the tenth demoder D10 in response to the second logic state of the second polarity control signal POL2.
The 4th image signal path selector switch s4 selects and exports the positive blue images signal VData that provides from the 12 demoder D12 in response to the first logic state of the second polarity control signal POL2, and selects and export the positive blue images signal VData that provides from the 9th demoder D9 in response to the second logic state of the second polarity control signal POL2.
The 5th image signal path selector switch s5 comprises the first switch s5a and second switch s5b, this first switch s5a is used in response to the second polarity control signal POL2 output from the red picture signal VData of the 7th demoder D7 or from the green picture signal VData of the 8th demoder D8, and this second switch s5b is used in response to the second polarity control signal POL2 output from the green picture signal VData of the 8th demoder D8 or from the red picture signal VData of the 7th demoder D7.The first switch s5a selects and exports the negative red picture signal VData that provides from the 7th demoder D7 in response to the first logic state of the second polarity control signal POL2, and selects and export the just green picture signal VData that provides from the 8th demoder D8 in response to the second logic state of the second polarity control signal POL2.Second switch s5b selects and exports the just green picture signal VData that provides from the 8th demoder D8 in response to the first logic state of the second polarity control signal POL2, and selects and export the negative red picture signal VData that provides from the 7th demoder D7 in response to the second logic state of the second polarity control signal POL2.
The 6th image signal path selector switch s6 comprises the first switch s6a and second switch s6b, this first switch s6a is used in response to the second polarity control signal POL2 output from the green picture signal VData of the 8th demoder D8 or from the red picture signal VData of the 7th demoder D7, and this second switch s6b is used in response to the second polarity control signal POL2 output from the red picture signal VData of the 7th demoder D7 or from the green picture signal VData of the 8th demoder D8.The first switch s6a selects and exports the just green picture signal VData that provides from the 8th demoder D8 in response to the first logic state of the second polarity control signal POL2, and selects and export the negative red picture signal VData that provides from the 7th demoder D7 in response to the second logic state of the second polarity control signal POL2.Second switch s6b selects and exports the negative red picture signal VData that provides from the 7th demoder D7 in response to the first logic state of the second polarity control signal POL2, and selects and export the just green picture signal VData that provides from the 8th demoder D8 in response to the second logic state of the second polarity control signal POL2.
The 7th image signal path selector switch s7 selects and exports the negative blue images signal VData that provides from the 3rd demoder D3 in response to the first logic state of the second polarity control signal POL2, and selects and export the negative blue images signal VData that provides from the 6th demoder D6 in response to the second logic state of the second polarity control signal POL2.
The 8th image signal path selector switch s8 selects and exports the picture signal VData at prime that provides from the 4th demoder D4 in response to the first logic state of the second polarity control signal POL2, and selects and export the just green picture signal VData that provides from the 5th demoder D5 in response to the second logic state of the second polarity control signal POL2.
The 9th image signal path selector switch s9 comprises the first switch s9a and second switch s9b, this first switch s9a is used in response to the second polarity control signal POL2 output from the green picture signal VData of the 11 demoder D11 or from the red picture signal VData of the 4th demoder D4, and this second switch s9b is used in response to the second polarity control signal POL2 output from the green picture signal VData of the 5th demoder D5 or from the green picture signal VData of the 11 demoder D11.The first switch s9a selects and exports the negative green picture signal VData that provides from the 11 demoder D11 in response to the first logic state of the second polarity control signal POL2, and selects and export the picture signal VData at prime that provides from the 4th demoder D4 in response to the second logic state of the second polarity control signal POL2.Second switch s9b selects and exports the just green picture signal VData that provides from the 5th demoder D5 in response to the first logic state of the second polarity control signal POL2, and selects and export the negative green picture signal VData that provides from the 11 demoder D11 in response to the second logic state of the second polarity control signal POL2.
The tenth image signal path selector switch s10 comprises the first switch s10a and second switch s10b, this first switch s10a is used in response to the second polarity control signal POL2 output from the blue images signal VData of the 12 demoder D12 or from the blue images signal VData of the 3rd demoder D3, and this second switch s10b is used in response to the second polarity control signal POL2 output from the blue images signal VData of the 6th demoder D6 or from the blue images signal VData of the 12 demoder D12.The first switch s10a selects and exports the positive blue images signal VData that provides from the 12 demoder D12 in response to the first logic state of the second polarity control signal POL2, and selects and export the negative blue images signal VData that provides from the 3rd demoder D3 in response to the second logic state of the second polarity control signal POL2.Second switch s10b selects and exports the negative blue images signal VData that provides from the 6th demoder D6 in response to the first logic state of the second polarity control signal POL2, and selects and export the positive blue images signal VData that provides from the 12 demoder D12 in response to the second logic state of the second polarity control signal POL2.
The second image signal path controller 420 comprises that the first to the 12 picture signal selector switch m1 is to m12.The first picture signal selector switch m1 provides the picture signal VData at prime that provides from the first demoder D1 to the first alignment buffer Im-11 of output buffer part 144 when the first polarity control signal POL1 is in the first logic state, and the negative red picture signal VData that provides from the second demoder D2 is provided the first alignment buffer Im-11 to output buffer part 144 when the first polarity control signal POL1 is in the second logic state.At this moment, the red picture signal VData of plus or minus that provides to the first alignment buffer Im-11 is corresponding to the data that provide to the first input channel Cm-11.
The second picture signal selector switch m2 provides the negative green picture signal VData that provides from the second demoder D2 to the second alignment buffer Im-10 of output buffer part 144 when the first polarity control signal POL1 is in the first logic state, and the just green picture signal VData that provides from the first demoder D1 is provided the second alignment buffer Im-10 to output buffer part 144 when the first polarity control signal POL1 is in the second logic state.At this moment, the green picture signal VData of plus or minus that provides to the second alignment buffer Im-10 is corresponding to the data that provide to the second input channel Cm-10.
The third image signal selector m3 of the first polarity control signal POL1 is in the first logic state to the output buffer part 144 when the third buffer line Im-9 provided by the first image signal path selector s1 to provide a first switch s1a from the third decoder D3 or the negative blue image signal VData from the twelfth decoder D12 in ? image signal VData, and in the first polarity control signal POL1 is in the second logic state to the output buffer part 144 when the first three buffer line Im-9 provided by the first image signal path selector s1 to provide a second switch s1b from the ninth decoder D9, ? image signal VData from the third decoder D3 or the negative blue image signal VData.At this moment, the plus or minus blue images signal VData that provides to the 3rd alignment buffer Im-9 is corresponding to the data that provide to the 3rd input channel Cm-9.
The fourth image signal selector m4 of the first polarity control signal POL1 is in the first logic state to the output buffer part 144 when the fourth buffer line Im-8 provided by the second image signal path selector s2 to provide a first switch s2a from the fourth decoder D4 positive red image signal VData from the eleventh decoder D11 or the negative red image signal VData, and in the first polarity control signal POL1 is in the second logic state to the output buffer part 144 when the first four buffer line Im-8 provided by the second image signal path selector switch s2b s2 second decoder provides the D10 from the tenth negative red image signal VData or from a fourth decoder D4 positive red image signal VData.At this moment, the red picture signal VData of plus or minus that provides to the 4th alignment buffer Im-8 is corresponding to the data that provide to the 4th input channel Cm-8.
The 5th picture signal selector switch m5 provides the just green picture signal VData that provides from the 5th demoder D5 to the 5th alignment buffer Im-7 of output buffer part 144 when the first polarity control signal POL1 is in the first logic state, and when the first polarity control signal POL1 is in the second logic state to the 5th alignment buffer Im-7 of output buffer part 144 provide by the 3rd image signal path selector switch s3 provide from the negative green picture signal VData of the 11 demoder D11 or from the negative green picture signal VData of the tenth demoder D10.At this moment, the green picture signal VData of plus or minus that provides to the 5th alignment buffer Im-7 is corresponding to the data that provide to the 5th input channel Cm-7.
The 6th picture signal selector switch m6 provides the negative blue images signal VData that provides from the 6th demoder D6 to the 6th alignment buffer Im-6 of output buffer part 144 when the first polarity control signal POL1 is in the first logic state, and when the first polarity control signal POL1 is in the second logic state to the 6th alignment buffer Im-6 of output buffer part 144 provide by the 4th image signal path selector switch s4 provide from the positive blue images signal VData of the 12 demoder D12 or from the positive blue images signal VData of the 9th demoder D9.At this moment, the plus or minus blue images signal VData that provides to the 6th alignment buffer Im-6 is corresponding to the data that provide to the 6th input channel Cm-6.
Seventh image signal selector m7 of the first polarity control signal POL1 is in the first logic state to the output buffer part 144 when the seventh buffer line Im-5 provided by the fifth image signal path selector s5 to provide a first switch s5a from the seventh decoder D7 the negative red image signal VData from the eighth decoder D8 or the positive red image signal VData, and in the first polarity control signal POL1 is in the second logic state to the output buffer part 144 when the seventh buffer line Im-5 provides an image signal path through the fifth selector switch s5b s5 provide a second decoder D8 from the eighth positive red image signal decoder VData or from a seventh D7 negative red image signal VData.At this moment, the red picture signal VData of plus or minus that provides to the 7th alignment buffer Im-5 is corresponding to the data that provide to the 7th input channel Cm-5.
Eighth image signal selector m8 of the first polarity control signal POL1 is in the first logic state to the output buffer part 144 when the eighth buffer line Im-4 provided by the sixth image signal path selector s6 to provide a first switch s6a from the eighth decoder D8 positive green image signal VData from the seventh decoder D7 or the negative green image signal VData, and in the first polarity control signal POL1 is in the second logic state to the output buffer part 144 when the eighth buffer line Im-4 provided by the sixth image signal path selector s6 s6b provided a second switch from the seventh decoder D7 negative green image signal VData from the eighth decoder D8 or the positive green image signal VData.At this moment, the green picture signal VData of plus or minus that provides to the 8th alignment buffer Im-4 is corresponding to the data that provide to the 8th input channel Cm-4.
The 9th picture signal selector switch m9 provides the positive blue images signal VData that provides from the 9th demoder D9 to the 9th alignment buffer Im-3 of output buffer part 144 when the first polarity control signal POL1 is in the first logic state, and when the first polarity control signal POL1 is in the second logic state to the 9th alignment buffer Im-3 of output buffer part 144 provide by the 7th image signal path selector switch s7 provide from the negative blue images signal VData of the 3rd demoder D3 or from the negative blue images signal VData of the 6th demoder D6.At this moment, the plus or minus blue images signal VData that provides to the 9th alignment buffer Im-3 is corresponding to the data that provide to the 9th input channel Cm-3.
The tenth picture signal selector switch m10 provides the negative red picture signal VData that provides from the tenth demoder D10 to the tenth alignment buffer Im-2 of output buffer part 144 when the first polarity control signal POL1 is in the first logic state, and when the first polarity control signal POL1 is in the second logic state to the tenth alignment buffer Im-2 that exports buffer part 144 provide by the 8th image signal path selector switch s8 provide from the picture signal VData at prime of the 4th demoder D4 or from the picture signal VData at prime of the 5th demoder D5.At this moment, the red picture signal VData of plus or minus that provides to the tenth alignment buffer Im-2 is corresponding to the data that provide to the tenth input channel Cm-2.
Eleventh image signal selector m11 of the first polarity control signal POL1 is in the first logic state to the output buffer part 144 when the eleventh buffer line Im-1 provided by the ninth image signal path selector s9 the first switch s9a supplied from the eleventh decoder D11 and negative green image signal VData from the fourth decoder D4 or the positive green image signal VData, and in the first polarity control signal POL1 is in the second logic state to the output buffer part 144 when the the eleventh buffer line Im-1 provided by the ninth image signal path selector s9 s9b second switch provided from the fifth decoder D5 positive green image signal VData from the eleventh decoder D11 or the negative green image signal VData.At this moment, the green picture signal VData of plus or minus that provides to the 11 alignment buffer Im-1 is corresponding to the data that provide to the 11 input channel Cm-1.
Twelfth image signal selector m12 of the first polarity control signal POL1 is in the first logic state of the output buffer section 144 provided by the twelfth buffer line Im tenth image signal path selector s10 to provide a first switch s10a from the twelfth decoder D12 in ? image signal VData from the third decoder D3 or the negative blue image signal VData, and in the first polarity control signal POL1 is in the second logic state to the output buffer part 144 when the first twelve buffer line Im providing an image signal path through the tenth of a second selector switch s10b s10 offers from sixth decoder D6 negative blue image signal VData or from the twelfth decoder D12's image signal ? VData.At this moment, the plus or minus blue images signal VData that provides to the 12 alignment buffer Im is corresponding to the data that provide to the 12 input channel Cm.
In such a way, D/A converter 142 utilizes data routing controller 300 and image signal path controller 400, controls the path of data and picture signal based on the logic state of the first and second polarity control signal POL1 and POL2.As a result, D/A converter 142 latch data RData is converted to the picture signal VData of the polar mode with 1 of level or 2 reversing mode of level, and will offer through the picture signal of conversion output buffer part 144.
For example, all be in the situation of the first logic state for the first and second polarity control signal POL1 and POL2, D/A converter 142 is converted to the polar mode of picture signal VData the polar mode of 2 reversing mode of level, and with the gained picture signal offer output buffer part 144, as shown in Figure 6A.At this moment because except first and last input channel Cm-11 and Cm, along continuous straight runs is take the polarity of two input channels as basic reverse image signal, so the polar mode of 2 reversing mode of level has the form such as {+--++--++--+}.
Be in the second logic state and the second polarity control signal POL2 is in the situation of the first logic state for the first polarity control signal POL1, D/A converter 142 is converted to the polar mode of picture signal VData the polar mode of 2 reversing mode of level through reversing, and with the gained picture signal offer output buffer part 144, shown in Fig. 6 B.At this moment because except first and last input channel Cm-11 and Cm, along continuous straight runs is take the polarity of two input channels as basic reverse image signal, thus through the polar mode of 2 reversing mode of level of counter-rotating have such as ++--++--++-form.
Be in the first logic state and the second polarity control signal POL2 is in the situation of the second logic state for the first polarity control signal POL1, D/A converter 142 is converted to the polar mode of picture signal VData the polar mode of 1 reversing mode of level, and with the gained picture signal offer output buffer part 144, shown in Fig. 6 C.At this moment because along continuous straight runs is take the polarity of every input channel as basic reverse image signal, so the polar mode of 1 reversing mode of level have such as+-+-+-+-+-+-form.
All be in the situation of the second logic state for the first and second polarity control signal POL1 and POL2, D/A converter 142 is converted to the polar mode of picture signal VData the polar mode of 1 reversing mode of level through reversing, and with the gained picture signal offer output buffer part 144, shown in Fig. 6 D.At this moment because along continuous straight runs is take the polarity of every input channel as basic reverse image signal, so through the polar mode of 1 reversing mode of level of counter-rotating have such as+-+-+-+-+-+form.
Therefore, D/A converter 142 is based on each the path in the logic state of the first and second polarity control signal POL1 and POL2 control data and the picture signal, so that data and picture signal are corresponding to 2 of levels or 1 reversing mode of level.As a result, the quantity of the demoder of setting is identical with the quantity of output channel.
The picture signal VData of each passage that output buffer part 144 buffering provides from D/A converter 142, and the picture signal of buffering outwards exported by final output channel.Output buffer part 144 is amplified and output image signal VData based on external loading.
As mentioned above, the data driven unit 100 of first embodiment of the invention can separate and the upper gray-scale voltage PBV_x of individually control indigo plant and NBV_x and red/green upper gray-scale voltage PRGV_x and NRGV_x, to keep the color temperature constant of intensity-based level.And, can reduce the size of gray-scale voltage maker 120.More particularly, each in will positive blue upper gray-scale voltage PBV_x of the data driven unit 100 of first embodiment of the invention is arranged to than each the high voltage level of voltage level among at prime/green upper gray-scale voltage PRGV_x, is arranged to than each the low voltage level of voltage level among negative red/green upper gray-scale voltage NRGV_x and will bear among the blue upper gray-scale voltage NBV_x each.Therefore, as shown in Figure 7, can be based on compensating colour temperature by the gray level in the upper gray level region shown in the curve B.Comparatively speaking, curve A represents the colour temperature curve of liquid crystal display intensity-based level that same grayscale step voltage wherein is used for the routine of red, green and blue data-signal.
And, in the first embodiment of the present invention, in digital/analog converter 142, be provided with the quantity demoder identical with the output channel number of data driven unit 100, reduced thus the size of data driven unit 100.
Fig. 8 is the schematic circuit of the exemplary gray scale voltage generator 120 of data driven unit 100 second embodiment of the invention.Data driven unit 100 second embodiment of the invention is except it also comprises the first and second external resistor RR21 and RR31 that are connected to gray-scale voltage maker 120, and remainder has the identical structure of structure with the data driven unit 100 of Fig. 2 and the first embodiment of the invention shown in 3 generally.Therefore, do not repeat description to the same parts among Fig. 2 and 3 described above.
Specifically, the first external resistor RR21 is connected in parallel to the second resistor RR2 in the second divider resistance string 124 that is arranged on gray-scale voltage maker 120.The first external resistor RR21 can be the resistor that the outside is mounted to data driven unit 100.The first external resistor RR21 is for the resistance of the second resistor RR2 of the second divider resistance string 124 of fine setting gray-scale voltage maker 120.The second external resistor RR31 is connected in parallel to the 3rd resistor RR3 in the 3rd divider resistance string 126 that is arranged on gray-scale voltage maker 120.The second external resistor RR31 can be the resistor that the outside is mounted to data driven unit 100.The second external resistor RR31 is for the resistance of the 3rd resistor RR3 of the 3rd divider resistance string 126 of fine setting gray-scale voltage maker 120.Therefore, data driven unit 100 second embodiment of the invention can utilize among the first and second external resistor RR21 and the RR31 each finely tune positive and negative red/among green upper gray-scale voltage PRGV_x and the NRGV_x each, more constant with the colour temperature that keeps the intensity-based level.
Perhaps, the g voltage grading resistor Rr_g of the second resistor RR2 of the second divider resistance string 124 and the 3rd divider resistance string 126 can by as mentioned above and same way as shown in Figure 4 be connected to the first divider resistance string 122.
Fig. 9 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the 3rd embodiment of the present invention.Have generally the structure identical with the data driven unit 100 of Fig. 2 and the first embodiment of the invention shown in 3 according to the data driven unit 100 of the 3rd embodiment of the present invention, but have some modifications.Therefore, do not repeat description to the same parts among Fig. 2 and 3 described above.
Specifically, gray-scale voltage maker 120 according to the data driven unit 100 of the 3rd embodiment of the present invention comprises the first and second selector switch RV1 and RV2, to replace the second and the 3rd resistor RR2 and RR3 in the second and the 3rd divider resistance string 124 and 126 shown in Figure 3.
As shown in figure 10, first selector RV1 comprises a plurality of optional resistor Ra, Rb, Rc and the Rd that is connected in parallel to first node n1, and is used for selecting signal RSS that any of optional resistor Ra, Rb, Rc and Rd is connected to the multiplexer MUX of Section Point n2 in response to providing from the outside to its resistor.In this illustrative embodiments, first node n1 is connected to driving voltage source VDD, and Section Point is connected to first at prime/green voltage grading resistor Rr_1 of the second divider resistance string 124.First selector RV1 selects signal RSS to select among optional resistor Ra, Rb, Rc and the Rd any based on resistor, thus so that x red/green gray-scale voltage PRGV_x in not only can optimization just distinguishing, and can finely tune them.
As shown in figure 10, second selector RV2 comprises a plurality of optional resistor Ra, Rb, Rc and the Rd that is connected in parallel to first node n1, and is used for selecting signal RSS that any of optional resistor Ra, Rb, Rc and Rd is connected to the multiplexer MUX of Section Point n2 in response to providing from the outside to its resistor.In this illustrative embodiments, first node n1 is connected to k2 benchmark gamma voltage line, and with Section Point be connected to the 3rd divider resistance string 126 negative red/green voltage grading resistor Rr_f+2.Second selector RV2 selects signal RSS to select among optional resistor Ra, Rb, Rc and the Rd any based on resistor, thus so that x red/green gray-scale voltage NRGV_x in not only can the optimization minus zone, and can finely tune them.
Therefore, according to the data driven unit 100 of the 3rd embodiment of the present invention can utilize among the first and second selector switch RV1 and the RV2 each come optimization and finely tune positive and negative red/among green upper gray-scale voltage PRGV_x and the NRGV_x each, more constant with the colour temperature that keeps the intensity-based level.
Perhaps, in the gray-scale voltage maker 120 according to the data driven unit 100 of the 3rd embodiment of the present invention, the g voltage grading resistor Rr_g of the first node n1 of the second divider resistance string 124 and the 3rd divider resistance string 126 can by as mentioned above and same way as shown in Figure 4 be connected to the first divider resistance string 122.
Figure 11 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the 4th embodiment of the present invention.Have generally the structure identical with the data driven unit 100 of Fig. 2 and the first embodiment of the invention shown in 3 according to the data driven unit 100 of the 4th embodiment of the present invention, but have some modifications.Therefore, do not repeat description to the same parts among Fig. 2 and 3 described above.
Specifically, the second divider resistance string 124 comprises the first resistor RR1 and first to (e-1) voltage grading resistor R_1 to R_e-1, and the described first in to (e-1) voltage grading resistor R_1 to R_e-1 each has the identical resistance of resistance of the resistor among the first district 122a with the first divider resistance string 122.That is, the second divider resistance string 124 has the identical structure of structure of the remainder the e voltage grading resistor R_e in this first district 122a with the first district 122a of the first divider resistance string 122.And, the positive gray level external voltage of i PEVi is offered the second divider resistance string 124 discretely.Therefore, the second divider resistance string 124 generates at prime/green upper gray-scale voltage PRGV_x based on the positive gray level external voltage of i PEVi.Therefore, in the 4th embodiment of the present invention, can finely tune at prime/green upper gray-scale voltage PRGV_x by regulating the positive gray level external voltage of i PEVi.
The 3rd divider resistance string 126 comprises (f+1) to g voltage grading resistor R_f+1 to R_g, and wherein each has the identical resistance of resistance of the resistor among the Second Region 122b with the first divider resistance string 122.That is, the 3rd divider resistance string 126 has the identical structure of structure of the remainder the f voltage grading resistor R_f in this Second Region 122b with the Second Region 122b of the first divider resistance string 122.And, with the negative gray level external voltage NEVh of h offer discretely the generation h of the 3rd divider resistance string 126 negative red/the dividing potential drop node of green gray-scale voltage NRGV_h.Therefore, the 3rd divider resistance string 126 generates negative red/green gray-scale voltage NRGV_x based on the negative gray level external voltage NEVh of h.Therefore, in the 4th embodiment of the present invention, can finely tune negative red/green upper gray-scale voltage NRGV_x by regulating the negative gray level external voltage NEVh of h.
Therefore, can utilize among i positive gray level external voltage PEVi and the negative gray level external voltage NEVh of h each according to the data driven unit 100 of the 4th embodiment of the present invention, come optimization and finely tune positive and negative red/among green upper gray-scale voltage PRGV_x and the NRGV_x each, more constant with the colour temperature that keeps the intensity-based level.
Figure 12 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the 5th embodiment of the present invention.Have generally the structure identical with the data driven unit 100 of Fig. 2 and the first embodiment of the invention shown in 3 according to the data driven unit 100 of the 5th embodiment of the present invention, but have some modifications.Therefore, do not repeat description to the same parts among Fig. 2 and 3 described above.
Specifically, the gray-scale voltage maker 120 according to the data driven unit 100 of the 5th embodiment of the present invention comprises the first to the 3rd divider resistance string 122,1124 and 1126.
The first resistor RR1 that the utilization of the first divider resistance string 122 is connected in series between driving voltage source VDD and the ground voltage supplies VSS becomes gray-scale voltage PBV_x and NBV_x and positive and negative three looks public gray-scale voltage CV on the positive and negative basket next life with first the press operation that divides to g voltage grading resistor R_1 to R_g.The first divider resistance string 122 has the identical structure of structure with the first embodiment of the present invention shown in Figure 3.Therefore, do not repeat detailed description.
The second divider resistance string 1124 comprises that the first to the t positive voltage grading resistor Rt_1 that is connected in series between the first supply voltage source AVDD1 and the ground voltage supplies VSS is to Rt_t.The first supply voltage source AVDD1 can have the voltage level that is between the positive gray-scale voltage PRGV_i of i and the driving voltage source VDD.A plurality of positive external voltage PEVi are offered the middle dividing potential drop node of the second divider resistance string 1124 to PEVh.For example, the i positive gray level external voltage PEVi corresponding with i gray-scale voltage PRGV_i can be offered the dividing potential drop node (between Rt_1 and the Rt_2) of the generation i gray-scale voltage PRGV_i in the middle of the dividing potential drop node of the second divider resistance string 1124, and (i-1) corresponding with (i-1) gray-scale voltage PRGV_i-1 positive gray level external voltage PEVi-1 can be offered the dividing potential drop node (between Rt_2 and the Rt_3) of generation (i-1) the gray-scale voltage PRGV_i-1 in the middle of the dividing potential drop node of the second divider resistance string 1124.The h positive gray level external voltage PEVh corresponding with h gray-scale voltage PRGV_h can be offered the dividing potential drop node (between Rt_t-1 and the Rt_t) of the generation h gray-scale voltage PRGV_h in the middle of the dividing potential drop node of the second divider resistance string 1124.
The second divider resistance string 1124 to analog processor 140 provide comprise i gray-scale voltage PRGV_i to the x of h gray-scale voltage PRGV_h at prime/green on gray-scale voltage PRGV_x, described i gray-scale voltage PRGV_i to h gray-scale voltage PRGV_h by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of the first to t positive voltage grading resistor Rt_1 in the Rt_t.
The 3rd divider resistance string 1126 comprises that being connected in series in first to t between the second supply voltage source AVDD2 and the ground voltage supplies VSS bears voltage grading resistor Rs_1 to Rs_t.The second supply voltage source AVDD2 can have the voltage level that is between the negative gray-scale voltage NRGV_h of h and the ground voltage supplies VSS.
A plurality of negative external voltage NEVh are offered the middle dividing potential drop node of the 3rd divider resistance string 1126 to NEVi.For example, the negative gray level external voltage NEVh of the h corresponding with h gray-scale voltage NRGV_h can be offered the dividing potential drop node (between Rs_1 and the Rs_2) of the generation h gray-scale voltage NRGV_h in the middle of the dividing potential drop node of the 3rd divider resistance string 1126, and (i-1) corresponding with (i-1) gray-scale voltage NRGV_i-1 negative gray level external voltage NEVi-1 can be offered the dividing potential drop node (between Rs_t-2 and the Rs_t-1) of generation (i-1) the gray-scale voltage NRGV_i-1 in the middle of the dividing potential drop node of the 3rd divider resistance string 1126.The negative gray level external voltage NEVi of the i corresponding with i gray-scale voltage NRGV_i can be offered the dividing potential drop node (between Rs_t-1 and the Rs_t) of the generation i gray-scale voltage NRGV_i in the middle of the dividing potential drop node of the 3rd divider resistance string 1126.
The 3rd divider resistance string 1126 to analog processor 140 provide comprise h gray-scale voltage NRGV_h to the x of i gray-scale voltage NRGV_i negative red/green on gray-scale voltage NRGV_x, described h gray-scale voltage NRGV_h to i gray-scale voltage NRGV_i by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of the first to t negative voltage grading resistor Rs_1 in the Rs_t.
Gray-scale voltage maker 120 according to the data driven unit 100 of the 5th embodiment of the present invention utilizes the first divider resistance string 122 to generate gray-scale voltage PBV_x and NBV_x and positive and negative three looks public gray-scale voltage CV on the positive and negative basket, and utilize with the second and the 3rd divider resistance string 1124 of the first divider resistance string 122 isolation and 1126 generation positive and negatives red/green upper gray-scale voltage PRGV_x and NRGV_x.In order to compensate colour temperature, among the positive blue upper gray-scale voltage PBV_x each has the voltage level than each the high predetermined value among at prime/green upper gray-scale voltage PRGV_x, and among the negative blue upper gray-scale voltage NBV_x each has the voltage level than each the low predetermined value among negative red/green upper gray-scale voltage NRGV_x.Therefore, can separate and the individually blue upper gray-scale voltage PBV_x of control and NBV_x and red/green upper gray-scale voltage PRGV_x and NRGV_x according to the data driven unit 100 of the 5th embodiment of the present invention, to keep the color temperature constant of intensity-based level.
Although will be described as according to the data driven unit of the first to the 5th illustrative embodiments of the present invention separating and controlling individually the upper gray level of bluish grey degree step voltage PBV_x and NBV_x and red/green gray-scale voltage PRGV_x and NRGV_x, but the invention is not restricted to this, but can separation as described below and control individually the lower gray level of gray-scale voltage.
Figure 13 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the 6th embodiment of the present invention.Except gray scale step voltage maker 120, have generally the structure identical with the data driven unit 100 of first embodiment of the invention shown in Figure 2 according to the data driven unit 100 of the 6th embodiment of the present invention.Therefore, do not repeat description to the same parts among Fig. 2 described above.
Gray-scale voltage maker 120 according to the data driven unit of the 6th embodiment of the present invention comprises the first to the 3rd divider resistance string 2122,2124 and 2126.The first divider resistance string 2122 comprises and is connected in series in first between driving voltage source VDD and the ground voltage supplies VSS to g voltage grading resistor R_1 to R_g (wherein, g is natural number).The first divider resistance string 2122 is divided into the first and second public area 2122c1 and 2122c2 and the first and second district 2122a and 2122b according to the voltage that utilizes resistor to carry out the described generation of dividing potential drop.
The first public area 2122c1 comprise be connected to driving voltage source VDD first to c voltage grading resistor R_1 to R_c (wherein, c is the natural number less than g).(wherein, r1 for less than the natural number of j/2) offers respectively the middle dividing potential drop node of the first public area 2122c1 to (r1-1) benchmark gamma voltage GMA_1 to GMA_r1-1 with first in the middle of j the benchmark gamma voltage GMA_j.First has rule or irregular voltage difference with respect to adjacent benchmark gamma voltage to (r1-1) benchmark gamma voltage GMA_1 to GMA_r1-1 according to electro-optical characteristic, color temperature characteristic and the gamma characteristic of liquid crystal, and is provided for respectively corresponding dividing potential drop node among the first public area 2122c1.The first public area 2122c1 provides to analog processor 140 and comprises i to the (v+1) gray-scale voltage PCV_i to the y of PCV_v+1 positive three looks public gray-scale voltage PCV_y, described i to the (v+1) gray-scale voltage PCV_i to PCV_v+1 by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between first per two adjacent resistor in to c voltage grading resistor R_1 to R_c.For example, when the figure place of data-signal was 8, the first public area 2122c1 generated and comprises that the 64th to the 255th positive gray-scale voltage PCV_64 is to 192 positive three looks public gray-scale voltage PCV_y of PCV_255.
The first district 2122a comprises that the c that is connected in series is to d voltage grading resistor R_c to R_d.R1 in the middle of j the benchmark gamma voltage GMA_j is offered respectively the middle dividing potential drop node of the first district 2122a to j/2 benchmark gamma voltage GMA_r1 to GMA_j/2.R1 has rule or irregular voltage difference with respect to adjacent benchmark gamma voltage to j/2 benchmark gamma voltage GMA_r1 to GMA_j/2 according to electro-optical characteristic, color temperature characteristic and the gamma characteristic of liquid crystal, and is provided for respectively corresponding dividing potential drop node among the first district 2122a.The first district 2122a provides to analog processor 140 and comprises v to the 0 positive gray-scale voltage PBV_v to the x of PBV_0 just bluish grey degree step voltage PBV_x, described v to the 0 gray-scale voltage PBV_v to PBV_0 by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of c in to d voltage grading resistor R_c to R_d.For example, when the figure place of data-signal was 8, the first district 2122a generated and comprises that the 63rd to the 0th positive gray-scale voltage PBV_63 is to 64 just bluish grey degree step voltage PBV_x of PBV_0.
Second Region 2122b comprises that the e that is connected in series is to f voltage grading resistor R_e to R_f.(j/2+1) in the middle of j the benchmark gamma voltage GMA_j offered respectively the middle dividing potential drop node of Second Region 2122b to GMA_r2-1 to (r2-1) benchmark gamma voltage GMA_j/2+1.(j/2+1) has rule or irregular voltage difference with respect to adjacent benchmark gamma voltage to (r2-1) benchmark gamma voltage GMA_j/2+1 to GMA_r2-1 according to electro-optical characteristic, color temperature characteristic and the gamma characteristic of liquid crystal, and is provided for respectively corresponding dividing potential drop node among the Second Region 2122b.Second Region 2122b provides to analog processor 140 and comprises the 0th to v negative gray-scale voltage NBV_0 to x the negative bluish grey degree step voltage NBV_x of NBV_v, the described the 0th to v bear gray-scale voltage NBV_0 to NBV_v by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of e in to f voltage grading resistor R_e to R_f.For example, when the figure place of data-signal was 8, Second Region 2122b generated and comprises that the 0th to the 63rd negative gray-scale voltage NBV_0 is to 64 negative bluish grey degree step voltage NBV_x of NBV_63.
Perhaps, at least one illusory resistor (not shown) can be connected between the first district 2122a and the Second Region 2122b.
The second public area 2122c2 comprises that the f that is connected in series is to g voltage grading resistor R_f to R_g.R2 in the middle of j the benchmark gamma voltage GMA_j is offered respectively the middle dividing potential drop node of the second public area 2122c2 to j benchmark gamma voltage GMA_r2 to GMA_j.R2 has rule or irregular voltage difference with respect to adjacent benchmark gamma voltage to j benchmark gamma voltage GMA_r2 to GMA_j according to electro-optical characteristic, color temperature characteristic and the gamma characteristic of liquid crystal, and is provided for respectively corresponding dividing potential drop node among the second public area 2122c2.The second public area 2122c2 provides to analog processor 140 and comprises the negative three looks public gray-scale voltage NCV_y of (v+1) y to i gray-scale voltage NCV_v+1 to NCV_i, described (v+1) to i gray-scale voltage NCV_ (v+1) to NCV_i by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of f in to g voltage grading resistor R_f to R_g.For example, when the figure place of data-signal was 8, the second public area 2122c2 generated and comprises that the 64th to the 255th negative gray-scale voltage NCV_64 is to 192 negative three looks public gray-scale voltage NCV_y of NCV_255.
The second divider resistance string 2124 comprises that first red/green resistor Rrg1 and x at prime/green voltage grading resistor Rr_c+2 are to Rr_d.The dividing potential drop node that this first red/green resistor Rrg1 is connected to the positive gray-scale voltage PBV-v of generation v of the first divider resistance string 2122 and externally provides r1 benchmark gamma voltage GMA_r1.First red/green resistor Rrg1 has the large resistance of resistance than (c+1) resistor R_c+1 of the first divider resistance string 2122, the x in just distinguishing with optimization red/green gray-scale voltage PRGV_x.
Described x is at prime/and green voltage grading resistor Rr_c+2 is connected in series in first red/green resistor Rrg1 and provides between the dividing potential drop node of j/2 benchmark gamma voltage GMA_j/2 to Rr_d.X is at prime/each in the Rr_d of green voltage grading resistor Rr_c+2 have with the first district 2122a that is arranged on the first divider resistance string 2122 in (c+2) to d voltage grading resistor R_c+2 to the identical resistance of the resistance of the corresponding resistor of R_d.Thereby the second divider resistance string 2124 is except the resistance of first red/green resistor Rrg1, and remainder has the structure identical with the structure of the first district 2122a of the first divider resistance string 2122.
At least one positive external voltage PEV1 can also be offered at least one in the dividing potential drop node of the second divider resistance string 2124.The second divider resistance string 2124 provides to analog processor 140 and comprises v to the 0 gray-scale voltage PRGV_v to the x of PRGV_0 at prime/green lower gray-scale voltage PRGV_x, described v to the 0 gray-scale voltage PRGV_v to PRGV_0 by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between resistor Rrg1 and Rr_c+2 per two adjacent resistor in the Rr_d.
The 3rd divider resistance string 2126 comprises that second red/green resistor Rrg2 and x negative red/green voltage grading resistor Rr_e+1 are to Rr_f-1.This second red/green resistor Rrg2 is connected to the dividing potential drop node that provides (j/2+1) benchmark gamma voltage GMA_j/2+1.Second red/green resistor Rrg2 has the large resistance of resistance than the e resistor R_e of the first divider resistance string 2122, with the x in the optimization minus zone red/green gray-scale voltage NRGV_x.
Described x negative red/green voltage grading resistor Rr_e+1 is connected in series between the dividing potential drop node that externally provides r2 benchmark gamma voltage GMA_r2 of second red/green resistor Rrg2 and the first divider resistance string 2122 to Rr_f-1.X is negative red/each in the Rr_f-1 of green voltage grading resistor Rr_e+1 have with the Second Region 2122b that is arranged on the first divider resistance string 2122 in (e+1) to (f-1) voltage grading resistor R_e+1 to the identical resistance of the resistance of the corresponding resistor of R_f-1.Thereby the 3rd divider resistance string 2126 is except the resistance of second red/green resistor Rrg2, and remainder has the structure identical with the structure of the Second Region 2122b of the first divider resistance string 2122.
At least one negative external voltage NEV1 can also be offered at least one in the dividing potential drop node of the 3rd divider resistance string 2126.The 3rd divider resistance string 2126 to analog processor 140 provide comprise the 0th x to v gray-scale voltage NRGV_0 to NRGV_v negative red/green lower gray-scale voltage NRGV_x, the described the 0th to v gray-scale voltage NRGV_0 to NRGV_v by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between resistor Rrg2 and Rr_e+1 per two adjacent resistor in the Rr_f-1.
Utilize the first divider resistance string 2122 to generate gray-scale voltage PBV_x and NBV_x and positive and negative three looks public gray-scale voltage PCV_y and NCV_y under the positive and negative basket according to the gray-scale voltage maker 120 of the 6th embodiment of the present invention, and utilize the second and the 3rd divider resistance string 2124 and 2126 generate positive and negatives red/green lower gray-scale voltage PRGV_x and NRGV_x.In order to compensate colour temperature, just each among the lower gray-scale voltage PBV_x of indigo plant has the voltage level than each the high predetermined value among at prime/green lower gray-scale voltage PRGV_x, and each among the gray-scale voltage NBV_x has than the voltage level of bearing each the low predetermined value among red/green lower gray-scale voltage NRGV_x under the negative basket.Therefore, can separate and the individually blue lower gray-scale voltage PBV_x of control and NBV_x and red/green lower gray-scale voltage PRGV_x and NRGV_x according to the data driven unit 100 of the 6th embodiment of the present invention, to keep the color temperature constant of intensity-based level.
Figure 14 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the 7th embodiment of the present invention., except also comprising the first and second external resistor Rrg11 and Rrg21 that are connected to gray-scale voltage maker 120, it has generally and Fig. 2 and the identical structure of the data driven unit 100 according to the 6th embodiment of the present invention shown in 13 according to the data driven unit 100 of the 7th embodiment of the present invention.Therefore, do not repeat description to the same parts among Fig. 2 and 13 described above.
Specifically, the first external resistor Rrg11 is connected in parallel to first red/green resistor Rrg1 of the second divider resistance string 2124, finely tuning the resistance of first red/green resistor Rrg1, as described in the second embodiment of the present invention.The second external resistor Rrg21 is connected in parallel to second red/green resistor Rrg2 of the 3rd divider resistance string 2126, finely tuning the resistance of second red/green resistor Rrg2, as described in the second embodiment of the present invention.Therefore, according to the data driven unit 100 of the 7th embodiment of the present invention can utilize each fine setting positive and negative among the first and second external resistor Rrg11 and the Rrg21 red/among green lower gray-scale voltage PRGV_x and the NRGV_x each, more constant with the colour temperature that keeps the intensity-based level.
Figure 15 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the 8th embodiment of the present invention.Have generally and Fig. 2 and the identical structure of the data driven unit 100 according to the 6th embodiment of the present invention shown in 13 according to the data driven unit 100 of the 8th embodiment of the present invention, but have some modifications.Therefore, do not repeat description to the same parts among Fig. 2 and 13 described above.
Specifically, the exemplary gray scale voltage generator 120 according to the data driven unit 100 of the 8th embodiment of the present invention comprises that the first and second selector switch RV1 and RV2 are to replace first and second red/green resistor Rrg1 and Rrg2 in the second and the 3rd divider resistance string 2124 and 2126 shown in Figure 13.
First selector RV1 comprises as above a plurality of optional resistor Ra, Rb, Rc and the Rd described in the 3rd embodiment of the present invention, and multiplexer MUX (Figure 10).First selector RV1 selects signal RSS to select among optional resistor Ra, Rb, Rc and the Rd any based on resistor, thus so that x red/green gray-scale voltage PRGV_x in not only can optimization just distinguishing, and can finely tune them.
Second selector RV2 comprises as above a plurality of optional resistor Ra, Rb, Rc and the Rd described in the 3rd embodiment of the present invention, and multiplexer MUX (Figure 10).Second selector RV2 selects signal RSS to select among optional resistor Ra, Rb, Rc and the Rd any based on resistor, thus so that x red/green gray-scale voltage NRGV_x in not only can the optimization minus zone, and can finely tune them.
Therefore, can utilize among the first and second selector switch RV1 and the RV2 each according to the data driven unit 100 of the 8th embodiment of the present invention, come optimization and finely tune positive and negative red/among green lower gray-scale voltage PRGV_x and the NRGV_x each, more constant with the colour temperature that keeps the intensity-based level.
Figure 16 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the 9th embodiment of the present invention.Have generally and Fig. 2 and the identical structure of the data driven unit 100 according to the 6th embodiment of the present invention shown in 13 according to the data driven unit 100 of the 9th embodiment of the present invention, but have some modifications.Therefore, do not repeat description to the same parts among Fig. 2 and 13 described above.
Specifically, the second divider resistance string 2124 comprises (c+1) to d voltage grading resistor R_c+1 to R_d, and wherein each has the identical resistance of resistance of the corresponding resistor of the resistor among the first district 2122a with the first divider resistance string 2122.The second divider resistance string 2124 generates at prime/green lower gray-scale voltage PRGV_x based on the positive gray level external voltage of v PEVv.Therefore, the 9th embodiment of the present invention can be finely tuned at prime/green lower gray-scale voltage PRGV_x by regulating the positive gray level external voltage of v PEVv.
The 3rd divider resistance string 2126 comprises e to the (f-1) voltage grading resistor R_e to R_f-1, and wherein each has the identical resistance of resistance of the corresponding resistor of the resistor among the Second Region 2122b with the first divider resistance string 2122.The 3rd divider resistance string 2126 generates negative red/green gray-scale voltage NRGV_x based on the 0th negative gray level external voltage NEV0.Therefore, the 9th embodiment of the present invention can be finely tuned negative red/green lower gray-scale voltage NRGV_x by regulating the 0th negative gray level external voltage NEV0.
Therefore, can utilize among v positive gray level external voltage PEVv and the 0th negative gray level external voltage NEV0 each according to the data driven unit 100 of the 9th embodiment of the present invention, come optimization and finely tune positive and negative red/among green lower gray-scale voltage PRGV_x and the NRGV_x each, more constant with the colour temperature that keeps the intensity-based level.
Figure 17 is the schematic circuit according to the exemplary gray scale voltage generator 120 of the data driven unit 100 of the tenth embodiment of the present invention.Have generally and Fig. 2 and the identical structure of the data driven unit 100 according to the 6th embodiment of the present invention shown in 13 according to the data driven unit 100 of the tenth embodiment of the present invention, but have some modifications.Therefore, do not repeat description to the same parts among Fig. 2 and 13 described above.
Specifically, the exemplary gray scale voltage generator 120 according to the data driven unit 100 of the tenth embodiment of the present invention comprises the first to the 3rd divider resistance string 2122,2124 and 2126.
The first divider resistance string 2122 utilizes and is connected in series in minute press operation of first between driving voltage source VDD and the ground voltage supplies VSS to g voltage grading resistor R_1 to R_g, generates positive and negative three looks public gray-scale voltage PCV_y and NCV_y and positive and negative bluish grey degree step voltage PBV_x and NBV_x.The first divider resistance string 2122 has the identical structure of structure with the 6th embodiment of the present invention shown in Figure 13, does not therefore repeat detailed description.
The second divider resistance string 2124 comprises that the first to the o positive voltage grading resistor Ro_1 that is connected in series between the first supply voltage source AVDD1 and the ground voltage supplies VSS is to Ro_o.The first supply voltage source AVDD1 can have the voltage level that is between the positive gray-scale voltage PRGV_v of v and the driving voltage source VDD, perhaps can be identical with r1 benchmark gamma voltage GMA_r1.A plurality of positive external voltage PEVv are offered the middle dividing potential drop node of the second divider resistance string 2124 to PEV0.The positive gray level external voltage of v PEVv can be r1 benchmark gamma voltage GMA_r1, and the 0th positive gray level external voltage PEV0 can be j/2 benchmark gamma voltage GMA_j/2.
The second divider resistance string 2124 provides to analog processor 140 and comprises v to the 0 gray-scale voltage PRGV_v to the x of PRGV_0 at prime/green lower gray-scale voltage PRGV_x, described v to the 0 gray-scale voltage PRGV_v to PRGV_0 by being respectively formed at first to the.Corresponding dividing potential drop node between per two adjacent resistor of positive voltage grading resistor Ro_1 in the Ro_o carries out dividing potential drop and generates.
The 3rd divider resistance string 2126 comprises that being connected in series in first to o between the second supply voltage source AVDD2 and the ground voltage supplies VSS bears voltage grading resistor Rp_1 to Rp_o.The second supply voltage source AVDD2 can have the voltage level that is between the negative gray-scale voltage NRGV_v of v and the ground voltage supplies VSS.A plurality of negative external voltage NEV0 are offered the middle dividing potential drop node of the 3rd divider resistance string 2126 to NEVv.The 0th negative gray level external voltage NEV0 can be (j/2+1) benchmark gamma voltage GMA_j/2+1, and the negative gray level external voltage NEVv of v can be r2 benchmark gamma voltage GMA_r2.
The 3rd divider resistance string 2126 to analog processor 140 provide comprise the 0th x to v gray-scale voltage NRGV_0 to NRGV_v negative red/green lower gray-scale voltage NRGV_x, the described the 0th to v gray-scale voltage NRGV_0 to NRGV_v by carrying out dividing potential drop and generate being respectively formed at corresponding dividing potential drop node between per two adjacent resistor of the first to o negative voltage grading resistor Rp_1 in the Rp_o.
Gray-scale voltage maker 120 according to the data driven unit 100 of the tenth embodiment of the present invention utilizes the first divider resistance string 2122 to generate positive and negative three looks public gray-scale voltage PCV_y and NCV_y and positive and negative bluish grey degree step voltage PBV_x and NBV_x, and utilize with the second and the 3rd divider resistance string 2124 of the first divider resistance string 2122 isolation and 2126 generation positive and negatives red/green lower gray-scale voltage PRGV_x and NRGV_x.In order to compensate colour temperature, just each among the lower gray-scale voltage PBV_x of indigo plant has the voltage level than each the high predetermined value among at prime/green lower gray-scale voltage PRGV_x, and each among the gray-scale voltage NBV_x has than the voltage level of bearing each the low predetermined value among red/green lower gray-scale voltage NRGV_x under the negative basket.Therefore, can separate and the individually blue lower gray-scale voltage PBV_x of control and NBV_x and red/green lower gray-scale voltage PRGV_x and NRGV_x according to the data driven unit 100 of the tenth embodiment of the present invention, to keep the color temperature constant of intensity-based level.
Although will be described as according to the data driven unit of the first to the tenth embodiment of the present invention separation and control individually the upper of bluish grey degree step voltage PBV_x and NBV_x and red/green gray-scale voltage PRGV_x and NRGV_x or lower gray level, but the invention is not restricted to this, but can separation as described below and control individually the upper and lower gray level of gray-scale voltage.
Figure 18 is the block diagram that schematically shows according to the representative configuration of the data driven unit 100 of the 11 embodiment of the present invention.Except gray scale step voltage maker 3120 and analog processor 3140, remainder has the identical structure of structure with the first embodiment of the present invention shown in Figure 2 generally according to the data driven unit 100 of the 11 embodiment of the present invention.Therefore, do not repeat description to the same parts among Fig. 2 described above.
Specifically, as shown in figure 19, gray-scale voltage maker 3120 comprises the first to the 5th divider resistance string 3122,3124,3125,3126 and 3127.In general, the gray-scale voltage maker 3120 of this illustrative embodiments comprises the combination of the gray-scale voltage maker 120 of the first embodiment of the present invention shown in Figure 3 and the 6th embodiment of the present invention shown in Figure 13.Therefore, do not repeat description to the same parts among Fig. 3 and 13 described above.
The first divider resistance string 3122 comprises the first to the 4th district 3122a1,3122a2,3122b1 and 3122b2, and the first and second public area 3122c1 and 3122c2.
The first district 3122a1 basically the first district 122a with gray-scale voltage maker 120 shown in Figure 3 is identical, but has different labels.Therefore, the first district 3122a1 generates according to above-mentioned principle and comprises gray-scale voltage PBUV_x on the x of i to the positive gray-scale voltage PBV_i of h to PBV_h the positive basket, and the voltage that generates is offered analog processor 3140.
The first public area 3122c1 is basically identical with the just district of the public area 122c of gray-scale voltage maker 120 shown in Figure 3, but has different labels.Therefore, the first public area 3122c1 generates according to above-mentioned principle and comprises (h-1) to (v+1) positive gray-scale voltage PCV_h-1 to y the positive three looks public gray-scale voltage PCV_y of PCV_v+1, and the voltage that generates is offered analog processor 3140.
Second Region 3122a2 basically the first district 2122a with gray-scale voltage maker 120 shown in Figure 13 is identical, but has different labels.Therefore, Second Region 3122a2 generates according to above-mentioned principle and comprises v to the 0 positive gray-scale voltage PBV_v to z of PBV_0 gray-scale voltage PBLV_z under the basket just, and the voltage of generation is offered analog processor 3140.
The 3rd district 3122b1 basically Second Region 122b with gray-scale voltage maker 120 shown in Figure 3 is identical, but has different labels.Therefore, the 3rd district 3122b1 generates according to above-mentioned principle and comprises gray-scale voltage NBUV_x on x the negative basket of h to the negative gray-scale voltage NBV_h of i to NBV_i, and the voltage that generates is offered analog processor 3140.
The second public area 3122c2 is identical in the textural basically minus zone with the public area 122c of gray-scale voltage maker 120 shown in Figure 3, but has different labels.Therefore, the second public area 3122c2 generates according to above-mentioned principle and comprises (v+1) to (h-1) negative gray-scale voltage NCV_v+1 to y the negative three looks public gray-scale voltage NCV_y of NCV_h-1, and the voltage that generates is offered analog processor 3140.
The 4th district 3122b2 basically Second Region 2122b with gray-scale voltage maker 120 shown in Figure 13 is identical, but has different labels.Therefore, the 4th district 3122b2 generates according to above-mentioned principle and comprises the 0th to v negative gray-scale voltage NBV_0 gray-scale voltage NBLV_z under z the negative basket of NBV_v, and the voltage of generation is offered analog processor 3140.
The second divider resistance string 3124 basically the second divider resistance string 124 with gray-scale voltage maker 120 shown in Figure 3 is identical, but has different labels.Therefore, the second divider resistance string 3124 according to above-mentioned principle generate comprise the x of i to the positive gray-scale voltage PRGV_i of h to PRGV_h at prime/green on gray-scale voltage PRGUV_x, and the voltage that generates offered analog processor 3140.
The 3rd divider resistance string 3125 basically the second divider resistance string 2124 with gray-scale voltage maker 120 shown in Figure 13 is identical, but has different labels.Therefore, the 3rd divider resistance string 3125 generates according to above-mentioned principle and comprises v to the 0 positive gray-scale voltage PRGV_v to z at prime/green lower gray-scale voltage PRGLV_z of PRGV_0, and the voltage that generates is offered analog processor 3140.
The 4th divider resistance string 3126 basically the 3rd divider resistance string 126 with gray-scale voltage maker 120 shown in Figure 3 is identical, but has different labels.Therefore, the 4th divider resistance string 3126 according to above-mentioned principle generate comprise to the negative gray-scale voltage NRGV_h of i to NRGV_i x of h negative red/green on gray-scale voltage NRGUV_x, and the voltage that generates offered analog processor 3140.
The 5th divider resistance string 3127 basically the 3rd divider resistance string 2126 with gray-scale voltage maker 120 shown in Figure 13 is identical, but has different labels.Therefore, the 5th divider resistance string 3127 generates according to above-mentioned principle and comprises the 0th to v negative gray-scale voltage NRGV_0 to z negative red/green lower gray-scale voltage NRGLV_z of NRGV_v, and the voltage that generates is offered analog processor 3140.
Gray-scale voltage maker 3120 according to the 11 embodiment of the present invention utilizes the first divider resistance string 3122 to generate the blue upper and lower gray-scale voltage PBUV_x of positive and negative, PBLV_z, NBUV_x, NBLV_z and positive and negative three looks public gray-scale voltage PCV_y and NVC_y, utilize the second and the 3rd divider resistance string 3124 and 3125 to generate at prime/green upper and lower gray-scale voltage PRGUV_x and PRGLV_z, and utilize the 4th and the 5th divider resistance string 3126 and 3127 to generate negative red/green upper and lower gray-scale voltage NRGUV_x and NRGLV_z.
Perhaps, as shown in figure 20, the second resistor RR2 of the second divider resistance string 3124 can be connected to the dividing potential drop node (between RR1 and the R_1) of the positive gray-scale voltage PBV_i of generation i in the middle of the dividing potential drop node of the first divider resistance string 3122, but not be connected to driving voltage source VDD.Equally, the g voltage grading resistor Rr_g of the 4th divider resistance string 3126 can be connected to the dividing potential drop node (between R_g-1 and the R_g) of the negative gray-scale voltage NBV_i of generation i in the middle of the dividing potential drop node of the first divider resistance string 3122, but not be connected to ground voltage supplies VSS.
As shown in figure 18, analog processor 3140 comprises D/A converter 3142 and output buffer part 144.As shown in figure 21, D/A converter 3142 is except gray-scale voltage PBUV_x, the PBLV_z, NBUV_x, NBLV_z, PCV_y, NCV_y, PRGUV_x, PRGLV_z, NRGUV_x and the NRGLV_z that provide to data converter 3200, and remainder is identical with the D/A converter of the first embodiment of the present invention shown in Figure 5.Therefore, do not repeat description to same parts shown in Figure 5 described above.
Specifically, will from gray-scale voltage maker 3120 at prime/green upper and lower gray-scale voltage PRGUV_x and PRGLV_z and positive three looks public gray-scale voltage PCV_y offer each among the first, the 4th, the 5th and the 8th demoder D1, D4, D5 and the D8.The first, the red or green data RData that utilizes at prime/green upper and lower gray-scale voltage PRGUV_x and PRGLV_z and positive three looks public gray-scale voltage PCV_y to have latched of each among the 4th, the 5th and the 8th demoder D1, D4, D5 and the D8 is converted at prime or green picture signal VData.
Will from gray-scale voltage maker 3120 negative red/green upper and lower gray-scale voltage NRGUV_x and NRGLV_z and negative three looks public gray-scale voltage NCV_y offer each among the second, the 7th, the tenth and the 11 demoder D2, D7, D10 and the D11.The second, each among the 7th, the tenth and the 11 demoder D2, D7, D10 and the D11 utilize negative red/red or green data RData that green upper and lower gray-scale voltage NRGUV_x and NRGLV_z and negative three looks public gray-scale voltage NCV_y will latch is converted to negative red or green picture signal VData.
To offer among the 9th and the 12 demoder D9 and the D12 each from the upper and lower gray-scale voltage PBUV_x of the positive indigo plant of gray-scale voltage maker 3120 and PBLV_z and positive three looks public gray-scale voltage PCV_y.The blue data RData that among the 9th and the 12 demoder D9 and the D12 each utilizes the upper and lower gray-scale voltage PBUV_x of positive indigo plant and PBLV_z and positive three looks public gray-scale voltage PCV_y to have latched is converted to positive blue images signal VData.
To offer among the 3rd and the 6th demoder D3 and the D6 each from the upper and lower gray-scale voltage NBUV_x of the negative indigo plant of gray-scale voltage maker 3120 and NBLV_z and negative three looks public gray-scale voltage NCV_y.The blue data RData that among the 3rd and the 6th demoder D3 and the D6 each utilizes negative blue upper and lower gray-scale voltage NBUV_x and NBLV_z and negative three looks public gray-scale voltage NCV_y to have latched is converted to negative blue images signal VData.
D/A converter 3142 with reference to the mode of Fig. 5 and 6A-6D description, utilizes data routing controller 300 and image signal path controller 400 based on the logic state control data of the first and second polarity control signal POL1 and POL2 and the path of picture signal by previous.Therefore, D/A converter 3142 latch data RData is converted to the picture signal VData of the polar mode with 1 of level or 2 reversing mode of level, and will offer through the picture signal of conversion output buffer part 144.
The picture signal VData of each passage that output buffer part 144 buffering provides from D/A converter 3142, and the picture signal of buffering outwards exported by final output channel.Output buffer part 144 is amplified and output image signal VData based on external loading.
As mentioned above, can separate and control individually blue upper and lower gray-scale voltage PBV and NBV and red/green upper and lower gray-scale voltage PRGV and NRGV according to the data driven unit 100 of the 11 embodiment of the present invention, more constant with the colour temperature that keeps the intensity-based level.
Figure 22 is the schematic circuit according to the exemplary gray scale voltage generator 3120 of the data driven unit 100 of the 12 embodiment of the present invention.Be connected to first to all round section's resistor RR21, Rrg11, RR31 and the Rrg21 of gray-scale voltage maker 3120 according to the data driven unit 100 of the 12 embodiment of the present invention except it also comprises, remainder is identical with the data driven unit 100 according to the 11 embodiment of the present invention shown in 19 with Figure 18 generally.Therefore, do not repeat description to the same parts among Figure 18 and 19 described above.
The first external resistor RR21 is connected in parallel to second red/green resistor RR2 of the second divider resistance string 3124, to finely tune the resistance of second red/green resistor RR2 by the similar manner described in top the second embodiment of the present invention.The second external resistor Rrg11 is connected in parallel to first red/green resistor Rrg1 of the 3rd divider resistance string 3125, to finely tune the resistance of first red/green resistor Rrg1 by the similar manner described in top the 7th embodiment of the present invention.The 3rd external resistor RR31 is connected in parallel to the 3rd red/green resistor RR3 of the 4th divider resistance string 3126, to finely tune the resistance of the 3rd red/green resistor RR3 by the similar manner described in top the second embodiment of the present invention.With all round section's resistor Rrg21 be connected in parallel to second red/green resistor Rrg2 of the 5th divider resistance string 3127, to finely tune the resistance of second red/green resistor Rrg2 by the similar manner described in top the 7th embodiment of the present invention.Therefore, according to the data driven unit 100 of twelveth embodiment of the invention can utilize first to all round each the fine setting positive and negative among section's resistor RR21, Rrg11, RR31 and the Rrg21 red/among green upper and lower gray-scale voltage PRGV and the NRGV each, more constant with the colour temperature that keeps the intensity-based level.
Perhaps, in the gray-scale voltage maker 3120 according to the data driven unit 100 of the 12 embodiment of the present invention, can by as shown in figure 20 and aforesaid same way as the second resistor RR2 of the second divider resistance string 3124 and the g voltage grading resistor Rr_g of the 4th divider resistance string 3126 are connected to the first divider resistance string 3122.
Figure 23 is the schematic circuit according to the exemplary gray scale voltage generator 3120 of the data driven unit 100 of the 13 embodiment of the present invention.According to the gray-scale voltage maker 3120 of the data driven unit 100 of the 13 embodiment of the present invention be generally as be applied to as shown in figure 19 the 3rd embodiment of the present invention the 11 embodiment of the present invention, as shown in Figures 9 and 10 and the combination of the 8th embodiment of the present invention shown in Figure 15.Namely, gray-scale voltage maker 3120 comprises the first to the 4th selector switch RV1 to RV4, to replace the second resistor RR2, first red/green resistor Rrg1, the 3rd resistor RR3 and the second red/green resistor Rrg2 in the second to the 5th divider resistance string 3124,3125,3126 and 3127.The first to the 4th selector switch RV1 to RV4 with the of the present invention the 3rd identical with selector switch in the 8th embodiment as mentioned above.Therefore, do not repeat its detailed description.Therefore, according to the data driven unit 100 of the 13 embodiment of the present invention can utilize the first to the 4th selector switch RV1 in the RV4 each optimization and finely tune positive and negative red/among green upper and lower gray-scale voltage PRGV and the NRGV each.
Figure 24 is the schematic circuit according to the exemplary gray scale voltage generator 3120 of the data driven unit 100 of the 14 embodiment of the present invention.According to the gray-scale voltage maker 3120 of the data driven unit 100 of the 14 embodiment of the present invention be generally as be applied to as shown in figure 19 the 4th embodiment of the present invention the 11 embodiment of the present invention, shown in Figure 11 and the combination of the 9th embodiment of the present invention shown in Figure 16.Therefore, gray-scale voltage maker 3120 can utilize as above each in the i described in the of the present invention the 4th and the 9th embodiment and v positive gray level external voltage PEVi and PEVv and h and the 0th negative gray level external voltage NEVh and NEV0 come optimization and finely tune positive and negative red/among green upper and lower gray-scale voltage PRGV and the NRGV each.
Figure 25 is the schematic circuit according to the exemplary gray scale voltage generator 3120 of the data driven unit 100 of the 15 embodiment of the present invention.According to the gray-scale voltage maker 3120 of the data driven unit 100 of the 15 embodiment of the present invention be generally as be applied to as shown in figure 19 the 5th embodiment of the present invention the 11 embodiment of the present invention, shown in Figure 12 and the combination of the tenth embodiment of the present invention shown in Figure 17.Therefore, gray-scale voltage maker 3120 can utilize as above at the first to the 4th supply voltage AVDD1, AVDD2, AVDD3 and the AVDD4 described in the of the present invention the 5th and the tenth embodiment, by isolating the second to the 5th divider resistance string 3124,3125,3126 and 3127 fully from the first divider resistance string 3122, and separate and control individually the blue upper and lower gray-scale voltage PBV of positive and negative and NBV and positive and negative red/green upper and lower gray-scale voltage PRGV and NRGV.
Figure 26 is the block diagram that schematically shows liquid crystal display according to an illustrative embodiment of the invention.Liquid crystal display according to present embodiment comprises: have the image display panel 2 that is respectively formed at a plurality of pixel cell P in the zone that is limited by many data line DL and many select lines GL, the gate driver 4 that is used for the select lines GL of driving image display panel 2, be used for providing to the data line DL of image display panel 2 data driver 6 of picture signal, be used for providing data-signal R to data driver 6, the timing controller 8 of G and B and control data driver 6 and gate driver 4, and be used for generating a plurality of benchmark gamma voltage GMA1 to GMAj and the benchmark gamma voltage of generation offered the benchmark gamma voltage maker 10 of data driver 6.
Image display panel 2 comprises for keeping bonding relative to one another upper substrate (not shown) and the interval body (not shown) of the cell gap between the infrabasal plate (not shown), and the liquid crystal layer (not shown) in the liquid crystal spatial that is provided by the interval body between upper substrate and the infrabasal plate is provided.Upper substrate comprises at least three color filters (it comprises red color filter, green color filter and blue color filter), is used for color filter separated from one another and limits the black matrix of pixel cell and the public electrode that provides common electric voltage Vcom.Here, can according to liquid crystal mode public electrode is formed on or infrabasal plate on.Infrabasal plate comprises the thin film transistor (TFT) that is respectively formed in the pixel cell P district that is limited by many data line DL and many select lines GL and a plurality of pixel electrodes that are connected to respectively thin film transistor (TFT).Each thin film transistor (TFT) all switches the picture signal that the respective data lines from many data line DL provides in response to conducting (gate-on) voltage that the corresponding select lines from many select lines GL provides to the respective pixel electrode in a plurality of pixel electrodes.
Timing controller 8 arranges view data Data and the data through arranging is offered data driver 6.Timing controller 8 also utilizes at least one in the outer synchronous signal (enabling the data enable signal DE in cycle and the Dot Clock DCLK of specified data transmission frequency such as designation data), generates for the gating control signal GCS of control gate driver 4 with for the data controlling signal DCS that controls data driver 6.At this moment, timing controller 8 can utilize at least one among external horizontal synchronization Hsync and the external vertical synchronizing Vsync, generates gating and data controlling signal GCS and DCS.Data controlling signal DCS comprises: the source initial pulse SSP of the source output enable signal SOE of the data output period of control data driver 6, beginning data sampling, control data sampling source shift clock SSC regularly and the polarity control signal POL of control data voltage polarity.Gating control signal GCS comprises: the output of control gate driver 4 with gating output enable signal GOE that forward voltage is provided, begin to drive the gating initial pulse GSP of gate driver 4 and the gating shift clock GSC that specifies the cycle of forward voltage.
Gate driver 4 generates forward voltage and the forward voltage that generates is sequentially offered select lines GL in response to the gating control signal GCS from timing controller 8.As a result, the select lines GL of image display panel 2 sequentially drives according to the forward voltage from gate driver 4.During the manufacturing process of thin film transistor (TFT), can form gate driver 4 on the substrate that be formed with image display panel 2 thereon and can be connected to select lines GL.
The divider resistance that benchmark gamma voltage maker 10 utilization is connected in series concatenate into have different voltage levels a plurality of benchmark gamma voltage GMA1 to GMAj, and the benchmark gamma voltage of generation offered data driver 6.
Data driver 6 comprises one or more data driven unit.Each data driven unit in the data driver 6 can be above-mentioned any according in the data driven unit 100 of the first to the 15 embodiment of the present invention.Thereby, do not repeat the description to each data driven unit.
In the data controlling signal DCS that is generated by timing controller 8, provide the first polarity control signal POL1 that provides to each data driven unit of data driver 6.The second polarity control signal POL2 can fix by the first logic state or the second logic state according to the indicating characteristic of image display panel 2.Perhaps, can by this mode that changes along with the characteristic of image display panel 2 or view data to be shown, generate the first and second polarity control signal POL1 and the POL2 that provide to each data driven unit 100 of data driver 6 by timing controller 8.
To offer according to each the gamma impact damper 125 in the data driven unit 100 of the first to the 15 embodiment of the present invention as mentioned above to GMAj from the benchmark gamma voltage GMA1 of benchmark gamma voltage maker 10.
Liquid crystal display according to present embodiment comprises one or more data driven unit 100 that can control individually red/green gray-scale voltage and bluish grey degree step voltage.Therefore, can realize being presented at constant colour temperature in the whole zone of black gray level on the image display panel 2 or white gray level.
And, in the liquid crystal display according to present embodiment, in D/A converter 142, be provided with the quantity demoder identical with the output channel number of each data driven unit 100, take with digital data conversion as picture signal.Therefore, can reduce the size of each data driven unit, thereby tackle more neatly the expansion of liquid crystal display.
Can separate and control individually above and/or under the basket gray-scale voltage above and/or under the gray-scale voltage and red/green according to data driven unit of the present invention, to keep the color temperature constant of intensity-based level.In addition, in digital/analog converter, be provided with the identical demoder of output channel number of quantity and data driven unit, thus, reduced the size of data driven unit.
Therefore, comprise can separate and control individually above and/or under the basket gray-scale voltage above and/or under the gray-scale voltage and red/green according to liquid crystal display of the present invention according to data driven unit of the present invention.Therefore, can realize being presented at constant colour temperature in the whole zone of black gray level on the image display panel or white gray level.In addition, because being provided with the identical demoder of the output channel number of quantity and data driven unit in digital/analog converter is picture signal with digital data conversion, so can reduce the size of data driven unit, thereby tackle more neatly the expansion of liquid crystal display.
To those skilled in the art clearly, under the condition that does not depart from the spirit or scope of the present invention, can in the liquid crystal display of data driven unit of the present invention and this data driven unit of use, make various modifications and variations.Thereby, be intended to contain modification of the present invention and modification under the condition of the present invention in the scope that falls into claims and equivalent thereof.

Claims (12)

1. gray-scale voltage maker, this gray-scale voltage maker comprises:
The divider resistance string, it generates blue B gray-scale voltage, red R gray-scale voltage and green G gray-scale voltage, and described divider resistance string comprises:
B gray-scale voltage generating unit;
R/G gray-scale voltage generating unit; And
Public COM gray-scale voltage generating unit,
Wherein, described B gray-scale voltage generating unit and described R/G gray-scale voltage generating unit are in the high grade grey level zone, perhaps in high grade grey level zone and low gray level region, generate individually B gray-scale voltage and R/G gray-scale voltage, make described B gray-scale voltage generating unit and described R/G gray-scale voltage generating unit in described high grade grey level zone, perhaps in described high grade grey level zone and described low gray level region, control individually B gray-scale voltage and R/G gray-scale voltage to keep constant colour temperature
Wherein, described high grade grey level zone comprises high grade grey level voltage,
Wherein, described B gray-scale voltage generating unit and described R/G gray-scale voltage generating unit are in described high grade grey level zone, perhaps in described high grade grey level zone and described low gray level region, generate individually B gray-scale voltage and R/G gray-scale voltage with the compensation colour temperature, and
Wherein, in described high grade grey level zone, in the just bluish grey degree step voltage each has than each the high voltage level at prime/green gray-scale voltage, and in the negative bluish grey degree step voltage each has than each the low voltage level in negative red/green gray-scale voltage, thereby in described high grade grey level zone, perhaps in described high grade grey level zone and described low gray level region, keep constant colour temperature.
2. gray-scale voltage maker according to claim 1, wherein, described R/G gray-scale voltage generating unit is connected to external resistor, to finely tune described R/G gray-scale voltage.
3. gray-scale voltage maker according to claim 1, wherein, described R/G gray-scale voltage generating unit is connected to multiplexer and optionally connects one or more external resistor in a plurality of external resistor, to finely tune described R/G gray-scale voltage.
4. gray-scale voltage maker according to claim 1, wherein, described R/G gray-scale voltage generating unit is connected to external voltage source, to finely tune described R/G gray-scale voltage.
5. gray-scale voltage maker according to claim 1, wherein, described R/G gray-scale voltage generating unit and described B gray-scale voltage generating portion from and be connected to independently supply voltage source, to finely tune described R/G gray-scale voltage.
6. gray-scale voltage maker according to claim 1, wherein,
Described B gray-scale voltage generating unit comprises just high B gray-scale voltage generating unit and negative high B gray-scale voltage generating unit,
Described R/G gray-scale voltage generating unit comprises just high R/G gray-scale voltage generating unit and negative high R/G gray-scale voltage generating unit, and
Described COM gray-scale voltage generating unit comprises positive COM gray-scale voltage generating unit and negative COM gray-scale voltage generating unit,
Wherein, described divider resistance string comprises first, second portion, third part and the 4th part, described first comprises described just high B gray-scale voltage generating unit and described just high R/G gray-scale voltage generating unit, described second portion comprises described positive COM gray-scale voltage generating unit, described third part comprises described negative COM gray-scale voltage generating unit, and described the 4th part comprises described negative high B gray-scale voltage generating unit and described negative high R/G gray-scale voltage generating unit.
7. gray-scale voltage maker according to claim 6, wherein, described just high R/G gray-scale voltage generating unit is connected to driving voltage source VDD, and described negative high R/G gray-scale voltage generating unit is connected to ground voltage supplies VSS.
8. gray-scale voltage maker according to claim 6, wherein, described just high R/G gray-scale voltage generating unit is connected to described just high B gray-scale voltage generating unit, and described negative high R/G gray-scale voltage generating unit is connected to described negative high B gray-scale voltage generating unit.
9. gray-scale voltage maker according to claim 1, wherein,
Described B gray-scale voltage generating unit comprises:
Just high B gray-scale voltage generating unit;
Just low B gray-scale voltage generating unit;
Negative high B gray-scale voltage generating unit; And
Negative low B gray-scale voltage generating unit,
Described R/G gray-scale voltage generating unit comprises:
Just high R/G gray-scale voltage generating unit;
Just low R/G gray-scale voltage generating unit;
Negative high R/G gray-scale voltage generating unit; And
Negative low R/G gray-scale voltage generating unit, and
Described COM gray-scale voltage generating unit comprises positive COM gray-scale voltage generating unit and negative COM gray-scale voltage generating unit,
Wherein, described divider resistance string comprises first, second portion, third part, the 4th part, the 5th part and the 6th part, described first comprises described just high B gray-scale voltage generating unit and described just high R/G gray-scale voltage generating unit, described second portion comprises described positive COM gray-scale voltage generating unit, described third part comprises described just low B gray-scale voltage generating unit and described just low R/G gray-scale voltage generating unit, described the 4th part comprises described negative high B gray-scale voltage generating unit and described negative high R/G gray-scale voltage generating unit, described the 5th part comprises described negative COM gray-scale voltage generating unit, and described the 6th part comprises described negative low B gray-scale voltage generating unit and described negative low R/G gray-scale voltage generating unit.
10. gray-scale voltage maker according to claim 9, wherein, described just high R/G gray-scale voltage generating unit is connected to driving voltage source VDD, and described negative high R/G gray-scale voltage generating unit is connected to ground voltage supplies VSS.
11. gray-scale voltage maker according to claim 9, wherein, described just high R/G gray-scale voltage generating unit is connected to described just high B gray-scale voltage generating unit, and described negative high R/G gray-scale voltage generating unit is connected to described negative high B gray-scale voltage generating unit.
12. a data driven unit that is used for liquid crystal display, this data driven unit comprises:
Control circuit, it carries out relaying to red R data-signal, green G data-signal and blue B data-signal;
The gray-scale voltage maker, it generates gray-scale voltage;
Digital processing unit, it latchs described R data-signal, described G data-signal and described B data-signal; And
Analog processor, it will be converted to from the R data-signal that has latched, G data-signal and the B data-signal that described digital processing unit provides the picture signal that will show in described liquid crystal display,
Described gray-scale voltage maker be according to claim 1-11 in gray-scale voltage maker in any one.
CN2008101869907A 2007-12-13 2008-12-12 Data driving device and liquid crystal display device using the same Expired - Fee Related CN101458911B (en)

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