KR20090121592A - Data driving device and liquid crystal display device using the same - Google Patents

Abstract

PURPOSE: A data driving device and a liquid crystal display device using the same are provided to reduce a size of a data driver by configuring a number of decoder of the digital analog converter as much as an output channel number of the data driver. CONSTITUTION: A data driver is composed of a digital processing part, a gray voltage generator, and an analog processing part. The digital processing part(130) latches inputted red, green, and blue data, and a gray voltage generator(120) generates a positive and negative green grayscale voltage, red/green a grayscale voltage, and 3 common grayscale voltages according to an option signal supplied to the digital processing unit by using a reference gamma voltage and a first and a second power. The analog processing part(140) converts the red and green latch data into a red/green image data by using the positive and negative green grayscale voltage, the positive and negative 3 common grayscale voltages.

Description

DATA DRIVING DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving device and a liquid crystal display using the same, and more particularly, to a data driving device capable of compensating color temperature according to gray scale and sharing a data driving device and a liquid crystal display using the same. It is about.

Recently, the display field for visually expressing electrical information signals has been rapidly developed as the information age has entered, and in response to this, various flat panel display devices having excellent performance of thinning, light weight, and low power consumption have been developed. Flat Display Device has been developed and is rapidly replacing the existing Cathode Ray Tube (CRT).

Specific examples of such a flat panel display device include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electroluminescent display device. (Electro luminescence Display Device, ELD) and the like, these are common to the flat panel display panel that implements the image as an essential component, the flat panel display panel has a pair of light emitting or polarizing material layer in between It has a configuration in which a transparent insulating substrate is faced and bonded together.

The dual liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the image display device includes a display panel having a liquid crystal cell, a backlight unit for irradiating light to the display panel, and a driving circuit for driving the liquid crystal cell.

The liquid crystal display displays gradations according to light transmittances of red, green, and blue dots (Dot) according to data signals of red (R), green (G), and blue (B), respectively. In this case, each of the red, green, and blue data signals uses the same gray voltage.

Accordingly, although the electro-optical characteristics of each of the red, green, and blue dots are clearly different, there is a problem that the color temperature is changed according to the gray level by using the same gray voltage.

That is, the color temperature is determined by the mixing ratio of the luminance of each of the red, green, and blue dots constituting the pixel. However, since the data signals of the red, green, and blue colors cannot be individually controlled when the grayscale is increased or decreased, As shown in the drawing, nonuniformity occurs in the upper and lower grayscale regions and continuous attempts to solve the problem have been made.

Therefore, in order to improve this phenomenon, in models where the red, green, and blue data signals are individually controlled, the red, green, and blue R-strings are independently present. It became unusable and made it difficult to share.

In order to solve the above problems, the present invention can compensate for the color temperature according to the gray scale (Gray Scale) and can be used without changing the data driver to the model that requires white tracking and the model is not required It is possible to provide a data driver and a liquid crystal display using the same.

According to another aspect of the present invention, there is provided a data driving device including: a digital processor configured to latch inputted red, green, and blue data; In accordance with the option signal supplied from the digital processing unit, a plurality of reference gamma voltages and blue and gray voltages of red and green colors and red and green gray voltages using the first and second power sources are used. A gradation voltage generation unit generating the gradations; And red and green latch data supplied from the digital processor using the positive and negative red / green gradation voltages and the positive and negative tricolor common gradation voltages as red and green image signals. The analog processing unit converts the blue latch data supplied from the digital processing unit into a blue image signal by converting the blue and gray gradation voltages of the positive and negative polarities and the three common color gradation voltages of the positive and negative polarities. It is configured to include.

The data driver according to the present invention can maintain the color temperature according to the gray level by separately controlling the upper and / or lower gray voltage for blue and the upper and / or lower gray voltage for red / green. Furthermore, the present invention can reduce the size of the data driver by configuring the number of decoders of the digital analog converter equal to the number of output channels of the data driver.

In addition, the liquid crystal display according to the present invention adds a multiplexer for selecting a model in which white tracking occurs and a model in which white tracking does not occur in the gray voltage generator, thereby enabling a common use of a data driver to reduce manufacturing costs. The production efficiency can be improved.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

2 is a block diagram schematically illustrating a data driving device according to a first embodiment of the present invention.

Referring to FIG. 2, the data driver 100 according to the first embodiment of the present invention relays red, green, and blue data signals R, G, and B and data control signals DCs supplied from the outside. Digital processing unit for latching the data signal (R, G, B) supplied from the control block 110 in accordance with the control block 110, data control signals (EN1, SSC, SOE) supplied from the control block 110 ( 130, the three-color common gradation voltage (CV) and the blue gradation voltages (PBV, NBV) are generated according to the option signal () supplied from the digital processing unit 130, and the red / green gradation voltages (PRGV, NRGV). ) Latch data RData supplied from the digital processor 130 is supplied from the control block 110 using the gray voltage generator 120 and gray voltages CV, PBV, NBV, PRGV, and NRGV. Converts to an image signal VData having a data polarity corresponding to the first and second polarity control signals POL1 and POL2. It is configured to include an analog processor 140 for outputting.

The control block 110 restores the N-bit red, green, and blue data signals R, G, and B supplied from the outside to correspond to the data interface method, and supplies them to the digital processor 130. In addition, the control block 110 includes data including a source start pulse SSP, a source shift clock SSC, a source output signal SOE, and first and second polarity control signals POL1 and POL2 supplied from an external source. Each of the digital processor 130 and the analog processor 140 is controlled using the control signal DCS.

As shown in FIG. 3, the gray voltage generator 120 includes first to third divided resistance strings 122, 124, and 126.

The first divided resistor row 122 includes first to g-th divided resistors R_1 to R_g connected in series between the driving power source VDD and the base power source VSS. The first divided resistor string 122 is divided into a first region 122a, a common region 122c, and a second region 122b according to a voltage generated by voltage division using a resistor.

The first region 122a includes first to e-th voltage divider resistors R_1 to R_e connected in series. In addition, the divided gamma node in the middle of the first region 122a includes a first gamma voltage of the first to k1 (k1 is a natural number smaller than j / 2) of j (where j is a natural number) reference gamma voltages GMA_j. GMA_1 to GMA_k1) are supplied. For example, the first reference gamma voltage GMA_1 may or may not be supplied to the divided nodes R_1 and R_2 that generate the i-th gray voltage PBV_i among the divided nodes of the first region 122a. The second reference gamma voltage GMA_2 may or may not be supplied to the divided nodes R_2 and R_3 that generate the i-1 th gray voltage PBV_i-1. In addition, the k th reference gamma voltage GMA_k1 is supplied to the divided node R_e-1 and R_e generating the h th gray voltage PBV_h. Here, i is N squared of 2 when the number of bits of the data signal is N. For example, i may be 255 when the number of bits of the data signal is eight. In addition, h is a natural number smaller than i, and may be, for example, 223 when the number of bits of the data signal is eight. In addition, k1 may be set to a natural number smaller than j / 2 according to at least one of the electro-optical characteristics, gamma characteristics, and color temperature characteristics of the liquid crystal. For example, k1 may be 2 or 3 when j is 18.

The first region 122a includes the i-th to h-th gray voltages PBV_i to PBV_h generated by voltage division at each divided node formed between the first to e-th voltage divider resistors R_1 to R_e. The upper blue gray-level voltage PBV_x having x pieces is supplied to the analog processor 140.

The common area 122c includes the e-th to f-th voltage divider resistors R_e to R_f. In the divided voltage node in the middle of the common area 122c, the gamma k1 + 1 to k2-1 (where k2 is a natural number larger than j / 2 and smaller than j) among the j reference gamma voltages GMA_j Voltages GMA_k1 + 1 to GMA_k2-1 are supplied. Each of the k1 + 1 to k2-1 reference gamma voltages GMA_k1 + 1 to GMA_k2-1 has a common or boiling interval according to the electro-optical, color temperature, and gamma characteristics of the liquid crystal. It can be supplied to any partial pressure node of. For example, the j / 2th reference gamma voltage GMA_j / 2 is supplied to the divided node which generates the positive tricolor common zero grayscale voltage PCV_0 among the divided nodes of the common region 122c, and receives the j / th reference gamma voltage GMA_j / 2. The 2-1 reference gamma voltage GMA_j / 2-1 may or may not be supplied to the divided node that generates the positive tricolor common first gray voltage voltage PCV_1 among the divided nodes of the common area 122c. In addition, each of the k1 + 1 to j / 2-2 reference gamma voltages GMA_k1 + 1 to GMA_j / 2-2 has three colors of positive polarity among the divided nodes of the common region 122c so as to have equal or boiling intervals. It is supplied to an arbitrary divided node which generates each of the common third to h-1 gradation voltages PCV_3 to PCV_h-1. In addition, the j / 2 + 1 reference gamma voltage GMA_j / 2 + 1 is supplied to the divided node which generates the negative tricolor common zero gradation voltage NCV_0 among the divided nodes of the common region 122c, The j / 2 + 2 reference gamma voltage GMA_j / 2 + 2 is supplied to the divided node which generates the negative tricolor common first gradation voltage NCV_1 among the divided nodes of the common area 122c. In addition, each of the j / 2 + 3 to k2-1 reference gamma voltages GMA_j / 2 + 3 to GMA_k2-1 has a negative polarity among the divided nodes of the common region 122c so as to have an equal interval or a boiling interval. It is supplied to an arbitrary divided node which generates each of the color-sharing third to h-1 gradation voltages NCV_3 to NCV_h-1.

The common area 122c includes the positive electrode from the positive h-1 gradation voltage PCV_h-1 generated by voltage division at each divided node formed between the e-th to f-th voltage divider resistors R_e to R_f. The positive three-color common gradation voltage PCV_y having y pieces including up to the zeroth gradation voltage PCV_0 and the negative zeroth gradation voltage NCP_0 to the negative h-1 gradation voltage NCV_h- 1) Each of the three negative common gradation voltages NCV_y having y pieces including up to is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the common area 122c generates 223 positive tricolor common gradation voltages PCV_y including the zeroth to 222th gradation voltages PCV_0 to PCV_222 of the positive polarity. In addition, 223 negative three-color common gradation voltages NCV_y including the zeroth to 222th gradation voltages NCV_0 to NCV_222 are generated.

On the other hand, at least one dummy resistor (not shown) between the divided node for generating the positive tricolor common zero gray voltage (PCV_0) and the divided node for generating the negative tricolor common zero gray voltage (NCV_0). This can be connected.

The second region 122b includes the f-th to g-th voltage divider resistors R_f to R_g connected in series. The kth to jth reference gamma voltages GMA_k2 to GMA_j of the j reference gamma voltages GMA_j are supplied to the divided nodes in the middle of the second region 122b. For example, a k2 reference gamma voltage GMA_k2 is supplied to the divided nodes R_f and R_f + 1 that generate the h-th gray voltage NBV_h among the divided nodes of the second region 122b, and the i-th The j-1 reference gamma voltage GMA_j-1 may or may not be supplied to the divided node R_g-2 and R_g-1 generating the -1 gray voltage NBV_i-1. In addition, the j th reference gamma voltage GMA_j may or may not be supplied to the divided nodes R_g-1 and R_g generating the i th gray voltage NBV_i. Here, k2 may be set to a natural number larger than j / 2 and smaller than j according to at least one of the electro-optical characteristics, gamma characteristics, and color temperature characteristics of the liquid crystal, for example, j-1 or j-2. Can be.

The second region 122b includes the h-th gray voltage NBV_h through the i-th gray voltage NBV_i generated by voltage division at each divided node formed between each of the f th to g th divided resistors R_f to R_g. The blue upper gray-level voltage NBV_x having x pieces including the power supply to the analog processor 140 is supplied. Here, the negative blue upper grayscale voltage NBV_x having x pieces has a voltage level symmetrical with the positive blue upper grayscale voltage PBV_x having x pieces based on a common voltage (not shown).

The second divided resistance string 124 is connected between the driving power supply VDD and the common region 122c of the first divided resistance row 122 so as to be connected in parallel with the first region 122a of the first divided resistance row 122. Resistances of the first to e-1 voltage-dividing resistors Rr_1 to Rr_e-1 for positive red / green with different resistance values connected in series and the first region 122a of the first voltage-dividing resistor row 122. First to nth multiplexers selectively outputting the i-th to h-th gray voltages PBV_i to PBV_h for the positive blue light and the i-th to h-th gray voltages PRGV_i to PRGV_h for the red / green polarity And (Mux1-1 to Mux1-n). In this case, some of the divided resistors of the first to e-1 divided resistors Rr_1 to Rr_e-1 for red / green of the positive polarity may have the same resistance value.

The first to e-th voltage divider resistors Rr_1 to Rr_e-1 for red / green polarity are connected in series between the driving power supply VDD and the e-th voltage divider resistor R_e of the first voltage divider resistor row 122. . Here, the second divided resistor string 124 has the same structure as the first region 122a of the first divided resistor string 122. Accordingly, each of the first to e-1 divided voltage resistors Rr_1 to Rr_e-1 for the positive red / green polarity is configured to include the first to e− configured in the first region 122a of the first divided voltage resistance row 122. Each of the voltage dividing resistors R_1 to R_e-1 has the same resistance value.

In addition, at least one positive external voltage PEVi and PEVi-1 and the k1 th reference gamma voltage GMA_k1 are supplied from the outside to the divided node in the middle of the second divided resistor row 124. For example, for the i-th gray level corresponding to the i-th gray voltage PRGV_i to the divided voltage node Rr_1 and Rr_2 that generate the i-th gray voltage PRGV_i among the divided voltage nodes of the second divided resistor row 124. The positive external voltage PEVi may or may not be supplied, and the i-1 gray voltage PRGV_i-1 may be applied to the divided node Rr_2 and Rr_3 that generate the i-1 th gray voltage PRGV_i-1. The i-1 gradation positive external voltage PEVi-1 corresponding to the i-1 gray level may or may not be supplied. Also, the k1 th reference gamma voltage GMA_k1 is supplied to the divided node Rr_e-1 and Rr_e that generates the h-th gray voltage PRGV_h.

The first to nth multiplexers Mux1 to Mux1-n may be formed at resistances of the first region 122a of the first divided resistor row 122 according to the option signal Opts supplied from the digital processor 130. The positive blue i-th to h-th gray voltages PBV_i to PBV_h and the positive red / green i-th to h-th gray voltages PRGV_i to PRGV_h are selectively supplied.

In other words, the first to nth multiplexers Mux1 to Mux1 to n may have positive electrodes according to option signals opts output from the digital processor 130 depending on whether the white tracking is a model. The i-th grayscale voltage PRGV_i to the h-th grayscale voltage PRGV_h generated by voltage division at each divided node formed between the first to e-1 divided voltage resistances Rr_1 to Rr_e-1 for red / green I to th generated by voltage distribution at each divided node formed between each of the positive red / green high gray-level voltages PRGV_x having the number of x's) and the first to e-th voltage divider resistors R_1 to R_e. The voltage of any one of the positive blue upper grayscale voltages PBV_x including the x th gray voltages PBV_i to PBV_h is selected and supplied to the analog processor 140.

The third divided resistor row 126 is connected between the common area 122c of the first divided resistor row 122 and the base power supply VSS so as to be connected in parallel with the second area 122b of the first divided resistor row 122. Of the red / green negative f + 1 to gth divided voltage resistors Rr_f + 1 to Rr_g having different resistances connected in series and the second region 122b of the first divided resistor row 122; First to selectively output the negative blue i-th to h-th gray voltages NBV_i to NBV_h and q negative polarity red / green i-th to h-th gray voltages NRGV_i to NRGV_h generated by the resistors To m-th multiplexers (Mux2-1 to Mux2-m). In this case, some of the divided resistances of the negative red / green f + 1 to g th divided resistors Rr_f + 1 to Rr_g may have the same resistance value.

The first to e-1 voltage divider resistors Rr_f + 1 to Rr_g for negative red / green are connected in series between the f-th divider resistor R_f of the first voltage divider resistor row 122 and the base power supply VSS. do. The third divided resistor string 126 has the same structure as the second region 122b of the first divided resistor string 122. Accordingly, each of the negative red / green (f + 1 to g-th) voltage divider resistors Rr_f + 1 to Rr_g each includes the first f + 1 to g regions formed in the second region 122b of the first voltage divider resistor array 122. It has the same resistance value as each of the g th partial resistances R_f + 1 to R_g.

The k2 reference gamma voltage GMA_k2 and at least one negative external voltage NEV1.NEV2 are supplied to the voltage dividing node in the middle of the third voltage dividing resistor row 126. For example, a k2 reference gamma voltage GMA_k2 is supplied to the divided nodes R_f and R_f + 1 that generate the h-th gray voltage NRGV_h among the divided nodes of the third divided resistor row 126. A negative polarity external to the i-1 gradation corresponding to the i-1 gradation voltage PRGV_i-1 is applied to the divided node Rr_g-2 and Rr_g-1 generating the i-1 gradation voltage NRGV_i-1. The voltage NEVi-1 is supplied. In addition, the i-th gray-level negative external voltage NEVi corresponding to the i-th gray voltage NRGV_i may or may not be supplied to the divided node Rr_g-1 and Rr_g generating the i-th gray voltage NRGV_i. Can be.

The first to mth multiplexers Mux2-1 to Mux2-m are formed at the resistances of the second region 122b of the first divided resistor row 122 according to the option signals Opts supplied from the digital processor 130. The generated negative blue to i-th gray voltages NBV_i to NBV_h and negative red / green i-th to h-th gray voltages NRGV_i to NRGV_h are selectively outputted.

In other words, the first to m th multiplexers Mux2-1 to Mux2-m are negative depending on the option signals (opts) output from the digital processor 130 depending on whether the white tracking is a model. H-th gray voltage (NRGV_h) to i-th gray voltage generated by voltage division at each divided node formed between the first to e-1 divided resistors Rr_f + 1 to Rr_g for red / green of polarity Generated by voltage distribution at each divided node formed between each of the q negative polarity red / green upper gray-level voltages (NRGV_x) having x pieces including NRGV_i) and the f-th to g-th voltage divider resistors R_f to R_g. The voltage of any one of the negative blue upper grayscale voltages NRGV_x including the x th to hth gray voltages NBV_i to NBV_h is selected and supplied to the analog processor 140.

As described above, the gray voltage generator 120 uses the first divided resistance string 122 to display the upper and lower gray voltages PBV_x and NBV_x for the positive and negative polarities, and the three common color voltages for the positive and negative polarities. (CV) is generated, and the upper and lower gray level voltages PRGV_x and NRGV_x for the positive and negative polarities are generated using the second and third voltage divider resistor lines 124 and 126. In addition, the gray voltage generator 120 determines whether to use the white tracking method according to the option signal (opts) supplied from the digital processor 130 and supplies the analog signal to the analog processor 140 so that the white tracking is not required. Also in the data driving apparatus 100 of the present invention can be applied.

At this time, in order to compensate for the color temperature, each of the positive blue upper gray voltages PBV_x has a voltage level higher than that of each of the positive red / green high gray voltages PRGV_x, and also has a negative voltage. Each of the blue upper grayscale voltages NBV_x has a voltage level lower than that of each of the negative red / green upper grayscale voltages NRGV_x.

In FIG. 2, each of the first to j-th reference gamma voltages GMA_1 to GMA_j supplied to the gray voltage generator 120 is buffered by the gamma buffer unit 125 built in the data driver 100. After output to the outside of the driving device 100 (for example, a data printed circuit board) is supplied again. This is to compensate for the deviation of the first to jth reference gamma voltages GMA_1 to GMA_j supplied to the data driving apparatuses 100 when a plurality of data driving apparatuses 100 are used.

The digital processor 130 includes a shift register unit 132 and a latch unit 134.

The shift register unit 132 sequentially shifts the first enable signal EN1 corresponding to the source start pulse SSP from the control block 110 according to the source shift clock SSC to convert the sampling signal Sam. And the generated sampling signal Sam is supplied to the latch unit 134. The shift register unit 132 is a bidirectional shift register, and the forward carry signal Car / EN2 or the reverse carry signal Car / EN1 generated by the shift register unit 132 is externally controlled through the control block 110. It is supplied by the source start pulse SSP of another data driver.

The latch unit 134 latches each of the red, green, and blue data signals R, G, and B supplied from the control block 110 according to the sampling signal Sam supplied from the shift register unit 132. The latch unit 134 supplies the latch data RData to the analog processor 140 according to the source output signal SOE. At this time, the latch unit 134 sequentially latches each of the red, green, and blue data signals R, G, and B corresponding to the number of output channels of the data driver 110. That is, the latch unit 134 sequentially latches the data signal R of the first channel to the data signal B of the last channel, and then the data signals R of all channels latched according to the source output signal SOE. , G, B) are output at the same time.

The analog processor 140 includes a digital analog converter 142 and an output buffer unit 144.

As illustrated in FIG. 4, the digital-to-analog converter 142 includes a plurality of data conversion blocks having 12 channels, and each data conversion block has x numbers supplied from the gray voltage generator 120. Positive and negative blue upper gray voltages (PBV_x, NBV_x), y positive and negative three-color common gray voltages (PCV_y, NCV_y), and x positive and negative polarities A data converter 200 for converting each of the red, green, and blue latch data RData input using the red / green upper gray voltages PRGV_x and NRGV_x into red, green, and blue image signals; Red, green, and blue latches supplied to the data converter 200 from the first to twelfth input channels Cm-11 to Cm, where m is a multiple of 12, according to the first and second polarity control signals POL1 and POL2. A data path controller 300 for controlling each path of data RData; And an image signal for controlling a path of each of the red, green, and blue image signals VData supplied from the data converter 200 to the output buffer unit 144 according to the first and second polarity control signals POL1 and POL2. It is configured to include a path control unit 400.

The data converter 200 includes first to twelfth decoders D1 to D12 in which a positive polarity (P) decoder and a negative polarity (N) decoder are disposed to correspond to the horizontal two dot inversion scheme. In this case, the first to twelfth decoders D1 to D12 are repeatedly arranged in the order of the positive polarity (P) decoder, the negative polarity (N) decoder, the negative polarity (N) decoder, and the positive polarity (P) decoder.

Each of the first, fourth, fifth, and eighth decoders D1, D4, D5, and D8 has a positive red / green upper grayscale voltage PRGV_x having x pieces supplied from the grayscale voltage generator 120, and The red or green latch data RData is converted into a positive red or green image signal VData by using the y-positive tricolor common gradation voltage PCV_y.

Each of the second, seventh, tenth, and eleventh decoders D2, D7, D10, and D11 has a negative upper / lower gray voltage (NRGV_x) having x supplied from the gray voltage generator 120. And the red or green latch data RData is converted to the negative red or green image signal VData by using the negative three-color common gradation voltage NCV_y.

Each of the ninth and twelfth decoders D9 and D12 has a positive blue upper gray-level voltage PBV_x having x pieces and a y-numbered positive three-color common gray level voltage supplied from the gray voltage generator 120. The blue latch data RData is converted into a positive blue image signal VData using PCV_y.

Each of the third and sixth decoders D3 and D6 has a negative blue upper grayscale voltage NBV_x having x and a negative tricolor common gray having y. The blue latch data RData is converted into a negative blue image signal VData using the voltage NCV_y.

The data path controller 300 controls the polarity of the image signal to correspond to the horizontal 1 dot or horizontal 2 dot inversion scheme according to the first and second polarity control signals POL1 and POL2. And first and second data path controllers 310 and 320 for controlling the paths of the latch data RData supplied to the data converter 200 from 11 to Cm.

The first data path controller 310 includes first to tenth data path selectors S1 to S10.

The first data path selector S1 outputs a blue latch data RData supplied to the third or twelfth input channels Cm-9 and Cm according to the second polarity control signal POL2. A second switching unit for outputting blue latch data RData supplied to the ninth or third input channels Cm-3 and Cm-9 according to the unit S1a and the second polarity control signal POL2. S1b). The first switching unit S1a selects and outputs the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the twelfth input channel Cm is selected and output according to the second polarity control signal POL2. The second switching unit S1b selects and outputs the blue latch data RData of the ninth input channel Cm-3 according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the third input channel Cm-9 is selected and output according to the second polarity control signal POL2.

The second data path selector S2 is connected to the red latch data RData or the eleventh input channel Cm-1 supplied to the fourth input channel Cm-8 according to the second polarity control signal POL2. The first switching unit S2a outputting the supplied green latch data RData and the red latch data RData supplied to the tenth input channel Cm-2 according to the second polarity control signal POL2. Or a second switching unit S2b for outputting red latch data RData supplied to the fourth input channel Cm-8. The first switching unit S2a selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2 of the first logic state, and outputs the red latch data RData of the second logic state. The green latch data RData of the eleventh input channel Cm−1 is selected and output according to the second polarity control signal POL2. The second switching unit S2b selects and outputs the red latch data RData of the tenth input channel Cm-2 according to the second polarity control signal POL2 of the first logic state, and outputs the red latch data RData of the second logic state. The red latch data RData of the fourth input channel Cm-8 is selected and output according to the second polarity control signal POL2.

The third data path selector S3 selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2 in the first logic state and outputs the second logic. The red latch data RData of the tenth input channel Cm-2 is selected and output according to the second polarity control signal POL2 in the state.

The fourth data path selector S4 selects and outputs the blue latch data RData of the twelfth input channel Cm according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the ninth input channel Cm-3 is selected and output according to the second polarity control signal POL2.

The fifth data path selector S5 is connected to the red latch data RData or the eighth input channel Cm-4, which is supplied to the seventh input channel Cm-5 according to the second polarity control signal POL2. Green latch data RData or seventh of the eighth input channel Cm-4 according to the first switching unit S5a outputting the supplied green latch data RData and the second polarity control signal POL2. And a second switching unit S5b for outputting red latch data RData supplied to the input channel Cm-5. The first switching unit S5a selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2 of the first logic state, and outputs the red latch data RData of the second logic state. The green latch data RData of the eighth input channel Cm-4 is selected and output according to the second polarity control signal POL2. The second switching unit S5b selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2 of the first logic state, and outputs the selected data. The red latch data RData of the seventh input channel Cm-5 is selected and output according to the second polarity control signal POL2.

The sixth data path selector S6 may include the red latch data RData of the eighth input channel Cm-4 or the red latch data of the seventh input channel Cm-5 according to the second polarity control signal POL2. The red latch data RData or the eighth input channel Cm-4 of the seventh input channel Cm-5 according to the first switching unit S6a for outputting (RData) and the second polarity control signal POL2. And a second switching unit S6b for outputting the green latch data RData. The first switching unit S6a selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2 of the first logic state, and outputs the selected data. The red latch data RData of the seventh input channel Cm-5 is selected and output according to the second polarity control signal POL2. The second switching unit S6b selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2 of the first logic state, and outputs the second latch state S6b. The green latch data RData of the eighth input channel Cm-4 is selected and output according to the second polarity control signal POL2.

The seventh data path selector S7 selects and outputs the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2 in the first logic state, and outputs the second logic. The blue latch data RData of the sixth input channel Cm-6 is selected and output according to the second polarity control signal POL2 in the state.

The eighth data path selector S8 selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic. The green latch data RData supplied to the fifth input channel Cm-7 is selected and output according to the second polarity control signal POL2 in the state.

The ninth data path selector S9 includes the green latch data RData of the eleventh input channel Cm-1 or the red latch data of the fourth input channel Cm-8 according to the second polarity control signal POL2. The green latch data RData of the fifth input channel Cm-7 or the eleventh input channel Cm-1 according to the first switching unit S9a for outputting (RData) and the second polarity control signal POL2. And a second switching unit S9b for outputting the green latch data RData. The first switching unit S9a selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2 of the first logic state and outputs the second latch state. The red latch data RData of the fourth input channel Cm-8 is selected and output according to the second polarity control signal POL2. The second switching unit S9b selects and outputs the green latch data RData of the fifth input channel Cm-7 according to the second polarity control signal POL2 of the first logic state, and outputs the selected data. The green latch data RData of the eleventh input channel Cm−1 is selected and output according to the second polarity control signal POL2.

The tenth data path selector S10 may include the blue latch data RData of the twelfth input channel Cm or the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2. ) Blue latch data RData of the sixth input channel Cm-6 or blue latch of the twelfth input channel Cm according to the first switching unit S10a and the second polarity control signal POL2. And a second switching unit S10b for outputting data RData. The first switching unit S10a selects and outputs the blue latch data RData of the twelfth input channel Cm according to the second polarity control signal POL2 of the first logic state, and outputs the second latch state of the second logic state. The blue latch data RData of the third input channel Cm-9 is selected and output according to the polarity control signal POL2. The second switching unit S10b selects and outputs the blue latch data RData of the sixth input channel Cm-6 according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the twelfth input channel Cm is selected and output according to the second polarity control signal POL2.

The second data path control unit 320 includes first to twelfth data selection units M1 to M12.

The first data selector M1 supplies the red latch data RData of the first input channel Cm-11 to the first decoder D1 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the green latch data RData of the second input channel Cm-10 is supplied to the first decoder D1.

The second data selector M2 selects the green latch data RData of the second input channel Cm-10 to the second decoder D2 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the red latch data RData of the first input channel Cm-11 is supplied to the second decoder D2.

The third data selector M3 is the third or twelfth input supplied from the first switch S1a of the first data path selector S1 when the first polarity control signal POL1 is in the first logic state. When the blue latch data RData of the channels Cm-9 and Cm is supplied to the third decoder D3, and the first polarity control signal POL1 is in the second logic state, the first data path selector S1. The blue latch data RData of the ninth or third input channels Cm-3 and Cm-9 supplied from the second switching unit S1b of the second supply unit S1b is supplied to the third decoder D3.

The fourth data selector M4 is the fourth input channel Cm supplied from the first switch S2a of the second data path selector S2 when the first polarity control signal POL1 is in the first logic state. The red latch data RData of -8) or the green latch data RData of the eleventh input channel Cm-1 is supplied to the fourth decoder D4, and the first polarity control signal POL1 is supplied with the second logic. In the state of the red latch data (RData) or the fourth input channel (Cm-8) of the tenth input channel (Cm-2) supplied from the second switching unit (S2b) of the second data path selector (S2). The red latch data RData is supplied to the fourth decoder D4.

The fifth data selector M5 supplies the green latch data RData of the fifth input channel Cm-7 to the fifth decoder D5 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the green latch data RData or the tenth input channel of the eleventh input channel Cm-1 supplied from the third data path selector S3 may be The red latch data RData of Cm-2 is supplied to the fifth decoder D5.

The sixth data selector M6 supplies the blue latch data RData of the sixth input channel Cm-6 to the sixth decoder D6 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the blue latch data RData of the twelfth or ninth input channels Cm and Cm-3 supplied from the fourth data path selector S4 is received. The sixth decoder D6 is supplied.

The seventh data selector M7 is the seventh input channel Cm supplied from the first switch S5a of the fifth data path selector S5 when the first polarity control signal POL1 is in the first logic state. The red latch data RData of -5) or the green latch data RData of the eighth input channel Cm-4 is supplied to the seventh decoder D7, and the first polarity control signal POL1 is supplied with the second logic. In the state of the green latch data of the eighth input channel (Cm-4) or the seventh input channel (Cm-5) of the eighth input channel (Cm-4) supplied from the second switching unit (S5b) of the fifth data path selector (S5). The red latch data RData is supplied to the seventh decoder D7.

The eighth data selector M8 is the eighth input channel Cm supplied from the first switch S6a of the sixth data path selector S6 when the first polarity control signal POL1 is in the first logic state. The green latch data RData of -4) or the red latch data RData of the seventh input channel Cm-5 is supplied to the eighth decoder D8, and the first polarity control signal POL1 receives the second polarity control signal POL1. In the logic state, the red latch data RData or the eighth input channel Cm-4 of the seventh input channel Cm-5 supplied from the second switching unit S6b of the sixth data path selector S6. Green latch data RData is supplied to the eighth decoder D8.

The ninth data selector M9 supplies the blue latch data RData of the ninth input channel Cm-3 to the ninth decoder D9 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the blue latch data RData of the third or sixth input channels Cm-9 and Cm-6 supplied from the seventh data path selector S7. ) Is supplied to the ninth decoder D9.

The tenth data selector M10 supplies the red latch data RData of the tenth input channel Cm-2 to the tenth decoder D10 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the red latch data RData or the fifth channel Cm of the fourth input channel Cm-8 supplied from the eighth data path selector S8. The green latch data RData of -7) is supplied to the tenth decoder D10.

The eleventh data selector M11 is the eleventh input channel Cm supplied from the first switch S9a of the ninth data path selector S9 when the first polarity control signal POL1 is in the first logic state. The green latch data RData of -1) or the red latch data RData of the fourth input channel Cm-8 is supplied to the eleventh decoder D11, and the first polarity control signal POL1 is applied to the second logic. In the state, the green latch data RData of the fifth or eleventh input channels Cm-7 and Cm-1 supplied from the second switching unit S9b of the ninth data path selector S9 is decoded. It supplies to (D11).

The twelfth data selector M12 is a twelfth or third input supplied from the first switch S10a of the tenth data path selector S10 when the first polarity control signal POL1 is in a first logic state. When the blue latch data RData of the channels Cm and Cm-9 is supplied to the twelfth decoder D12 and the first polarity control signal POL1 is in the second logic state, the tenth data path selector S10. The blue latch data RData of the sixth or twelfth input channels Cm-6 and Cm supplied from the second switching unit S10b is supplied to the twelfth decoder D12.

The image signal path controller 400 corresponds to the horizontal 1 dot or horizontal 2 dot inversion scheme according to the first and second polarity control signals POL1 and POL2 of the image signal VData supplied from the data converter 200. The first and second image signal path controllers 410 and 420 which control the path of the image signal VData so as to be supplied to the data output unit 144 may be included.

The first image signal path control unit 410 includes first to tenth image signal path selection units s1 to s10.

The first image signal path selector s1 outputs a blue image signal VData from each of the third or twelfth decoders D3 and D12 according to the second polarity control signal POL2. ) And a second switching unit s1b which outputs a blue image signal VData from each of the ninth or third decoders D9 and D3 in accordance with the second polarity control signal POL2. The first switching unit s1a selects and outputs a negative blue image signal VData supplied from the third decoder D3 according to the second polarity control signal POL2 in the first logic state, and outputs the second signal. The blue image signal VData of the positive polarity supplied from the twelfth decoder D12 is selected and output according to the second polarity control signal POL2 in the logic state. The second switching unit s1b selects and outputs the positive blue image signal VData supplied from the ninth decoder D9 according to the second polarity control signal POL2 of the first logic state, and the second logic state. The blue image signal VData of the negative polarity supplied from the third decoder D3 is selected and output in accordance with the second polarity control signal POL2.

The second image signal path selector s2 is configured to display the red image signal VData from the fourth decoder D4 or the green image signal VData from the eleventh decoder D11 according to the second polarity control signal POL2. The red image signal VData from the tenth decoder D10 or the red image signal VData from the fourth decoder D4 in accordance with the first switching unit s2a and the second polarity control signal POL2. It is configured to include a second switching unit (s2b) for outputting. The first switching unit s2a selects and outputs a positive red image signal VData supplied from the fourth decoder D4 according to the second polarity control signal POL2 of the first logic state and outputs the second logic state. The green image signal VData supplied from the eleventh decoder D11 is selected and output in accordance with the second polarity control signal POL2. The second switching unit s2b selects and outputs the red image signal VData supplied from the tenth decoder D10 according to the second polarity control signal POL2 in the first logic state, and outputs the second logic state in the second logic state. The red image signal VData from the fourth decoder D4 is selected and output in accordance with the two polarity control signals POL2.

The third image signal path selection unit s3 selects and outputs the negative green image signal VData supplied from the eleventh decoder D11 according to the second polarity control signal POL2 in the first logic state. In response to the second polarity control signal POL2 in the second logic state, the negative red image signal VData supplied from the tenth decoder D10 is selected and output.

The fourth image signal path selector s4 selects and outputs a positive blue image signal VData supplied from the twelfth decoder D12 in accordance with the second polarity control signal POL2 in the first logic state. The blue image signal VData of the positive polarity supplied from the ninth decoder D9 is selected and output in accordance with the second polarity control signal POL2 in the logic state.

The fifth image signal path selector s5 is the red image signal VData from the seventh decoder D7 or the green image signal VData from the eighth decoder D8 in accordance with the second polarity control signal POL2. The green image signal VData from the eighth decoder D8 or the red image signal VData from the seventh decoder D7 according to the first switching unit s5a and the second polarity control signal POL2. It is configured to include a second switching unit (s5b) for outputting. The first switching unit s5a selects and outputs the negative red image signal VData supplied from the seventh decoder D7 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive green image signal VData supplied from the eighth decoder D8 is selected and output. The second switching unit s5b selects and outputs the positive green image signal VData supplied from the eighth decoder D8 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic state. According to the second polarity control signal POL2, the negative red image signal VData supplied from the seventh decoder D7 is selected and output.

The sixth image signal path selector s6 is provided with the red image signal VData from the eighth decoder D8 or the red image signal VData from the seventh decoder D7 in accordance with the second polarity control signal POL2. The red image signal VData from the seventh decoder D7 or the green image signal VData from the eighth decoder D8 in accordance with the first switching unit s6a and the second polarity control signal POL2. It is configured to include a second switching unit (s6b) for outputting. The first switching unit s6a selects and outputs the positive green image signal VData supplied from the eighth decoder D8 according to the second polarity control signal POL2 of the first logic state, and the second logic state. According to the second polarity control signal POL2, the negative red image signal VData supplied from the seventh decoder D7 is selected and output. The second switching unit s6b selects and outputs a negative red image signal VData supplied from the seventh decoder D7 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive green image signal VData supplied from the eighth decoder D8 is selected and output.

The seventh image signal path selector s7 selects and outputs a negative blue image signal VData supplied from the third decoder D3 according to the second polarity control signal POL2 in the first logic state. The blue image signal VData of the negative polarity supplied from the sixth decoder D6 is selected and output according to the second polarity control signal POL2 in the second logic state.

The eighth image signal path selector s8 selects and outputs a positive red image signal VData supplied from the fourth decoder D4 according to the second polarity control signal POL2 in the first logic state. The positive green image signal VData supplied to the fifth decoder D5 is selected and output according to the second polarity control signal POL2 in the two logic states.

The ninth image signal path selector s9 is the green image signal VData from the eleventh decoder D11 or the red image signal VData from the fourth decoder D4 in accordance with the second polarity control signal POL2. The green image signal VData from the fifth decoder D5 or the green image signal VData from the eleventh decoder D11 according to the first switching unit s9a and the second polarity control signal POL2. It is configured to include a second switching unit (s9b) for outputting. The first switching unit s9a selects and outputs the negative green image signal VData supplied from the eleventh decoder D11 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive red image signal VData supplied from the fourth decoder D4 is selected and output. The second switching unit s9b selects and outputs the positive green image signal VData supplied from the fifth decoder D5 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic state. The negative polarity green image signal VData supplied from the eleventh decoder D11 is selected and output according to the second polarity control signal POL2.

The tenth image signal path selector s10 may be a blue image signal VData from the twelfth decoder D12 or a blue image signal VData from the third decoder D3 according to the second polarity control signal POL2. The blue image signal VData from the sixth decoder D6 or the blue image signal VData from the twelfth decoder D12 according to the first switching unit s10a and the second polarity control signal POL2. It is configured to include a second switching unit (s10b) for outputting. The first switching unit s10a selects and outputs a positive blue image signal VData supplied from the twelfth decoder D12 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic state. According to the second polarity control signal POL2, the negative blue image signal VData from the third decoder D3 is selected and output. The second switching unit s10b selects and outputs the negative blue image signal VData supplied from the sixth decoder D6 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive blue image signal VData supplied from the twelfth decoder D12 is selected and output.

The second image signal path control section 420 includes first to twelfth image signal selection sections m1 to m12.

The first image signal selector m1 outputs a positive red image signal VData supplied from the first decoder D1 when the first polarity control signal POL1 is in the first logic state. The output buffer unit outputs the negative red image signal VData supplied to the first buffer line Im-11 and supplied from the second decoder D2 when the first polarity control signal POL1 is in the second logic state. It is supplied to the first buffer line Im-11 of 144. At this time, the positive or negative red image signal VData supplied to the first buffer line Im-11 is data supplied to the first input channel Cm-11.

The second image signal selector m2 outputs the negative green image signal VData supplied from the second decoder D2 when the first polarity control signal POL1 is in the first logic state. An output buffer unit for supplying the positive green image signal VData supplied to the second buffer line Im-10 of the second buffer line and supplied from the first decoder D1 when the first polarity control signal POL1 is in the second logic state. The second buffer line Im-10 is supplied to the second buffer line Im-10. In this case, the positive or negative green image signal VData supplied to the second buffer line Im-10 is data supplied to the second input channel Cm-10.

When the first polarity control signal POL1 is in the first logic state, the third image signal selector m3 is configured to perform a third decoder D3 through the first switching unit s1a of the first image signal path selector s1. The blue color image signal VData supplied from the negative polarity or the blue color image signal VData supplied from the twelfth decoder D12 is supplied to the third buffer line Im-9 of the output buffer unit 144. When the first polarity control signal POL1 is in the second logic state, the positive blue image supplied from the ninth decoder D9 through the second switching unit s1b of the first image signal path selection unit s1. The blue image signal VData of the negative polarity supplied from the signal VData or the third decoder D3 is supplied to the third buffer line Im-9 of the output buffer unit 144. At this time, the positive or negative blue image signal VData supplied to the third buffer line Im-9 is data supplied to the third input channel Cm-9.

The fourth image signal selector m4 is configured to pass through the fourth decoder D4 through the first switching unit s2a of the second image signal path selector s2 when the first polarity control signal POL1 is in the first logic state. ) Is supplied to the fourth buffer line Im-8 of the output buffer unit 144 by the positive red image signal VData supplied from the negative polarity or the red image signal VData supplied from the eleventh decoder D11. When the first polarity control signal POL1 is in the second logic state, the negative polarity supplied from the tenth decoder D10 through the second switching unit s2b of the second image signal path selection unit s2 is used. The positive red image signal VData supplied from the red image signal VData or the fourth decoder D4 is supplied to the fourth buffer line Im-8 of the output buffer unit 144. In this case, the positive or negative red image signal VData supplied to the fourth buffer line Im-8 is data supplied to the fourth input channel Cm-8.

The fifth image signal selector m5 may output the positive green image signal VData supplied from the fifth decoder D5 when the first polarity control signal POL1 is in the first logic state. Supplied to the fifth buffer line Im-7 and supplied from the eleventh decoder D11 through the third image signal path selector s3 when the first polarity control signal POL1 is in the second logic state. The polarity green image signal VData or the negative red image signal VData supplied from the tenth decoder D10 is supplied to the fifth buffer line Im-7 of the output buffer unit 144. At this time, the positive or negative green image signal VData supplied to the fifth buffer line Im-7 is data supplied to the fifth input channel Cm-7.

The sixth image signal selector m6 outputs the negative blue image signal VData supplied from the sixth decoder D6 when the first polarity control signal POL1 is in the first logic state. Supplied to the sixth buffer line Im-6 and supplied from the twelfth decoder D12 through the fourth image signal path selection unit s4 when the first polarity control signal POL1 is in the second logic state. The positive blue image signal VData or the positive blue image signal VData supplied from the ninth decoder D9 is supplied to the sixth buffer line Im-6 of the output buffer unit 144. At this time, the positive or negative blue image signal VData supplied to the sixth buffer line Im-6 is data supplied to the sixth input channel Cm-6.

When the first polarity control signal POL1 is in the first logic state, the seventh image signal selector m7 may operate the seventh decoder D7 through the first switching unit s5a of the fifth image signal path selector s5. ) Is supplied to the seventh buffer line Im-5 of the output buffer unit 144 by the negative red image signal VData supplied from the negative polarity or the red image signal VData supplied from the eighth decoder D8. And the red image of the positive polarity supplied from the eighth decoder D8 through the second switching unit s5b of the fifth image signal path selection unit s5 when the first polarity control signal POL1 is in the second logic state. The signal VData or the negative red image signal VData supplied from the seventh decoder D7 is supplied to the seventh buffer line Im-5 of the output buffer unit 144. At this time, the positive or negative red image signal VData supplied to the seventh buffer line Im-5 is data supplied to the seventh input channel Cm-5.

When the first polarity control signal POL1 is in the first logic state, the eighth image signal selector m8 may include the eighth decoder D8 through the first switching unit s6a of the sixth image signal path selector s6. The green image signal VData supplied from the positive polarity or the green image signal VData supplied from the seventh decoder D7 is supplied to the eighth buffer line Im-4 of the output buffer unit 144. When the first polarity control signal POL1 is in the second logic state, the negative green color supplied from the seventh decoder D7 through the second switching unit s6b of the sixth image signal path selection unit s6 The positive green image signal VData supplied from the image signal VData or the eighth decoder D8 is supplied to the eighth buffer line Im-4 of the output buffer unit 144. At this time, the positive or negative green image signal VData supplied to the eighth buffer line Im-4 is data supplied to the eighth input channel Cm-4.

The ninth image signal selector m9 outputs the positive blue image signal VData supplied from the ninth decoder D9 when the first polarity control signal POL1 is in the first logic state. Supplied to the ninth buffer line Im-3 and supplied from the third decoder D3 through the seventh image signal path selector s7 when the first polarity control signal POL1 is in the second logic state. The blue image signal VData having the polarity or the blue image signal VData having the negative polarity supplied from the sixth decoder D6 is supplied to the ninth buffer line Im-3 of the output buffer unit 144. At this time, the positive or negative blue image signal VData supplied to the ninth buffer line Im-3 is data supplied to the ninth input channel Cm-3.

The tenth image signal selector m10 may output the red image signal VData supplied from the tenth decoder D10 when the first polarity control signal POL1 is in the first logic state, to the tenth image of the output buffer unit 144. The positive red color supplied to the buffer line Im-2 and supplied from the fourth decoder D4 through the eighth image signal path selector s8 when the first polarity control signal POL1 is in the second logic state. The positive red image signal VData supplied from the image signal VData or the fifth decoder D5 is supplied to the tenth buffer line Im-2 of the output buffer unit 144. At this time, the positive or negative red image signal VData supplied to the tenth buffer line Im-2 is data supplied to the tenth input channel Cm-2.

When the first polarity control signal POL1 is in the first logic state, the eleventh image signal selector m11 receives the eleventh decoder D11 through the first switching unit s9a of the ninth image signal path selector s9. Negative green image signal VData supplied from the PDP or the positive green image signal VData supplied from the fourth decoder D4 is transferred to the eleventh buffer line Im-1 of the output buffer unit 144. And the positive green color supplied from the fifth decoder D5 through the second switching unit s9b of the ninth image signal path selection unit s9 when the first polarity control signal POL1 is in the second logic state. The negative green image signal VData supplied from the image signal VData or the eleventh decoder D11 is supplied to the eleventh buffer line Im-1 of the output buffer unit 144. At this time, the positive or negative green image signal VData supplied to the eleventh buffer line Im-1 is data supplied to the eleventh input channel Cm-1.

The twelfth image signal selector m12 uses the first switch unit s10a of the tenth image signal path selector s10 when the first polarity control signal POL1 is in a first logic state, to allow the twelfth decoder D12 to operate. ) Is supplied to the twelfth buffer line Im of the output buffer unit 144 by supplying the positive blue image signal VData supplied from the PDP or the negative blue image signal VData supplied from the third decoder D3, When the first polarity control signal POL1 is in the second logic state, the negative blue image signal supplied from the sixth decoder D6 through the second switching unit s10b of the tenth image signal path selection unit s10 The positive blue image signal VData supplied from (VData) or the twelfth decoder D12 is supplied to the twelfth buffer line Im of the output buffer unit 144. At this time, the positive or negative blue image signal VData supplied to the twelfth buffer line Im is data supplied to the twelfth input channel Cm.

As described above, the digital-to-analog converter 142 uses the data path controller 300 and the image signal path controller 400 according to the logic states of the first and second polarity control signals POL1 and POL2. The latch data RData is converted into an image signal VData to be supplied to the output buffer unit 144 so as to have a polar pattern of a horizontal 1 dot or horizontal 2 dot inversion scheme by controlling the path of?.

For example, when the first and second polarity control signals POL1 and POL2 both have a first logic state, the digital-to-analog converter 142 of the image signal VData may be configured as shown in FIG. 5A. The polarity pattern is converted into a horizontal two-dot inversion method and supplied to the output buffer unit 144. At this time, the polarity pattern of the horizontal two-dot inversion type has the polarity reversed in units of two input channels in the horizontal direction except for the first input channel Cm-11, and thus "+-++-++- It has the form + ".

In addition, when the first polarity control signal POL1 has a second logic state and the second polarity control signal POL2 has a first logic state, the digital-to-analog converter 142 is illustrated in FIG. 5B. As described above, the polarity pattern of the image signal VData is converted into an inverted horizontal two-dot inversion scheme and supplied to the output buffer unit 144. At this time, the polarized pattern of the inverted horizontal two-dot inversion type has the polarity inverted in units of two input channels in the horizontal direction except for the first input channel Cm-11, and thus the "-++-++- ++-"

In addition, when the first polarity control signal POL1 has a first logic state and the second polarity control signal POL2 has a second logic state, the digital-to-analog converter 142 is illustrated in FIG. 5C. As described above, the polarity pattern of the image signal VData is converted into the horizontal one-dot inversion method and supplied to the output buffer unit 144. At this time, the polarity pattern of the horizontal 1 dot inversion type has a shape such as "+-+-+-+-+-+-" because the polarity is inverted in each input channel unit in the horizontal direction.

In addition, when the first and second polarity control signals POL1 and POL2 have a second logic state, the digital-to-analog converter 142 may have a polarity pattern of the image signal VData as shown in FIG. 5D. Is converted into an inverted horizontal 1 dot inversion scheme and supplied to the output buffer unit 144. At this time, the polarized pattern of the inverted horizontal 1 dot inversion method has a shape such as "-+-+-+-+-+-+" because the polarity is inverted for each input channel unit in the horizontal direction.

As a result, the digital-to-analog converter 142 performs a path for each of the data and image signals so as to correspond to the horizontal two-dot or horizontal one-dot inversion scheme according to the logic states of the first and second polarity control signals POL1 and POL2. By controlling, the number of decoders is configured equal to the number of output channels.

The output buffer unit 144 buffers the image signal VData of each channel supplied from the digital-to-analog converter 142 and outputs the result to the outside through the final output channel. At this time, the output buffer unit 144 amplifies and outputs the image signal VData in consideration of an external load.

As described above, the data driving apparatus 100 according to the first exemplary embodiment of the present invention separates the blue upper gray voltages PBV_x and NBV_x from the red and green upper gray voltages PRGV_x and NRGV_x to control the gray levels. The color temperature may be kept constant, and the size of the gray voltage generator 120 may be reduced. Specifically, the data driver 100 according to the first embodiment of the present invention sets the positive gray upper gray voltage PBV_x higher than the positive red / green gray gray voltage PRGV_x. As shown in FIG. 6, the upper gray voltage NBV_x for the negative blue color is set to be lower than the upper gray voltage NRGV_x for the red / green polarity, and as shown in the curve B of the color temperature curve according to the gray level, as shown in FIG. 6. The color temperature of the gradation region can be compensated. In Fig. 6, curve A shows a color temperature curve according to a conventional gray scale using the same gray voltage for each of the data signals of red, green, and blue, respectively.

Furthermore, the present invention can reduce the size of the data driver 100 by configuring the number of decoders of the digital-to-analog converter 142 equal to the number of output channels of the data driver 100.

7 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 7, a liquid crystal display according to an exemplary embodiment of the present invention includes an image display unit having a plurality of pixel cells P formed in each region defined by a plurality of data lines DL and gate lines GL. (2); A gate driver 4 which drives the gate line GL of the image display unit 2; A data driver 6 for supplying an image signal to the data line DL of the image display unit 2; A timing controller 8 for supplying data signals R, G, and B to the data driver 6 and controlling the data driver 6 and the gate driver 4; And a reference gamma voltage generator 10 generating a plurality of reference gray voltages GMA1 to GMAj and supplying them to the data driver 8.

The image display unit 2 includes a spacer (not shown) for maintaining a constant cell gap between the upper substrate (not shown) and the lower substrate (not shown) bonded to each other; And a liquid crystal layer (not shown) formed in the liquid crystal space provided by the spacer.

The upper substrate includes at least three color filters including red, green, and blue; A black matrix for separating pixel filters and defining pixel cells; And a common electrode to which the common voltage Vcom is supplied. Here, the common electrode may be formed on the lower substrate according to the mode of the liquid crystal.

The lower substrate may include a thin film transistor formed in each pixel cell P region defined by the data lines DL and the gate lines GL; And a pixel electrode connected to the thin film transistor. The thin film transistor switches the image signal supplied from the data line DL to the pixel electrode in response to the gate-on voltage supplied from the gate line GL.

The timing controller 8 arranges the image data Data from the outside and supplies them to the data driver 6. In addition, the timing controller 8 uses a gate using at least one of an external synchronization signal, for example, a data enable signal DE for notifying a valid section of data and a dot clock DCLK for determining a transmission frequency of data. The gate control signal GCS controlling the driver 4 and the data control signal DCCS controlling the data driver 6 are generated. In this case, the timing controller 8 may further generate the gate and data control signals GCS and DCS by using at least one of an external horizontal synchronization signal Hsync and a vertical synchronization signal Vsync. The data control signal DCS includes a source output signal SOE for controlling the data output period of the data driver 6, a source start pulse SSP for instructing the start of data sampling, and a source shift clock for controlling the sampling timing of data. (SSC) and a polarity control signal POL for controlling the voltage polarity of the data. The gate control signal GCS is an output of the gate driver 4, that is, a gate output signal GOE for controlling the output of the gate-on voltage, and a gate start pulse GSP for instructing the driving of the gate driver 4. And a gate shift clock GSC that specifies a period of the gate on voltage.

The gate driver 4 generates a gate-on voltage according to the gate control signal GCS from the timing controller 8 and sequentially supplies the gate-on voltage to the gate lines GL. Accordingly, the gate lines GL of the image display unit 2 are sequentially driven by the gate-on voltage from the gate driver 4. Meanwhile, the gate driver 4 may be formed on a substrate on which the image display unit 2 is formed at the same time as the manufacturing process of the thin film transistor and connected to the gate line GL.

The reference gamma voltage generator 10 generates a plurality of reference gamma voltages GMA1 to GMAj having different voltage levels by using the divided resistance series connected in series and supplies them to the data driver 8.

The data driver 6 includes at least one data driver. Each of the data driving devices has the same configuration as the data driving device 100 according to the exemplary embodiment of the present invention illustrated in FIGS. 2 to 6. Accordingly, the description of each data driver of the data driver 6 will be replaced with the description of the data driver 100 according to the embodiment of the present invention.

Meanwhile, the first polarity control signal POL1 supplied to each data driver of the data driver 6 is the same as the polarity control signal included in the data control signal DCS generated by the timing controller 8. The polarity control signal POL2 may be fixed to the first logic state or the second logic state according to the characteristics of the image display unit 2. Of course, the first and second polarity control signals POL1 and POL2 supplied to each data driving apparatus 100 of the data driver 6 may vary according to the characteristics of the image data or the image display unit 2. Can be generated).

In addition, a plurality of reference gamma voltages GMA1 to GMAj are provided from the reference gamma voltage generator 10 to the gamma buffer unit 125 of the data driving apparatus 100 shown in FIGS. 2 to 6. Is supplied.

As described above, the liquid crystal display according to the exemplary embodiment of the present invention includes the data driver 100 capable of individually controlling the red / green gray voltage and the blue gray voltage separately configured to the image display unit 2. A constant color temperature may be realized in all areas of the displayed black gray to white gray.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention is configured in the digital-to-analog converter 142 so that the number of decoders for converting digital data into image signals is the same as the number of output channels of the data driver 100. By reducing the size of the data driver, it is easier to cope with the increase in size.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a graph showing color temperature according to a conventional gradation;

2 is a block diagram schematically showing a data driving apparatus according to a first embodiment of the present invention;

3 is a circuit diagram schematically illustrating a gray scale generator of a data driving apparatus according to the exemplary embodiment shown in FIG. 2;

4 is a block diagram schematically illustrating a digital-to-analog converter shown in FIG. 2;

5A is a diagram illustrating a path of data and an image signal corresponding to a horizontal two dot inversion scheme according to first and second polarity control signals according to an embodiment of the present invention;

FIG. 5B is a diagram illustrating data and image signal paths corresponding to an inverted horizontal two-dot inversion scheme according to first and second polarity control signals according to an embodiment of the present disclosure; FIG.

FIG. 5C is a diagram illustrating a path of data and image signals corresponding to a horizontal one dot inversion scheme according to first and second polarity control signals according to an embodiment of the present disclosure; FIG.

5D is a diagram illustrating a path of data and an image signal corresponding to an inverted horizontal 1 dot inversion scheme according to the first and second polarity control signals according to an embodiment of the present invention;

6 is a graph showing a color temperature according to gray scale in a data driver and a liquid crystal display according to an exemplary embodiment of the present invention;

7 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Claims (15)

A digital processor configured to latch input red, green, and blue data; In accordance with the option signal supplied from the digital processing unit, a plurality of reference gamma voltages and blue and gray voltages of red and green colors and red and green gray voltages using the first and second power sources are used. A gradation voltage generation unit generating the gradations; And The red and green latch data supplied from the digital processor are converted into red and green image signals by using the positive and negative red / green gradation voltages and the positive and negative tricolor common gradation voltages. At the same time, the analog processing unit converts the blue latch data supplied from the digital processing unit into a blue image signal using the positive and negative blue gradation voltages and the positive and negative tricolor common gradation voltages. Data drive device comprising a. The method of claim 1, Each of the positive gray gray voltages has a higher voltage level than each of the positive red / green gray voltages. Each of the negative gray gray voltages has a lower voltage level than each of the negative red / green gray voltages. The method of claim 2, The gray gradation voltages are i to h (where h is a natural number less than i) of the total i gradations corresponding to the number of bits of the data, and / or v (where v is a natural number less than h). To zeroth gray voltage, The red / green gradation voltages are i th to h th gradation voltages and / or v th to 0 th gradation voltages among the i th gradation numbers, The three color common gradation voltages may be a 0th to h-1 gradation voltage or a v + 1 to i gradation voltage or a v + 1 to h-1 gradation voltage among the total i gradation numbers. . The method of claim 3, wherein The gray voltage generator; A first voltage divider resistor for generating the positive and negative blue i-h gray voltages and the positive and negative tri-color common h-1 to 0 gray voltages; A second voltage divider resistor for generating the positive red / green i-h gray voltage or the positive blue i-h gray voltage; And And a third voltage divider resistor string for generating the negative red / green i-th to h-th gray voltages or the positive blue i-th to h-th gray voltages. The method of claim 4, wherein The plurality of first voltage divider resistors; A first region for generating the i-th to h-gradation voltages for the blue positive polarity; A first common region for generating the positive tricolor common h-1 to 0 gray voltages; A second common region for generating the negative tricolor common h-1 to 0 gray voltages; And And a second area for generating the negative blue first to h gray voltages. The method of claim 5, wherein The second partial pressure resistance heat is, The i-th to h-gradation voltages for the positive red / green color generated using a plurality of second voltage divider resistors connected in series so as to be separated from the first voltage divider resistor string; The positive blue i-th to h-th gray voltages generated by the resistors in the first region of the first divided resistor string and the red to green i-h gray voltages of the positive red / green color according to the option signal of the digital processor And a first to n-th multiplexer for selectively outputting the data driving apparatus. The method of claim 6, The i-gradation external voltage corresponding to the i-th gray voltage is supplied from the outside to the divided node for generating the positive red / green i-th gray voltage among the divided voltage nodes of the second divided resistance row, The i-gradation external voltage corresponding to the i-th gray voltage is supplied from the outside to the divided node which generates the negative red / green i-th gray voltage among the divided voltage nodes of the third divided resistor row. Device. The method of claim 5, wherein The third partial pressure resistance heat, I-h gray voltages for red / green for the negative polarity generated using a plurality of third voltage divider resistors connected in series to be separated from the first voltage divider resistor string; Option signals of the digital processing unit may be configured to convert the negative blue i-th to h-th gray voltages generated by the resistors in the second region of the first divided resistor row and the negative i / h gray voltages of the red / green of the negative polarity. And a first to m-th multiplexer selectively outputting the data driver. The method of claim 3, wherein The analog processing unit; The latch data is converted into an image signal having a polarity corresponding to the first and second polarity control signals by using the blue and gray gradation voltages, the red and green gradation voltages, and the three-color common gradation voltages. A digital analog converter; And And an output buffer unit for buffering the image signal supplied from the digital analog converter. The method of claim 9, The digital-to-analog converter includes a plurality of data conversion blocks having 12 channels repeatedly arranged in the order of red, green, and blue, each data conversion block comprising: a plurality of data conversion blocks; A data converter converting red, green, and blue latch data into red, green, and blue image signals using the positive and negative blue gray voltages, the red / green gray voltages, and the three-color common gray voltages; A data path controller configured to control a path of each of the red, green, and blue latch data supplied from the digital processor to the data converter through the first through twelfth input channels according to the first and second polarity control signals; And And an image signal path control unit configured to control paths of the red, green, and blue image signals supplied from the data converter to the output buffer unit according to the first and second polarity control signals. Drive system. The method of claim 10, The data converter; A first to twelfth decoder including a positive decoder for converting the latch data into a positive image signal, and a negative decoder for converting the latch data into a negative image signal; And the first to twelfth decoders are arranged to be repeated in the order of the positive polarity, the negative polarity, the negative polarity, and the positive polarity. The method of claim 11, Each of the first, fourth, fifth and eighth decoders is supplied with the positive red / green gradation voltages and the positive tricolor common gradation voltages supplied from the gradation voltage generation unit. Each of the second, seventh, tenth, and eleventh decoders is supplied with the negative red / green gray voltages and the negative tricolor common gray voltages from the gray voltage generator. Each of the ninth and twelfth decoders is supplied with the gray blue voltages of the positive polarity and the three common color gradation voltages of the positive polarity from the gray voltage generator. And each of the third and sixth decoders is supplied with the negative gray gray voltages and the negative three color common gray voltages from the gray voltage generator. The method of claim 12, The data path control unit; A first data path controller configured to control a path of the latch data supplied through the second to twelfth input channels according to the second polarity control signal; And The first, second, fifth, sixth, ninth, and tenth input channels and the path of the latch data supplied through the first data path controller are controlled according to the first polarity control signal. And a second data path control unit for supplying each to the twelfth decoder. The method of claim 13, The image signal path control section; A first image signal path control unit which controls the path of the image signal supplied from the second to twelfth decoders according to the second polarity control signal; And The image signals supplied from the first, second, fifth, sixth, ninth, and tenth decoders and the paths of the image signals supplied through the first image signal path control unit according to the first polarity control signal. And a second image signal path controller for controlling and supplying the buffers to the respective buffer units. An image display unit having a plurality of pixel cells formed for each region defined by a plurality of data lines and gate lines; A gate driver for driving a gate line of the image display unit; A data driver for supplying an image signal to a data line of the image display unit; A timing controller which supplies a data signal to the data driver and controls the data driver and the gate driver; And A reference gamma voltage generator configured to generate a plurality of reference gray voltages and supply them to the data driver; The data driver of claim 1, wherein the data driver comprises the data driver of claim 1.

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