KR101407296B1 - Data driving device and liquid crystal display device using the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving apparatus capable of compensating for a color temperature according to a gray scale and a liquid crystal display using the same.

A data driving apparatus according to the present invention includes: a digital processing unit for latching input red, green, and blue data; (I is a total number of gradations corresponding to the number of bits of the data) using the plurality of reference gamma voltages, the first and second voltages, and the positive polarity and the negative polarity gradation voltage for red / A gradation voltage generator for separately generating a positive polarity and a negative polarity gradation voltage; And converting the red and green latch data supplied from the digital processing unit into red and green image signals of positive or negative polarity respectively using the i positive and negative polarity gradation voltages for the i and And an analog processor for converting the blue latch data supplied from the digital processor into a positive or negative blue image signal using the i positive and negative polarity gradation voltages for blue, .

A gradation voltage, an image signal, a decoder, a color temperature,

Description

Technical Field [0001] The present invention relates to a data driving apparatus and a liquid crystal display using the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving device and a liquid crystal display device using the same, and more particularly, to a data driving device capable of compensating a color temperature according to a gray scale and a liquid crystal display using the same.

In general, a liquid crystal display displays a desired image by applying an electric field to a liquid crystal material having an anisotropic permittivity formed between two substrates, and adjusting the light transmittance by adjusting the intensity of the electric field.

Such a general liquid crystal display device displays gradations according to the light transmittances of red, green and blue dots (Dot) according to respective data signals of red (R), green (G) and blue (B) At this time, the red, green, and blue data signals use the same gray scale voltage. Accordingly, although the electro-optical characteristics of red, green, and blue dots are clearly different from each other, the use of the same gradation voltage causes a problem in that the color temperature according to the gradation is changed. That is, the color temperature is determined by the blending ratio of the luminance of each of the red, green, and blue dots constituting the pixel. Since the data signals of red, green, and blue can not be individually controlled when the gradation is increased or decreased, The color temperature becomes uneven.

In order to solve the above problems, the present invention provides a data driving apparatus capable of compensating a color temperature according to a gray scale and a liquid crystal display using the same.

According to an aspect of the present invention, there is provided a data driving apparatus including a digital processing unit for latching input red, green, and blue data; (I is a total number of gradations corresponding to the number of bits of the data) using the plurality of reference gamma voltages, the first and second voltages, and the positive polarity and the negative polarity gradation voltage for red / A gradation voltage generator for separately generating a positive polarity and a negative polarity gradation voltage; And converting the red and green latch data supplied from the digital processing unit into red and green image signals of positive or negative polarity respectively using the i positive and negative polarity gradation voltages for the i and And an analog processor for converting the blue latch data supplied from the digital processor into a positive or negative blue image signal using the i positive and negative polarity gradation voltages for blue, .

Wherein the gradation voltage generating unit includes a first voltage generating unit for generating the i positive blue gradation voltages for blue and the i negative blue gradation voltages for blue using a plurality of first voltage dividing resistors connected in series between the first voltage and the second voltage, Partial pressure resistance heat; And a second voltage divider for generating the i positive red / green positive gray scale voltages and the i red / green negative gray scale voltages using a plurality of second voltage dividing resistors connected in series between the first and second voltages, And a partial pressure resistance column.

And the resistance value of each of the second voltage-dividing resistors has a larger resistance value than the corresponding first voltage-dividing resistor.

Wherein the data driving apparatus further comprises a gamma buffer unit for buffering each of the plurality of reference gamma voltages supplied from the outside and outputting a plurality of buffered reference gamma voltages to the outside, Each of the plurality of buffered reference gamma voltages is supplied to any one of the nodes among the plurality of first voltage dividing resistors and is supplied to any one of the nodes among the plurality of second voltage dividing resistors .

Each of the i blue positive polarity gradation voltages and the i blue positive polarity gradation voltages is generated at a node between the plurality of first voltage dividing resistors, and the i red / green positive polarity gradation voltages and i Each of the red / green negative polarity gradation voltages is generated at a node between the plurality of second voltage dividing resistors. Wherein the highest gradation voltage among the plurality of blue positive polarity gradation voltages corresponds to the highest reference gamma voltage among the plurality of reference gamma voltages, and the lowest gradation voltage among the plurality of blue negative gradation voltages corresponds to one of the plurality of reference gamma voltages Corresponds to the lowest reference gamma voltage.

The data driving apparatus according to the present invention separately configures the first and second voltage dividing resistor columns for generating the red / green gradation voltage and the blue voltage gradation voltage, . Furthermore, the present invention can reduce the size of the data driver by configuring the number of decoders of the digital-analog converter to be equal to the number of output channels of the data driver.

Further, the liquid crystal display device according to the present invention includes the data driving device capable of individually controlling the individually configured red / green gradation voltages and blue gradation voltages, so that the entire region of the black gradation to the white gradation A constant color temperature can be realized. In addition, the present invention can reduce the size of the data driving apparatus by configuring the digital-analog converting unit to have the same number of decoders for converting digital data into image signals as the number of output channels of the data driving apparatus, have.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1 is a block diagram schematically showing a data driving apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a data driving apparatus according to an embodiment of the present invention includes a control block 110 for relaying data signals R, G, and B supplied from the outside and a data control signal DCS; Using the buffered plurality of reference gamma voltages (GMAj) supplied from the outside i (stage, i is 2 ^N, and, N is the number of bits of the data signal, or less, N is assumed to 8) of the red / green dragon A gradation voltage generator 120 for generating gradation voltages PRG-Vi and NRG-Vi and blue gradation voltages PB-Vi and NB-Vi; A digital processing unit 130 for latching the data signals R, G and B supplied from the control block 110 according to the data control signals EN1, SSC and SOE supplied from the control block 110; (RData) supplied from the digital processing section 120 using the gradation voltages PRG-Vi, NRG-Vi, PB-Vi and NB-Vi is supplied from the control block 110 to the first and second polarities And an analog processing unit 140 for converting the image signal VData having the data polarity corresponding to the control signals POL1 and POL2 and outputting the same.

The control block 110 restores the N-bit data signals R, G, and B supplied from the outside according to the data interface scheme to correspond to the data interface scheme and supplies the data signals to the digital processing unit 120. The control block 110 also receives data including externally supplied source start pulse SSP, source shift clock SSC, source output signal SOE, first and second polarity control signals POL1 and POL2 And controls the digital processing unit 120 and the analog processing unit 130 using the control signal DCS.

2, the gray-scale voltage generating unit 120 is connected between the driving voltage VDD and the base voltage VSS to generate i blue positive-polarity gradation voltages PB-Vi and i- A first voltage dividing resistor row 122 for generating a negative blue gradation voltage NB-Vi for the blue color and a first voltage dividing resistor row 122 connected between the driving voltage VDD and the ground voltage VSS, And a second voltage dividing resistor row 124 for generating a polarity gradation voltage PRG-Vi and i red / green negative gradation voltages NRG-Vi.

The first voltage divider resistor row 122 includes K first voltage dividing resistors R11 through R1K connected in series between a driving voltage VDD and a ground voltage VSS. The first to j-th reference gamma voltages GMA1 to GMAj are supplied in the middle of the first voltage-dividing resistor row 122. [ For example, the first reference gamma voltage GMA1 is supplied to the voltage dividing node (node between R11 and R12) that generates the positive polarity '255' gradation voltage for blue, and the 254th gradation voltage for blue is generated The second reference gamma voltage GMA2 is supplied to the divided node (the node between R12 and R13). Further, the j-th reference gamma voltage GMAj is supplied to the voltage-dividing node (the node between R1K-1 and R1K) for generating the negative polarity '255' gradation voltage for blue, and the negative 254- 1 reference gamma voltage GMAj-1 is supplied to the divided node (a node between R1K-2 and R1K-1). The other reference gamma voltages GMA3 to GMAj-2 except for the first, second, j-1 and j reference gamma voltages GMA1, GMA2, GMAj-1 and GMAj are the electro- Is supplied to each of the optional voltage dividing nodes so as to have an equal interval or a boiling interval to be matched. The voltage-dividing nodes of the first voltage-dividing resistor row 122 to which each of the reference gamma voltages GMAj are supplied may be changed according to at least one of electro-optic characteristics, gamma characteristics, and color temperature characteristics of the liquid crystal.

The first row of voltage dividing resistors 122 has a positive polarity gradation voltage PB-Vi for blue and a negative polarity gradation voltage PB-Vi for blue between the first divided voltage resistors R11 to R1K according to the resistance ratio according to the resistance value, Generates a voltage (NB-Vi) and supplies it to the analog processing unit 140. [

On the other hand, in the first voltage divider resistor row 122, the first and second voltage dividing resistors R11 and R12 of the K first voltage dividing resistors R11 to R1K are omitted . In this case, the highest gradation voltage among the positive gradation voltages for blue PB-Vi corresponds to the highest gamma voltage among the plurality of reference gamma voltages, that is, the first reference gamma voltage, and the negative polarity gradation voltage for blue NB- The lowest gradation voltage among the plurality of reference gamma voltages may correspond to the lowest one of the plurality of reference gamma voltages, that is, the j-th reference gamma voltage.

The second voltage dividing resistor row 124 includes K second voltage dividing resistors R21 to R2K connected in series between a driving voltage VDD and a ground voltage VSS. Here, the resistance value of each of the second voltage-dividing resistors R21 to R2K is set to have a larger resistance value than that of the corresponding first voltage-dividing resistors R11 to R1K, The first to j-th reference gamma voltages GMA1 to GMAj are supplied in the same manner as the 1-divided-pressure resistance column 122, respectively. The second row of voltage-dividing resistors 124 has the positive polarity gradation voltage PRG-Vi for red / green and the negative polarity for red / green for each of the voltage-dividing resistors R21 to R2K according to the resistance ratio according to the resistance value. Generates the gradation voltage NRG-Vi and supplies it to the analog processing unit 130. [

The gradation voltage generator 120 generates i color gradation voltages of relatively higher voltages than i red / green gradation voltages using the first and second voltage dividing resistor rows 122 and 124, respectively Thereby compensating for the color temperature according to the gradation.

The first to jth reference gamma voltages GMA1 to GMAj supplied to the gradation voltage generating unit 120 are buffered by the gamma buffer unit 125 incorporated in the data driving apparatus 100, 100) (for example, a data printed circuit board), and then supplied again. This is to compensate for the deviation of the first to jth reference gamma voltages (GMA1 to GMAj) supplied to each data driving apparatus 100 when a plurality of the data driving apparatuses 100 are used.

The digital processing unit 130 includes a shift register unit 132 and a latch unit 134.

The shift register unit 132 sequentially shifts the first enable signal EN1 corresponding to the source start pulse SSP from the control block 110 according to the source shift clock SSC to generate the sampling signal Sam And supplies the generated sampling signal Sam to the latch unit 134. The shift register unit 132 includes a bi-directional shift register. At this time, the forward carry signal Car / EN2 or the reverse carry signal Car / EN1 generated in the shift register unit 132 is supplied to the source start pulse SSP of another external data driving apparatus through the control block 110 .

The latch unit 134 latches the data signals R, G, and B supplied from the control block 110 according to the sampling signal Sam supplied from the shift register unit 132. The latch unit 134 then supplies the latch data RData to the analog processing unit 140 in accordance with the source output signal SOE. At this time, the latch unit 134 sequentially latches the data signals R, G, and B corresponding to the number of output channels of the data driver 110. That is, the latch unit 134 sequentially latches the data signal R of the first channel to the data signal B of the last channel, and then latches the data signals R, G, B) at the same time.

The analog processor 140 includes a digital-to-analog converter 142 and an output buffer 144.

4, the digital-analog converter 142 includes a plurality of data conversion blocks each having 12 channels, and each data conversion block includes i red / Green, and blue colors using the positive polarity and negative polarity gradation voltages for green (PRG-Vi, NRG-Vi) and i blue positive polarity and negative polarity gradation voltages (PB-Vi, NB-Vi) A data conversion unit 200 for converting each of the latch data RData into red, green, and blue image signals, respectively; Green and blue latches supplied from the first to twelfth input channels Cm-11 to Cm (m is a multiple of 12) to the data converter 200 according to the first and second polarity control signals POL1 and POL2, A data path control unit 300 for controlling paths of data RData; Green and blue image signals VData supplied from the data conversion section 200 to the output buffer section 144 in accordance with the first and second polarity control signals POL1 and POL2, And a path control unit 400.

The data converting unit 200 includes first through twelfth decoders D1 through D12 in which a positive (P) decoder and a negative (N) decoder are arranged so as to correspond to a horizontal two-dot inversion system. The first through twelfth decoders D1 through D12 are repeatedly arranged in order of a positive (P) decoder, a negative (N) decoder, a negative (N) decoder and a positive (P) decoder.

Each of the first, fourth, fifth, and eighth decoders D1, D4, D5, and D8 uses the positive polarity gradation voltage PRG-Vi for red / green supplied from the gradation voltage generator 120, The latch data RData is converted into a positive red or green image signal VData.

Each of the first, second, seventh, tenth and eleventh decoders D2, D7, D10 and D11 is connected to the red / green negative gray-scale voltage NRG-Vi supplied from the gray- And converts the latch data RData into a negative red or green image signal VData.

Each of the ninth and twelfth decoders D9 and D12 uses the blue positive polarity gradation voltage PB-Vi supplied from the gradation voltage generation section 120 to convert the blue latch data RData into a positive blue image signal VData).

Each of the third and sixth decoders D3 and D6 uses the negative polarity gradation voltage for blue NB-Vi supplied from the gradation voltage generator 120 to output the blue latch data RData to the negative polarity blue image signal (VData).

The data path control unit 300 controls the polarities of the image signals based on the first and the second input control signals POL1 and POL2 so as to correspond to the horizontal 1 dot or horizontal 2 dot version scheme, First and second data path control units 310 and 320 for controlling the paths of the red, green and blue latch data RData supplied to the data conversion unit 200 from the scan lines 11 to Cm.

The first data path control unit 310 includes first to tenth data path selection units S1 to S10.

The first data path selection unit S1 selects the first switching path S1 for outputting the blue latch data RData supplied to the third or twelfth input channels Cm-9 and Cm according to the second polarity control signal POL2, And outputs a blue latch data RData supplied to the ninth or third input channels Cm-3 and Cm-9 according to the second polarity control signal POL2. S1b). The first switching unit S1a selects and outputs the blue latch data RData of the third input channel Cm-9 in accordance with the second polarity control signal POL2 of the first logic state, And selects and outputs the blue latch data RData of the twelfth input channel Cm in accordance with the second polarity control signal POL2. The second switching unit S1b selects and outputs the blue latch data RData of the ninth input channel Cm-3 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2.

The second data path selecting unit S2 selects either the red latch data RData or the eleventh input channel Cm-1 supplied to the fourth input channel Cm-8 in accordance with the second polarity control signal POL2 (RData) supplied to the tenth input channel (Cm-2) according to the second polarity control signal (POL2), and a second switching unit S2a for outputting green latch data And a second switching unit S2b for outputting the red latch data RData supplied to the fourth input channel Cm-8. The first switching unit S2a selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2. The second switching unit S2b selects and outputs the red latch data RData of the tenth input channel Cm-2 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2.

The third data path selecting section S3 selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the red latch data RData of the tenth input channel Cm-2 in accordance with the second polarity control signal POL2 in the state.

The fourth data path selection unit S4 selects and outputs the blue latch data RData of the twelfth input channel Cm in accordance with the second polarity control signal POL2 of the first logic state, And selects and outputs the blue latch data RData of the ninth input channel Cm-3 according to the second polarity control signal POL2.

The fifth data path selecting unit S5 selects either the red latch data RData or the eighth input channel Cm-4 supplied to the seventh input channel Cm-5 according to the second polarity control signal POL2 A first switching unit S5a for outputting the green latch data RData to be supplied and a second switching unit S5b for outputting green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2, And a second switching unit S5b for outputting red latch data RData of the input channel Cm-5. The first switching unit S5a selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2 of FIG. The second switching unit S5b selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2.

The sixth data path selection unit S6 selects either the red latch data RData of the eighth input channel Cm-4 or the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2. (RData) of the seventh input channel Cm-5 or the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2; And a second switching unit S6b for outputting the green latch data RData of the green latch data RData. The first switching unit S6a selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2. The second switching unit S6b selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2.

The seventh data path selection unit S7 selects and outputs the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the blue latch data RData of the sixth input channel Cm-6 according to the second polarity control signal POL2 in the state.

The eighth data path selecting unit S8 selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the green latch data RData supplied to the fifth input channel Cm-7 in accordance with the second polarity control signal POL2 in the state.

The ninth data path selecting section S9 selects either the green latch data RData of the eleventh input channel Cm-1 or the red latch data RDmata of the fourth input channel Cm-8 according to the second polarity control signal POL2. (RData) of the fifth input channel Cm-7 or the green latch data RData of the fifth input channel Cm-1 according to the second polarity control signal POL2, And a second switching unit S9b for outputting the green latch data RData of the green latch data RData. The first switching unit S9a selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2. The second switching unit S9b selects and outputs the green latch data RData of the fifth input channel Cm-7 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2.

The tenth data path selection unit S10 selects either the blue latch data RData of the twelfth input channel Cm or the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2. And a second switching unit S10b for outputting the blue latch data RData of the sixth input channel Cm-6 or the blue color data RData of the twelfth input channel Cm according to the second polarity control signal POL2. And a second switching unit (S10b) for outputting latch data (RData). The first switching unit S10a selects and outputs the blue latch data RData of the twelfth input channel Cm in accordance with the second polarity control signal POL2 of the first logic state, And selects and outputs the blue latch data RData of the third input channel Cm-9 according to the polarity control signal POL2. The second switching unit S10b selects and outputs the blue latch data RData of the sixth input channel Cm-6 according to the second polarity control signal POL2 of the first logic state, And selects and outputs the blue latch data RData of the twelfth input channel Cm in accordance with the second polarity control signal POL2.

The second data path control unit 320 includes first to twelfth data selection units M1 to M2.

The first data selection unit M1 supplies the red latch data RData of the first input channel Cm-11 to the first decoder D1 when the first polarity control signal POL1 is in the first logic state And supplies the green latch data RData of the second input channel Cm-10 to the first decoder D1 when the first polarity control signal PLO1 is in the second logic state.

The second data selection unit M2 selects the green latch data RData of the second input channel Cm-10 and outputs the green latch data RData to the second decoder D2 when the first polarity control signal POL1 is in the first logic state And supplies the red latch data RData of the first input channel Cm-11 to the second decoder D2 when the first polarity control signal PLO1 is in the second logic state.

The third data selection unit M3 selects either the third or the twelfth data signal SEL1 supplied from the first switching unit S1a of the first data path selection unit S1 when the first polarity control signal POL1 is in the first logic state, The blue latch data RData of the input channels Cm-9 and Cm is supplied to the third decoder D3 and the first data path selection unit S1 To the third decoder D3, the blue latch data RData of the ninth or the third input channel Cm-3 or Cm-9 supplied from the second switching unit S1b of the third switching unit S1b.

The fourth data selection unit M4 may select the fourth input channel Cm supplied from the first switching unit S2a of the second data path selection unit S2 when the first polarity control signal POL1 is in the first logic state Supplies the red latch data RData of the first input channel Cm-1 or the green latch data RData of the eleventh input channel Cm-1 to the fourth decoder D4 and outputs the first polarity control signal POL1 as the second logic The red latch data RData of the tenth input channel Cm-2 supplied from the second switching unit S2b of the second data path selecting unit S2 or the red latch data RData of the fourth input channel Cm- And supplies the red latch data RData to the fourth decoder D4.

The fifth data selecting unit M5 supplies the green latch data RData of the fifth input channel Cm-7 to the fifth decoder D5 when the first polarity control signal POL1 is in the first logic state Green latch data RData of the eleventh input channel Cm-1 supplied from the third data path selecting unit S3 when the first polarity control signal POL1 is in the second logic state, Cm-2) to the fifth decoder (D5).

The sixth data selection unit M6 supplies the blue latch data RData of the sixth input channel Cm-6 to the sixth decoder D6 when the first polarity control signal POL1 is in the first logic state And the blue latch data RData of the twelfth or ninth input channel Cm or Cm-3 supplied from the fourth data path selecting unit S4 when the first polarity control signal POL1 is in the second logic state And supplies it to the sixth decoder D6.

The seventh data selecting unit M7 selects the seventh input channel Cm supplied from the first switching unit S5a of the fifth data path selecting unit S5 when the first polarity control signal POL1 is in the first logic state The green latch data RData of the eighth input channel Cm-4 is supplied to the seventh decoder D7 and the first polarity control signal POL1 is supplied to the second logic The green latch data RData of the eighth input channel Cm-4 supplied from the second switching unit S5b of the fifth data path selecting unit S5 or the green latch data RData of the seventh input channel Cm- And supplies the red latch data RData to the seventh decoder D7.

The eighth data selecting unit M8 selects the eighth input channel Cm supplied from the first switching unit S6a of the sixth data path selecting unit S6 when the first polarity control signal POL1 is in the first logic state 4 to the eighth decoder D8 and supplies the red latch data RData of the seventh input channel Cm-5 to the eighth decoder D8 so that the first polarity control signal POL1 becomes the second logic The red latch data RData of the seventh input channel Cm-5 or the red latch data RData of the eighth input channel Cm-4 supplied from the second switching unit S6b of the sixth data path selecting unit S6, And supplies the green latch data RData to the eighth decoder D8.

The ninth data selecting section M9 supplies the blue latch data RData of the ninth input channel Cm-3 to the ninth decoder D9 when the first polarity control signal POL1 is in the first logic state And the blue latch data of the third or sixth input channels Cm-9 and Cm-6 supplied from the seventh data path selecting unit S7 when the first polarity control signal POL1 is in the second logic state RData) to the ninth decoder D9.

The tenth data selecting unit M10 supplies the red latch data RData of the tenth input channel Cm-2 to the tenth decoder D10 when the first polarity control signal POL1 is in the first logic state The red latch data RData of the fourth input channel Cm-8 supplied from the eighth data path selecting unit S8 or the red latch data RData of the fourth channel Cm-8 supplied from the eighth data path selecting unit S8 when the first polarity control signal POL1 is in the second logic state. -7) to the tenth decoder D10.

The eleventh data selecting unit M11 selects the eleventh input channel Cm supplied from the first switching unit S9a of the ninth data path selecting unit S9 when the first polarity control signal POL1 is in the first logic state The red latch data RData of the first input channel Cm-1 or the red latch data RData of the fourth input channel Cm-8 to the eleventh decoder D11 and the first polarity control signal POL1 is the second logic Green latch data RData of the fifth or eleventh input channel Cm-7 or Cm-1 supplied from the second switching unit S9b of the ninth data path selecting unit S9 is supplied to the eleventh decoder (D11).

The twelfth data selecting section M12 may select the twelfth or third input from the first switching section S10a of the tenth data path selecting section S10 when the first polarity control signal POL1 is in the first logic state The blue latch data RData of the channels Cm and Cm-9 is supplied to the twelfth decoder D12 and the tenth data path selector S10 when the first polarity control signal POL1 is in the second logic state. To the twelfth decoder D12, the blue latch data RData of the sixth or twelfth input channels Cm-6 and Cm supplied from the second switching unit S10b of the sixth switch unit S10b.

The image signal path control unit 400 sets the image signal VData supplied from the data conversion unit 200 to a horizontal 1 dot or a horizontal 2 dot version in accordance with the first and second polarity control signals POL1 and POL2 And first and second image signal path control units (410, 420) for controlling the path of the image signal (VData) so as to be supplied to the data output unit (144).

The first image signal path control unit 410 includes first to tenth image signal path selection units s1 to s10.

The first image signal path selecting section s1 includes a first switching section s1a for outputting a blue image signal VData from each of the third or twelfth decoders D3 and D12 in accordance with the second polarity control signal POL2 And a second switching unit s1b for outputting a blue image signal VData from the ninth or the third decoder D9 or D3 in accordance with the second polarity control signal POL2. The first switching unit s1a selects and outputs the negative blue image signal VData supplied from the third decoder D3 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the positive blue image signal (VData) supplied from the twelfth decoder (D12) in accordance with the second polarity control signal (POL2) in the state. The second switching unit s1b selects and outputs the positive blue image signal VData supplied from the ninth decoder D9 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the negative blue image signal VData supplied from the third decoder D3 in accordance with the second polarity control signal POL2 of FIG.

The second image signal path selecting section s2 selects either the red image signal VData from the fourth decoder D4 or the green image signal VData from the eleventh decoder D11 in accordance with the second polarity control signal POL2, A red image signal VData from the tenth decoder D10 or a red image signal VD2 from the fourth decoder D4 in accordance with the second polarity control signal POL2 And a second switching unit s2b for outputting VData. The first switching unit s2a selects and outputs the positive red image signal VData supplied from the fourth decoder D4 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the green image signal VData supplied from the eleventh decoder D11 in accordance with the second polarity control signal POL2. The second switching unit s2b selects and outputs the red image signal VData supplied from the tenth decoder D10 according to the second polarity control signal POL2 in the first logic state, And selects and outputs the red image signal (VData) from the fourth decoder (D4) according to the bipolarity control signal (POL2).

The third image signal path selecting section s3 selects and outputs the negative green image signal VData supplied from the eleventh decoder D11 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the negative red image signal (VData) supplied from the tenth decoder (D10) in accordance with the second polarity control signal (POL2) in the second logic state.

The fourth image signal path selection unit s4 selects and outputs the positive blue image signal VData supplied from the twelfth decoder D12 in accordance with the second polarity control signal POL2 in the first logic state, And outputs the positive blue image signal VData supplied from the ninth decoder D9 in accordance with the second polarity control signal POL2 in the logic 2 state.

The fifth image signal path selecting section s5 selects either the red image signal VData from the seventh decoder D7 or the green image signal VData from the eighth decoder D8 in accordance with the second polarity control signal POL2, A green image signal VData from the eighth decoder D8 or a red image signal VData from the seventh decoder D7 in accordance with the second polarity control signal POL2, And a second switching unit s5b for outputting the second switching unit s5b. The first switching unit s5a selects and outputs the negative red image signal VData supplied from the seventh decoder D7 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the positive green image signal (VData) supplied from the eighth decoder (D8) in accordance with the second polarity control signal (POL2) in the state. The second switching unit s5b selects and outputs the positive green image signal VData supplied from the eighth decoder D8 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the negative red image signal VData supplied from the seventh decoder D7 in accordance with the second polarity control signal POL2.

The sixth image signal path selecting section s6 selects either the red image signal VData from the eighth decoder D8 or the red image signal VData from the seventh decoder D7 in accordance with the second polarity control signal POL2, And a red image signal VData from the seventh decoder D7 or a green image signal VData from the eighth decoder D8 in accordance with the second polarity control signal POL2, And a second switching unit s6b for outputting the second switching unit s6b. The first switching unit s6a selects and outputs the positive green image signal VData supplied from the eighth decoder D8 in accordance with the second polarity control signal POL2 in the first logic state, Polarity red image signal (VData) supplied from the seventh decoder (D7) in accordance with the second polarity control signal (POL2) in the ON state. The second switching unit s6b selects and outputs the negative red image signal VData supplied from the seventh decoder D7 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the positive green image signal (VData) supplied from the eighth decoder (D8) in accordance with the second polarity control signal (POL2) in the state.

The seventh image signal path selection unit s7 selects and outputs the negative blue image signal VData supplied from the third decoder D3 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the negative blue image signal (VData) supplied from the sixth decoder (D6) in accordance with the second polarity control signal (POL2) in the second logic state.

The eighth image signal path selecting section s8 selects and outputs the positive red image signal VData supplied from the fourth decoder D4 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the positive green image signal (VData) supplied to the fifth decoder (D5) in accordance with the second polarity control signal (POL2) in the 2 logical state.

The ninth image signal path selecting section s9 selects either the green image signal VData from the eleventh decoder D11 or the red image signal VData from the fourth decoder D4 in accordance with the second polarity control signal POL2, A green image signal VData from the fifth decoder D5 or a green image signal VData from the eleventh decoder D11 in accordance with the second polarity control signal POL2, And a second switching unit s9b for outputting the output signal s9b. The first switching unit s9a selects and outputs the negative green image signal VData supplied from the eleventh decoder D11 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the positive red image signal (VData) supplied from the fourth decoder (D4) in accordance with the second polarity control signal (POL2) in the state. The second switching unit s9b selects and outputs the positive green image signal VData supplied from the fifth decoder D5 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the negative green image signal VData supplied from the eleventh decoder D11 in accordance with the second polarity control signal POL2.

The tenth image signal path selection unit s10 selects either the blue image signal VData from the twelfth decoder D12 or the blue image signal VData from the third decoder D3 in accordance with the second polarity control signal POL2, A blue image signal VData from the sixth decoder D6 or a blue image signal VData from the twelfth decoder D12 in accordance with the second polarity control signal POL2; And a second switching unit s10b for outputting the second switching unit s10b. The first switching unit s10a selects and outputs the positive blue image signal VData supplied from the twelfth decoder D12 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the negative blue image signal (VData) from the third decoder (D3) in accordance with the second polarity control signal (POL2). The second switching unit s10b selects and outputs the negative blue image signal VData supplied from the sixth decoder D6 in accordance with the second polarity control signal POL2 in the first logic state, And selects and outputs the positive blue image signal VData supplied from the twelfth decoder D12 according to the second polarity control signal POL2.

The second image signal path control unit 420 includes first to twelfth image signal selectors m1 to m2.

The first image signal selection unit m1 outputs the positive red image signal VData supplied from the first decoder D1 to the output buffer unit 144 when the first polarity control signal POL1 is in the first logic state And supplies the negative red image signal (VData) supplied from the second decoder (D2) to the output buffer unit (Im-11) when the first polarity control signal (PLO1) To the first buffer line (Im-11) of the buffer circuit (144). At this time, the positive or negative red image signal VData supplied to the first buffer line Im-11 is data supplied to the first input channel Cm-11.

The second image signal selection unit m2 outputs the negative green image signal VData supplied from the second decoder D2 to the output buffer unit 144 when the first polarity control signal POL1 is in the first logic state, And supplies the positive green image signal VData supplied from the first decoder D1 to the second buffer line Im-10 of the output buffer unit Im-10 when the first polarity control signal PLO1 is in the second logic state. To the second buffer line (Im-10) of the buffer circuit (144). At this time, the positive or negative green image signal VData supplied to the second buffer line Im-10 is data supplied to the second input channel Cm-10.

The third image signal selection unit m3 selects the third image signal path selection unit s1 through the first switching unit s1a when the first polarity control signal POL1 is in the first logic state, 9) of the output buffer unit 144 to the blue image signal (VData) of the negative polarity supplied from the twelfth decoder (D12) or the positive blue image signal (VData) supplied from the twelfth decoder And the first polarity control signal POL1 is in the second logic state, the first polarity control signal POL1 is supplied from the ninth decoder D9 through the second switching unit s1b of the first image signal path selection unit s1, And supplies the image signal VData or the negative blue image signal VData supplied from the third decoder D3 to the third buffer line Im-9 of the output buffer unit 144. [ At this time, the positive polarity or negative polarity blue image signal VData supplied to the third buffer line Im-9 is data supplied to the third input channel Cm-9.

The fourth image signal selection unit m4 selects the fourth image signal D4 through the first switching unit s2a of the second image signal path selection unit s2 when the first polarity control signal POL1 is in the first logic state, (VData) supplied from the first decoder D11 or the negative red image signal VData supplied from the eleventh decoder D11 to the fourth buffer line Im-8 of the output buffer unit 144 And supplies the negative polarity red (R0) from the tenth decoder (D10) through the second switching unit (s2b) of the second image signal path selection unit s2 when the first polarity control signal POL1 is in the second logic state. And supplies the positive red video signal VData supplied from the image signal VData or the fourth decoder D4 to the fourth buffer line Im-8 of the output buffer unit 144. [ At this time, the positive or negative red image signal VData supplied to the fourth buffer line Im-8 is data supplied to the fourth input channel Cm-8.

The fifth image signal selection unit m5 selects the positive green image signal VData supplied from the fifth decoder D5 when the first polarity control signal POL1 is in the first logic state, To the fifth buffer line Im-7 and supplied from the eleventh decoder D11 through the third image signal path selection unit s3 when the first polarity control signal POL1 is in the second logical state And supplies the negative green image signal VData or the negative red image signal VData supplied from the tenth decoder D10 to the fifth buffer line Im-7 of the output buffer unit 144. [ At this time, the positive or negative green image signal VData supplied to the fifth buffer line Im-7 is data supplied to the fifth input channel Cm-7.

The sixth image signal selection unit m6 outputs the negative blue image signal VData supplied from the sixth decoder D6 to the output buffer unit 144 when the first polarity control signal POL1 is in the first logic state, And supplied from the twelfth decoder D12 through the fourth image signal path selection unit s4 when the first polarity control signal POL1 is in the second logic state The positive blue image signal VData or the positive blue image signal VData supplied from the ninth decoder D9 is supplied to the sixth buffer line Im-6 of the output buffer unit 144. [ The positive or negative blue image signal VData supplied to the sixth buffer line Im-6 is data supplied to the sixth input channel Cm-6.

When the first polarity control signal POL1 is in the first logic state, the seventh image signal selecting section m7 selects the seventh decoder D7 through the first switching section s5a of the fifth image signal path selecting section s5, (VData) supplied from the first decoder D8 or the positive red image signal VData supplied from the eighth decoder D8 to the seventh buffer line Im-5 of the output buffer unit 144 And a positive polarity red image supplied from the eighth decoder D8 through the second switching unit s5b of the fifth image signal path selection unit s5 when the first polarity control signal POL1 is in the second logic state, And supplies the negative red image signal VData supplied from the signal VData or the seventh decoder D7 to the seventh buffer line Im-5 of the output buffer unit 144. [ At this time, the positive or negative red image signal VData supplied to the seventh buffer line Im-5 is data supplied to the seventh input channel Cm-5.

The eighth image signal selecting section m8 selects the eighth decoder D8 through the first switching section s6a of the sixth image signal path selecting section s6 when the first polarity control signal POL1 is in the first logic state, (VData) supplied from the seventh decoder D7 or the negative green image signal VData supplied from the seventh decoder D7 to the eighth buffer line Im-4 of the output buffer unit 144 And the negative polarity green (G) supplied from the seventh decoder (D7) through the second switching unit (s6b) of the sixth image signal path selection unit s6 when the first polarity control signal POL1 is in the second logic state, The green image signal VData of positive polarity supplied from the image signal VData or the eighth decoder D8 is supplied to the eighth buffer line Im-4 of the output buffer unit 144. [ At this time, the positive or negative green image signal VData supplied to the eighth buffer line Im-4 is data supplied to the eighth input channel Cm-4.

The ninth image signal selecting section m9 outputs the positive blue image signal VData supplied from the ninth decoder D9 to the output buffer section 144 when the first polarity control signal POL1 is in the first logic state Supplied from the third decoder D3 through the seventh image signal path selection unit s7 when the first polarity control signal POL1 is in the second logic state, The negative blue image signal VData supplied from the polarity blue image signal VData or the sixth decoder D6 is supplied to the ninth buffer line Im-3 of the output buffer unit 144. [ At this time, the positive polarity or negative polarity blue picture signal VData supplied to the ninth buffer line Im-3 is data supplied to the ninth input channel Cm-3.

The tenth image signal selection unit m10 outputs the red image signal VData supplied from the tenth decoder D10 to the tenth image signal output unit 130 of the output buffer unit 144 when the first polarity control signal POL1 is in the first logic state. And supplies it to the buffer line Im-2. When the first polarity control signal POL1 is in the second logic state, the first polarity control signal POL1 is supplied from the fourth decoder D4 through the eighth image signal path selection section s8, The red image signal VData of positive polarity supplied from the image signal VData or the fifth decoder D5 is supplied to the tenth buffer line Im-2 of the output buffer unit 144. [ At this time, the positive or negative red image signal VData supplied to the tenth buffer line Im-2 is data supplied to the tenth input channel Cm-2.

The eleventh image signal selecting section m11 is connected to the eleventh decoder D11 through the first switching section s9a of the ninth image signal path selecting section s9 when the first polarity control signal POL1 is in the first logic state 1 to the eleventh buffer line Im-1 of the output buffer unit 144, the negative green image signal VData supplied from the first decoder D4 or the positive green image signal VData supplied from the fourth decoder D4 And supplies the positive green image (S9) supplied from the fifth decoder (D5) through the second switching unit (s9b) of the ninth image signal path selection unit s9 when the first polarity control signal POL1 is in the second logic state And supplies the negative green image signal VData supplied from the signal VData or the eleventh decoder D11 to the eleventh buffer line Im-1 of the output buffer unit 144. [ At this time, the positive or negative green image signal VData supplied to the eleventh buffer line Im-1 is data supplied to the eleventh input channel Cm-1.

The twelfth image signal selecting section m12 selects the twelfth image signal D12 through the first switching section s10a of the tenth image signal path selecting section s10 when the first polarity control signal POL1 is in the first logic state, To the twelfth buffer line Im of the output buffer unit 144 and supplies the positive blue image signal VData supplied from the first decoder D3 or the negative blue image signal VData supplied from the third decoder D3 to the twelfth buffer line Im of the output buffer unit 144, When the first polarity control signal POL1 is in the second logic state, the negative polarity blue image signal supplied from the sixth decoder D6 through the second switching unit s10b of the tenth image signal path selection unit s10, To the twelfth buffer line Im of the output buffer unit 144, the positive blue image signal (VData) supplied from the first decoder (VData) or the twelfth decoder (D12). At this time, the positive polarity or negative polarity blue image signal VData supplied to the twelfth buffer line Im is data supplied to the twelfth input channel Cm.

The digital-to-analog conversion unit 142 converts the data and the image signals according to the logic states of the first and second polarity control signals POL1 and POL2 using the data path control unit 300 and the image signal path control unit 400. [ The latch data RData is converted into the image signal VData so as to have a polar pattern of a version system of horizontal one dot or horizontal two dots and supplies the image data to the output buffer unit 144. [

For example, when the first and second polarity control signals POL1 and POL2 all have the first logic state, the digital-to-analog converter 142 converts the image signal VData Converts the polarity pattern into a version method with horizontal 2 dots, and supplies it to the output buffer unit 144. At this time, the polarity pattern of the version with the horizontal 2-dot is inverted in units of two input channels in the horizontal direction except for the first input channel (Cm-11) + ".

In addition, the digital-to-analog converter 142 may be configured so that when the first polarity control signal POL1 has the second logic state and the second polarity control signal POL2 has the first logic state, The polarity pattern of the image signal VData is converted into a reversed horizontal two dot version system and supplied to the output buffer unit 144 as shown in Fig. At this time, the polarity pattern of the inverted horizontal 2-dot version is inverted in two input channel units in the horizontal direction except for the first input channel (Cm-11) ++ - ".

Also, the digital-to-analog converter 142 may be configured so that when the first polarity control signal POL1 has the first logic state and the second polarity control signal POL2 has the second logic state, The polarity pattern of the image signal VData is converted into a version method with horizontal one dot and supplied to the output buffer unit 144 as shown in Fig. In this case, the polarity pattern of the version with the horizontal 1 dot has a shape such as "+ - + - + - + - + - + -" in which the polarity is reversed in each input channel in the horizontal direction.

When both the first and second polarity control signals POL1 and POL2 have the second logic state, the digital-analog converter 142 converts the polarity pattern of the image signal VData, And supplies the converted version to the output buffer 144, At this time, the reversed polarity pattern of the horizontal 1-dot version has a shape such as "- + - + - + - + - + - +" in which the polarity is reversed in each input channel in the horizontal direction.

As a result, the digital-to-analog converter 142 converts the path of each of the data and image signals to correspond to the version scheme of 2 horizontal dots or 1 horizontal dot according to the logic states of the first and second polarity control signals POL1 and POL2 The number of decoders is configured to be equal to the number of output channels.

The output buffer 144 buffers the image signal VData of each channel supplied from the digital-analog converter 142 and outputs the buffered signal to the outside through the final output channel. At this time, the output buffer 144 amplifies and outputs the image signal VData in consideration of an external load.

The data driving apparatus 10 according to the embodiment of the present invention includes a first voltage dividing resistor row 122 for generating a red / green gradation voltage and a second voltage dividing resistor row 124 for generating a blue gradation voltage, So that the color temperature according to the gradation can be kept constant.

Furthermore, the present invention can reduce the size of the data driving apparatus 10 by configuring the number of decoders of the digital-analog converting unit 142 equal to the number of output channels of the data driving apparatus 10. [

6 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention.

6, a liquid crystal display according to an exemplary embodiment of the present invention includes an image display unit 100 having a plurality of pixel cells P formed in regions defined by a plurality of data lines DL and gate lines GL, (2); A gate driver 4 for driving a gate line GL of the image display unit 2; A data driver 6 for supplying an image signal to the data line DL of the image display unit 2; A timing controller 8 for supplying data signals R, G and B to the data driver 6 and controlling the data driver 6 and the gate driver 4; And a reference gamma voltage generator 10 for generating a plurality of reference gradation voltages GMA1 to GMAj and supplying the same to the data driver 8.

The image display unit 2 includes spacers (not shown) for maintaining a constant cell gap between an upper substrate (not shown) and a lower substrate (not shown) bonded to each other and facing each other. And a liquid crystal layer (not shown) formed in a liquid crystal space provided by spacers.

The top substrate comprises at least three color filters including red, green and blue; A black matrix defining a pixel cell as well as a separation of each color filter; And a common electrode to which the common voltage Vcom is supplied. Here, the common electrode may be formed on the lower substrate depending on the mode of the liquid crystal.

The lower substrate includes a thin film transistor formed in each pixel cell region defined by the data lines DL and the gate lines GL. And a pixel electrode connected to the thin film transistor. The thin film transistor switches the image signal supplied from the data line DL to the pixel electrode in response to the gate-on voltage supplied from the gate line GL.

The timing controller 8 aligns image data (Data) from the outside and supplies the image data to the data driver 6. The timing control unit 8 may use at least one of a synchronizing signal from the outside, for example, a data enable signal DE informing an effective period of data and a dot clock DCLK determining a data transmission frequency, A gate control signal GCS for controlling the driving unit 4 and a data control signal DCS for controlling the data driving unit 6 are generated. At this time, the timing controller 8 may generate at least one of the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync from the outside to generate the gate and data control signals GCS and DCS. The data control signal DCS includes a source output signal SOE for controlling the data output period of the data driver 6, a source start pulse SSP for instructing the start of data sampling, a source shift clock for controlling sampling timing of data, (SSC) and a polarity control signal (POL) for controlling the voltage polarity of the data. The gate control signal GCS includes a gate output signal GOE for controlling the output of the gate driver 4, that is, an output of the gate-on voltage, a gate start pulse GSP for instructing driving of the gate driver 4, And a gate shift clock (GSC) for specifying a period of the gate-on voltage.

The gate driver 4 generates a gate-on voltage according to the gate control signal GCS from the timing controller 8 and sequentially supplies the generated gate-on voltage to the gate lines GL. Accordingly, the gate lines GL of the image display unit 2 are sequentially driven by the gate-on voltage from the gate driver 4. [ Meanwhile, the gate driver 4 may be formed on the substrate on which the image display unit 2 is formed at the same time as the manufacturing process of the thin film transistor, and connected to the gate line GL.

The reference gamma voltage generator 10 generates a plurality of reference gamma voltages GMA1 to GMAj having different voltage levels by using the series-connected voltage-resistance series and supplies them to the data driver 8.

The data driver 6 includes at least one data driver. Each of the data driving apparatuses has the same configuration as the data driving apparatus 100 according to the embodiment of the present invention shown in Figs. 1 to 5D. Accordingly, the description of each data driving apparatus 100 of the data driving unit 6 will be given instead of the description of the data driving apparatus 100 according to the embodiment of the present invention described above.

The first polarity control signal POL1 supplied to each data driving device 100 of the data driver 6 is the same as the polarity control signal included in the data control signal DCS generated by the timing controller 8 , The second polarity control signal POL2 may be fixed to the first logic state or the second logic state according to the characteristics of the image display section 2. [ Of course, the first and second polarity control signals POL1 and POL2 supplied to the respective data driving apparatuses 100 of the data driver 6 may be varied in accordance with the characteristics of the image data or the image display unit 2, (8).

A plurality of reference gamma voltages GMA1 to GMAj are supplied from the reference gamma voltage generator 10 to the gamma buffer 125 of each data driving apparatus 100 shown in FIG.

As described above, the liquid crystal display device according to the embodiment of the present invention includes the data driving device 10 that can separately control the individually configured red / green gradation voltages and blue gradation voltages, A constant color temperature can be realized in all the areas of black gradation to white gradation to be displayed.

In the liquid crystal display device according to the embodiment of the present invention, the number of decoders configured in the digital-analog converter 142 to convert digital data into image signals is made equal to the number of output channels of the data driver 10 The size of the data driving apparatus 10 can be reduced to cope with a larger size more easily.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 is a block diagram schematically showing a data driving apparatus according to an embodiment of the present invention;

2 is a circuit diagram showing a first embodiment of the gradation voltage generator shown in Fig. 1;

3 is a circuit diagram showing a second embodiment of the gradation voltage generator shown in Fig. 1;

4 is a block diagram schematically showing the digital-analog converter shown in FIG. 1;

FIG. 5A is a diagram showing paths of data and image signals corresponding to a version method with horizontal 2-dot according to the first and second polarity control signals in the embodiment of the present invention; FIG.

FIG. 5B is a diagram showing paths of data and image signals corresponding to inverted horizontal 2-dot inversion systems according to the first and second polarity control signals in the embodiment of the present invention; FIG.

FIG. 5C is a diagram showing paths of data and image signals corresponding to a version system with horizontal one dot according to the first and second polarity control signals in the embodiment of the present invention; FIG.

5D is a diagram showing paths of data and image signals corresponding to inverted horizontal 1-dot inversion methods according to the first and second polarity control signals in the embodiment of the present invention; And

6 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention.

Claims (16)

A digital processing unit for latching red, green, and blue data to be input; (I is a total number of gradations corresponding to the number of bits of the data) using the plurality of reference gamma voltages, the first and second voltages, and the positive polarity and the negative polarity gradation voltage for red / A gradation voltage generator for separately generating a positive polarity and a negative polarity gradation voltage; The red and green latch data supplied from the digital processing unit are converted into positive and negative red and green image signals respectively using the i positive and negative polarity gray voltages, and an analog processing section for converting the blue latch data supplied from the digital processing section into a positive or negative blue image signal by using i positive polarity and negative polarity gradation voltages for blue and outputting the same, The gray-scale voltage generating unit A first voltage dividing resistor row for generating the i blue positive polarity gradation voltages and the i blue positive polarity gradation voltages using a plurality of first voltage dividing resistors connected in series between the first and second voltages; And A second partial pressure generating unit for generating the i positive red / green positive gray scale voltages and the i red / green negative gray scale voltages using a plurality of second voltage dividing resistors connected in series between the first and second voltages, And a resistance column. delete The method according to claim 1, Wherein a resistance value of each of the second voltage-dividing resistors has a resistance value larger than that of the corresponding first voltage-dividing resistors. The method according to claim 1, Further comprising a gamma buffer unit for buffering each of the plurality of reference gamma voltages supplied from the outside and outputting a plurality of buffered reference gamma voltages to the outside, Wherein each of the plurality of buffered reference gamma voltages output by the gamma buffer unit is supplied to any one of nodes among the plurality of first voltage dividing resistors and at the same time, Is supplied to any of the nodes of the data driver. 5. The method of claim 4, Each of the i blue positive polarity gradation voltages and the i blue positive polarity gradation voltages is generated at a node between the plurality of first voltage dividing resistors, Wherein the i positive red / green positive gray scale voltages and the i red / green negative gray scale voltages are generated at nodes between the plurality of second voltage dividing resistors. 6. The method of claim 5, Wherein the highest grayscale voltage among the plurality of blue positive polarity gradation voltages corresponds to the highest reference gamma voltage among the plurality of reference gamma voltages, Wherein the lowest gradation voltage among the plurality of blue negative polarity gradation voltages corresponds to the lowest one of the plurality of reference gamma voltages. The method according to claim 1, Wherein the analog processing unit comprises: A digital-analog converter for converting the latch data into an image signal having a polarity corresponding to the first and second polarity control signals using the red / green gradation voltage and the blue gradation voltage, and outputting the converted image signal; And And an output buffer unit for buffering the image signal supplied from the digital-analog converter. 8. The method of claim 7, Wherein the digital-to-analog conversion unit includes a plurality of data conversion blocks having twelve channels repeatedly arranged in the order of red, green, and blue, each data conversion block comprising: A data converter for converting the red, green, and blue latch data into red, green, and blue image signals using the red / green gradation voltages and the blue gradation voltages; A data path control unit for controlling the path of each of the red, green, and blue latch data supplied from the digital processing unit to the data converting unit through the first to twelfth input channels according to the first and second polarity control signals; And And an image signal path control unit for controlling the paths of the red, green, and blue image signals supplied from the data conversion unit to the output buffer unit according to the first and second polarity control signals, respectively Driving device. 9. The method of claim 8, Wherein the data conversion unit comprises: A first to a twelfth decoder including a positive polarity decoder for converting the latch data into a positive polarity image signal and a negative polarity decoder for converting the latch data into a negative polarity image signal, Wherein the first to twelfth decoders are arranged to be repeated in the order of the positive polarity, the negative polarity, the negative polarity, and the positive polarity. 10. The method of claim 9, Wherein the data path control unit comprises: A first data path control unit for controlling the path of the latch data supplied through the second to twelfth input channels according to the second polarity control signal; And And a control unit for controlling the first, second, fifth, sixth, ninth, and tenth input channels and the path of the latch data supplied through the first data path control unit according to the first polarity control signal, And a second data path control unit for supplying the data to the first to 12th decoders, respectively. 11. The method of claim 10, Wherein the first data path control unit comprises: A first switching unit for outputting latch data of the third or twelfth input channel according to the second polarity control signal, and a second switching unit for outputting latch data of the third or ninth input channel in accordance with the second polarity control signal A first data path selection unit configured as a second switching unit; A first switching unit for outputting latch data of the fourth or eleventh input channel according to the second polarity control signal, and a latch unit for outputting latch data of the fourth or tenth input channel in accordance with the second polarity control signal A second data path selection unit configured as a second switching unit; A third data path selector for outputting the latch data of the eleventh or tenth input channel according to the second polarity control signal; A fourth data path selector for outputting the latch data of the twelfth or ninth input channel according to the second polarity control signal; A first switching unit for outputting latch data of the seventh or eighth input channel according to the second polarity control signal, and a latch unit for outputting latch data of the eighth or seventh input channel in accordance with the second polarity control signal A fifth data path selection unit configured as a second switching unit; A first switching unit for outputting latch data of the eighth or seventh input channel according to the second polarity control signal, and a latch unit for outputting latch data of the seventh or eighth input channel in accordance with the second polarity control signal A sixth data path selection unit configured as a second switching unit; A seventh data path selector for outputting the latch data of the third or sixth input channel according to the second polarity control signal; An eighth data path selector for outputting the latch data of the fourth or fifth input channel according to the second polarity control signal; A first switching unit for outputting the latch data of the eleventh or the fourth input channel according to the second polarity control signal, a second switching unit for outputting the latch data of the fifth or eleventh channel according to the second polarity control signal, A ninth data path selection unit configured of two switching units; And A first switching unit for outputting the latch data of the twelfth or third input channel according to the second polarity control signal, and a second switching unit for outputting the latch data of the sixth or twelfth input channel according to the second polarity control signal And a tenth data path selection unit configured by a second switching unit for performing a second switching operation. 12. The method of claim 11, Wherein the second data path control unit comprises: A first data selector for supplying latch data of a first input channel or latch data of a second input channel to the first decoder according to the first polarity control signal; A second data selector for supplying the latch data of the second input channel or the latch data of the first input channel to the second decoder according to the first polarity control signal; A third data selector for supplying latch data supplied from the first switching unit or the second switching unit of the first data path selector to the third decoder according to the first polarity control signal; A fourth data selector for supplying latch data from the first switching unit or the second switching unit of the second data path selector to the fourth decoder according to the first polarity control signal; A fifth data selector for supplying the latch data of the fifth input channel or the latch data from the third data path selector to the fifth decoder according to the first polarity control signal; A sixth data selector for supplying the latch data of the sixth input channel or the latch data from the fourth data path selector to the sixth decoder according to the first polarity control signal; A seventh data selector for supplying latch data from the first switching unit or the second switching unit of the fifth data path selector to the seventh decoder according to the first polarity control signal; An eighth data selector for supplying latch data from the first switching unit or the second switching unit of the sixth data path selector to the eighth decoder according to the first polarity control signal; A ninth data selector for supplying the latch data of the ninth input channel or the latch data from the seventh data path selector to the ninth decoder according to the first polarity control signal; A tenth data selector for supplying latch data of the tenth input channel or latch data from the eighth data path selector to the tenth decoder according to the first polarity control signal; An eleventh data selector for supplying latch data from the first switching unit or the second switching unit of the ninth data path selector to the eleventh decoder according to the first polarity control signal; And And a twelfth data selector for supplying latch data from the first switching unit or the second switching unit of the tenth data path selector to the twelfth decoder in accordance with the first polarity control signal. Device. 10. The method of claim 9, Wherein the image signal path control unit comprises: A first image signal path control unit for controlling a path of an image signal supplied from the second to twelfth decoders in accordance with the second polarity control signal; And And the image signal supplied from the first, second, fifth, sixth, ninth, and tenth decoders and the image signal supplied through the first image signal path control section, according to the first polarity control signal And a second image signal path control unit for controlling the first image signal and the second image signal and for supplying the control signal to each buffer unit of the output buffer unit. 14. The method of claim 13, Wherein the first image signal path control unit comprises: A first switching unit for outputting an image signal from the third decoder or an image signal from the twelfth decoder in accordance with the second polarity control signal, A first image signal path selection unit configured to configure a second switching unit for outputting an image signal from the third decoder; A first switching unit for outputting an image signal from the fourth decoder or an image signal from the eleventh decoder in accordance with the second polarity control signal, Or a second switching unit for outputting an image signal from the fourth decoder; A third image signal path selection unit for outputting the image signal from the eleventh decoder or the image signal from the tenth decoder in accordance with the second polarity control signal; A fourth image signal path selection unit for outputting the image signal from the twelfth decoder or the image signal from the ninth decoder in accordance with the second polarity control signal; A first switching unit for outputting an image signal from the seventh decoder or an image signal from an eighth decoder in accordance with the second polarity control signal and an image signal from the eighth decoder in accordance with the second polarity control signal A fifth image signal path selection unit configured to configure a second switching unit for outputting an image signal from the seventh decoder; A first switching unit for outputting an image signal from the eighth decoder or an image signal from the seventh decoder in accordance with the second polarity control signal, Or a second switching unit for outputting an image signal from the eighth decoder; A seventh image signal path selection unit for outputting the image signal from the third decoder or the image signal from the sixth decoder according to the second polarity control signal; An eighth image signal path selection unit for outputting the image signal from the fourth decoder or the image signal from the fifth decoder according to the second polarity control signal; A first switching unit for outputting an image signal from the eleventh decoder or an image signal from a fourth decoder in accordance with the second polarity control signal and an image signal from the fifth decoder in accordance with the second polarity control signal A ninth image signal path selection unit configured to configure a second switching unit for outputting an image signal from the eleventh decoder; And A first switching unit for outputting an image signal from the twelfth decoder or an image signal from the third decoder in accordance with the second polarity control signal; And a second switching unit configured to output an image signal from the twelfth decoder or a twelfth image signal path selection unit configured to output an image signal from the twelfth decoder. 15. The method of claim 14, Wherein the second image signal path control unit comprises: A first image signal selection unit for supplying an image signal from the first decoder or an image signal from the second decoder to the first buffer line of the output buffer unit in accordance with the first polarity control signal; A second image signal selection unit for supplying an image signal from the second decoder or an image signal from the first decoder to a second buffer line of the output buffer unit in accordance with the first polarity control signal; A third image signal selection unit for supplying an image signal from the first switching unit or the second switching unit of the first image signal path selection unit to the third buffer line of the output buffer unit according to the first polarity control signal; A fourth image signal selection unit for supplying an image signal from the first switching unit or the second switching unit of the second image signal path selection unit to the fourth buffer line of the output buffer unit in accordance with the first polarity control signal; A fifth image signal selection unit for supplying the image signal from the fifth decoder or the image signal from the third image signal path selection unit to the fifth buffer line of the output buffer unit in accordance with the first polarity control signal; A sixth image signal selector for supplying the image signal from the sixth decoder or the image signal from the fourth image signal path selector to the sixth buffer line of the output buffer unit in accordance with the first polarity control signal; A seventh image signal selection unit for supplying an image signal from the first switching unit or the second switching unit of the fifth image signal path selection unit to a seventh buffer line of the output buffer unit in accordance with the first polarity control signal; An eighth image signal selector for supplying an image signal from the first switching unit or the second switching unit of the sixth image signal path selection unit to the eighth buffer line of the output buffer unit in accordance with the first polarity control signal; A ninth image signal selection unit for supplying the image signal from the ninth decoder or the image signal from the seventh image signal path selection unit to the ninth buffer line of the output buffer unit in accordance with the first polarity control signal; A tenth image signal selecting unit for supplying an image signal from the tenth decoder or the image signal from the eighth image signal path selecting unit to a tenth buffer line of the output buffer unit in accordance with the first polarity control signal; An eleventh image signal selection unit for supplying an image signal from the first switching unit or the second switching unit of the ninth image signal path selection unit to the eleventh buffer line of the output buffer unit in accordance with the first polarity control signal; And And a twelfth image signal selecting unit for supplying an image signal from the first switching unit or the second switching unit of the tenth image signal path selecting unit to the twelfth buffer line of the output buffer unit in accordance with the first polarity control signal, And said data driver is a data driver. An image display unit having a plurality of pixel cells formed for each region defined by a plurality of data lines and gate lines; A gate driver for driving a gate line of the image display unit; A data driver for supplying an image signal to a data line of the image display unit; A timing controller for supplying a data signal to the data driver and controlling the data driver and the gate driver; And And a reference gamma voltage generator for generating a plurality of reference gradation voltages and supplying the generated reference gradation voltages to the data driver, Wherein the data driver comprises the data driver according to any one of claims 1 to 15.

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