CN101452930A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN101452930A CN101452930A CN200810179557.0A CN200810179557A CN101452930A CN 101452930 A CN101452930 A CN 101452930A CN 200810179557 A CN200810179557 A CN 200810179557A CN 101452930 A CN101452930 A CN 101452930A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000000137 annealing Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims description 26
- 238000009792 diffusion process Methods 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000926 separation method Methods 0.000 claims description 6
- 230000011218 segmentation Effects 0.000 claims 2
- 230000003287 optical effect Effects 0.000 abstract description 4
- 230000005855 radiation Effects 0.000 abstract 1
- 230000031700 light absorption Effects 0.000 description 9
- 230000001795 light effect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 230000005457 Black-body radiation Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
- H01L21/2686—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
This invention relates to a semiconductor device in which the temperature irregularity can be reduced without causing a delay in the temperature raising time of the semiconductor substrate when the optical annealing process is performed and thus the circuit performance can be enhanced and a manufacturing method thereof. The semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 mum or less includes a circuit pattern region 20 formed on a semiconductor substrate, and a dummy pattern region 30 formed separately from the circuit pattern region 20 on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern 21, 22. The dummy pattern region has dummy gate patterns 31 that have the same structure as that of a gate pattern 21 used in the integrated circuit pattern and the dummy gate patterns 31 are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.
Description
Technical field
The present invention relates to a kind of surface element of semiconductor substrate by the semiconductor device of photo-annealing, particularly a kind of semiconductor device and manufacture method thereof that is provided with the illusory figure that do not relate to circuit working different with integrated circuit pattern.
Background technology
In order to make the integrated circuit that is configured on the semiconductor substrate become electroactive state, generally adopt following technology, that is in the past, annealing devices such as use heater make semiconductor substrate be in several minutes high temperature.But,, need only anneal, and annealing time is also than reduced significantly in the past to the minimum skin section of semiconductor substrate along with the miniaturization of in recent years circuit.
Therefore, recently, proposed the high-intensity light of irradiation, be in high temperature with the interior semiconductor substrate surface that makes in the several seconds, thus the photo-annealing technology of electroactiveization fine circuits (for example, with reference to non-patent literature 1).In this technology, constitute the irradiates light that sends from light source for the surface irradiation that is configured in the semiconductor substrate on the pedestal (susceptor).The irradiation time of irradiates light be tens of second below, with this reached a high temperature surface temperature moment of semiconductor substrate, thereby have only skin section to be annealed.
As light source, the spike RTA that can use at the black body radiation light of the about 3000K～3500K of irradiation between the several seconds (Rapid Thermal Annealing: rapid thermal annealing), the FLA of the light that shines about 6500K temperature between about 1ms (Flash Lamp Annealing: flash lamp annealing), between about 1ms the monochromatic LSA (Laser Spike Annealing: laser spiking is annealed) etc. of the about 10 μ m of illumination wavelength.
On the other hand, in photo-annealing, on semiconductor substrate, can produce the phenomenon of temperature inequality.When this temperature is not when big,, make circuit performance descend because the threshold voltage of crystal defect that produces because of thermal stress or circuit is inhomogeneous etc.Therefore, following method has been proposed, promptly, by forming dielectric film being formed with on the semiconductor substrate of integrated circuit pattern, on dielectric film, form light absorping film again, with light absorping film absorbing light equably, make surface temperature evenly (for example, with reference to patent documentation 1) with this.
But, in this method, owing to what generate heat in rayed is not that semiconductor substrate itself (semiconductor substrate that comprises integrated circuit patterns such as gate patterns or element separation figure) is formed in the light absorping film on the dielectric film, therefore, from light absorping film generate heat to heat be delivered to by dielectric film till the semiconductor substrate can generation time delay.Thus, the impurity of semiconductor substrate surface unnecessarily is diffused into the depths, thereby causes the deterioration of circuit performance.
Patent documentation 1: the Japan Patent spy opens the 2000-138177 communique
Non-patent literature 1:T.Ito, et al., " 10-15nm Ultras shallow JunctionFormation by Flash-Lamp Annealing ", Jpn.J.Appl.Phys., 2002, Vol.41,2394-2398
Summary of the invention
The present invention is based on above-mentioned problem points and makes, even its purpose is to provide a kind of heating-up time of the semiconductor substrate when not postponing photo-annealing, also can reduce the inequality of temperature, thus can be to improving semiconductor device and the manufacture method thereof that circuit performance contributes.
In order to solve the above problems, the present invention adopts following formation.
Promptly, an embodiment of the invention is characterized in that having: the circuitous pattern zone for the semiconductor device of process with the photo-annealing operation of the irradiates light of dominant wavelength below 1.5 μ m, it forms on semiconductor substrate, has the integrated circuit pattern relevant with circuit working; And illusory graphics field, it leaves formation mutually with described circuitous pattern zone on described substrate, the spacing below 0.4 times with described dominant wavelength periodically disposes the dummy gate electrode figure, and the gate patterns that uses in described dummy gate electrode figure and the described integrated circuit pattern has same structure and irrelevant with circuit working.
In addition, another embodiment of the invention is characterized in that having: the circuitous pattern zone for the semiconductor device of process with the photo-annealing operation of the irradiates light of dominant wavelength below 1.5 μ m, it forms on semiconductor substrate, has the integrated circuit pattern relevant with circuit working; And illusory graphics field, it leaves formation mutually with described circuitous pattern zone on described substrate, the spacing below 2 times with described dominant wavelength periodically disposes the dummy elements isolation pattern, and the element separation figure that uses in described dummy elements isolation pattern and the described integrated circuit pattern has same structure and irrelevant with circuit working.
In addition, another embodiment of the invention is characterized in that having: the circuitous pattern zone for the semiconductor device of process with the photo-annealing operation of the irradiates light of dominant wavelength below 1.5 μ m, it forms on semiconductor substrate, has the integrated circuit pattern relevant with circuit working; And illusory graphics field, it leaves formation mutually with described circuitous pattern zone on described substrate, have and the irrelevant illusory figure of circuit working; Wherein, the wide minimum value of the folder of the described illusory figure in described illusory graphics field is below 2 times of described dominant wavelength.
According to the present invention, by on the surface of semiconductor substrate, being provided with and different illusory graphics field, circuitous pattern zone with illusory figure with integrated circuit pattern, even the heating-up time of the semiconductor substrate when not postponing photo-annealing, also can reduce the temperature uneven phenomenon, thereby can contribute improving circuit performance.
Description of drawings
Fig. 1 is the wide schematic diagram of folder that is used to illustrate figure.
Fig. 2 is the schematic diagram of expression basic circuit structure.
Fig. 3 is the figure that the figure of the semiconductor device of expression first execution mode disposes.
Fig. 4 is the figure of indication cycle's configuration as the grid of circuitous pattern.
Fig. 5 is the performance plot of the figure dependency characteristic of the absorptivity in the gate configuration of presentation graphs 4.
Fig. 6 is the close quarters of presentation graphic and evacuates the figure that the example that exists is mixed in the zone.
Fig. 7 is the performance plot of the relation between expression temperature difference and the light absorption rate variance.
Fig. 8 is the spacing of expression gate patterns and the performance plot of the relation between the absorptivity.
Fig. 9 is the example of isolated GC is used in expression as illusory figure figure.
Figure 10 is the figure that the example of illusory figure of cross or circular illusory figure is used in expression.
Figure 11 is the figure that the figure of the semiconductor device of expression second execution mode disposes.
Figure 12 is the figure of indication cycle's configuration as the example of the STI of circuitous pattern.
Figure 13 is the dependent performance plot of figure of the absorptivity during the STI of expression Figure 12 disposes.
Figure 14 is the spacing of expression STI and the performance plot of the relation between the absorptivity.
Figure 15 is the example of isolated STI is used in expression as illusory figure figure.
Figure 16 is the figure that the figure of the semiconductor device of expression the 3rd execution mode disposes.
Figure 17 is the figure of the variation of expression the 3rd execution mode.
Reference numeral
1: illusory figure
10: semiconductor substrate
11: the semiconductor substrate interarea
20: the circuitous pattern zone
21：GC
22：STI
30: illusory graphics field
31: illusory GC (dummy gate electrode figure)
32: the illusory graphics field of unit
41: close quarters
42: evacuate the zone
50: the isolation pattern zone
51: illusory GC
55: the illusory figure of cross
56: circular illusory figure
70: illusory graphics field
71: illusory STI (dummy elements isolation pattern)
80: the isolation pattern zone
81: illusory STI
100: the semiconductor integrated circuit inner region
110: square area
111: the circuitous pattern zone
112: illusory graphical set
Embodiment
Before the explanation embodiments of the present invention, principle of the present invention is described.
In the present invention, when the photo-annealing operation, the place that the absorptivity in semiconductor device is low disposes illusory figure.At this, illusory figure has feature on the dominant wavelength level (order) of the irradiates light that is used for the photo-annealing operation.Therefore this illusory figure makes the absorptivity unification owing to the influence absorptivity height because of interference of light effect.
At this, the dominant wavelength of irradiates light is the light absorbing wavelength region may of semiconductor substrate, is below the 1.5 μ m.But, be under the monochromatic situation at irradiates light, dominant wavelength is the peak value of the spectrum of irradiates light.At irradiates light is not under the monochromatic situation, by having the spectral function of 2500K to the black body radiation of the temperature of 7000K, when the spectrum of 200nm match in the wavelength region may of 2 μ m (fitting) irradiates light, with the peak value of spectral function as dominant wavelength.
Do not need during the irrelevant and circuit working of the work of illusory figure and electric circuit.In addition, in the cloth line procedures after the photo-annealing operation when the enterprising row wiring of circuit, need be at the enterprising row wiring of illusory figure.The circuit that connects up can be regarded as illusory figure.In addition, the circuit of the different shape relevant with electric circuit work is called circuitous pattern.
As the size of concrete illusory figure, suppose that the wide minimum value of folder is below the twice of dominant wavelength.At this, will press from both sides wide being defined as follows.As shown in Figure 1, the surface that disposes the semiconductor substrate of semiconductor integrated circuit figure is called interarea 11, and hypothesis disposes illusory figure 1 on this interarea 11.At this, get orthogonal coordinates X, Y on the interarea, and get two straight lines that are parallel on the coordinate direction.Then, illusory figure 1 is included in the zone that two straight lines fold.With the interval of these two straight lines of constriction gradually, when each straight line and illusory figure 1 join, the interval of these two straight lines is called the wide W of folder
H
But, when illusory figure is periodically arranged more than two cycles in one direction with certain spacing P, suppose that spacing P is the wide W of folder
H(P=W
H).In addition, illusory figure is periodically being arranged more than two cycles respectively on the both direction, and all directions suppose that little spacing is the wide W of folder when having different spacings
H
Circuit structure has basic structure as shown in Figure 2, and by GC (Gate Conductor: grid conductor) 21 and STI (Shallow Trench Isolation: shallow trench isolation from) 22 constitute.The size of GC21 or STI22 has a variety of, and it is complicated that the shape of circuitous pattern becomes on the whole, but basic structure is identical.At this, GC21 is identical with the refractive index of semiconductor substrate 10, the refractive index of STI22 and SiO
2Refractive index identical.For the design process that makes illusory figure becomes simply as far as possible, can be identical shaped with illusory figure and circuitous pattern.Therefore, as illusory figure, can consider by constituting with irrelevant illusory GC or the illusory STI of circuit working.
At this, so-called illusory GC is for to have identical optical characteristics with the GC of circuitous pattern, and identical with GC to the restriction of shapes such as thickness or Breadth Maximum.In addition, also have identical optical characteristics for illusory STI, and the restriction of shape is identical with STI with the STI of circuitous pattern.In addition, in illusory graphics field, the coverage rate of illusory GC is more than 30% and below 80%, and the coverage rate of illusory STI is more than 45% and less than 100%.In addition, so-called coverage rate is the occupied area ratio on the interarea of semiconductor substrate.For example, the coverage rate of the illusory GC in illusory graphics field is the occupied area ratio shared to the occupied area of illusory graphics field of illusory GC.
With in the evacuation zone in the surface of semiconductor substrate as the configuring area of illusory figure.At this, defining and evacuating the zone is the zone that does not have circuitous pattern, and comprises the zone of one side for the foursquare size of dominant wavelength for having.In addition, be called close quarters with evacuating zone in addition, zone.At the circuitous pattern that is configured in the dominant wavelength level on the close quarters or has feature on the little level than dominant wavelength level.
In addition, use SiO usually for STI
2, so refractive index is different from semiconductor substrate.Mix in the zone that exists at semiconductor substrate and STI, absorptivity is than semiconductor-based plate hight.Therefore, even in the low zone of absorptivity, dispose illusory STI, also can realize the unification of absorptivity.At this moment, the size of illusory STI is below the thermal diffusion length.But, can consider as follows as thermal diffusion length.In the chart that changes in the time of expression photo-annealing exposure intensity, the half value full width of the peak value of exposure intensity is made as Δ t, the thermal diffusion coefficient that is up among the Da Wendu of semiconductor substrate is made as κ, then with L=(κ Δ t)
1/2The amount of definition is as thermal diffusion length.
In addition, during illusory figure, consider that the temperature gradient of the following rank of thermal diffusion length (scale) is roughly homogenized, also can consider to make by the thermal diffusion length rank to average the absorptivity distribution unification of having changed in configuration.Therefore, on the interarea of semiconductor substrate, in semiconductor integrated circuit, Jiang Gebian is divided into thermal diffusion length following square or rectangular region, and each zone of being cut apart is called cut zone.In described each cut zone,, evacuating the illusory figure of area configurations by following two kinds of methods.First method is, the set of illusory figure is called illusory graphical set, make illusory graphical set and close quarters coverage rate be aggregated in be made as in each cut zone certain.Second method is that the coverage rate of illusory graphical set is made as in each cut zone necessarily.
As mentioned above, (evacuate the zone) in the low zone of absorptivity and dispose the high illusory figure of absorptivity, make absorptivity, realize unification, thereby reduce the temperature inequality with this on the whole near higher limit.If the characteristic rank of the circuitous pattern in semiconductor integrated circuit then uprises because of interference of light effect absorptivity below the dominant wavelength level of light.On the other hand, perhaps there is not the evacuation zone of circuitous pattern in the zone that the characteristic rank of circuitous pattern is bigger than the dominant wavelength level of light, and absorptivity is low.Therefore, the illusory figure that will have feature on the dominant wavelength level of light is configured in to be evacuated in the zone, realizes unification with this on the direction that makes absorptivity near higher limit.Thus, reduce the temperature inequality, can prevent the deterioration of circuit performance.
Below, the execution mode shown in describes the present invention in detail with reference to the accompanying drawings.
First execution mode
Fig. 3 is the figure that the figure of the semiconductor device of expression first execution mode of the present invention disposes.
Configuration has the circuitous pattern zone 20 of the integrated circuit pattern relevant with circuit working and has illusory graphics field 30 with the irrelevant illusory figure of circuit working on the interarea 11 of the semiconductor substrate of Si etc.Semiconductor substrate interarea 11 is handled by photo-annealing by the method that is called spike RTA in semiconductor manufacturing process.At this, the dominant wavelength of the irradiates light of spike RTA is 1 μ m.If the dominant wavelength of irradiates light more than 1.5 μ m, then sees through semiconductor substrate, can not be to semiconductor-based Plate supplying heat, therefore need be below 1.5 μ m.
At this, in illusory graphics field 30, if having the zone definitions of an illusory figure is the illusory graphics field 32 of unit, then the figure coverage rate of the illusory GC31 in the illusory graphics field 32 of unit is 50%, thereby the figure coverage rate in the illusory graphics field 32 of unit is more than 30% and in the scope below 80%.In addition, with the number that can fully fill the mode fetch cycle of evacuating zone 42 and the size L of illusory GC31
DGC
The absorptivity in circuitous pattern zone 20 in the present embodiment is 80～85%.At this, absorptivity is in shining the light of unit are, do not reflect or scatters to the outside and be absorbed into the ratio of inner energy, defines in than the little zone of the thermal diffusion length of semiconductor substrate.
In addition, suppose that circuitous pattern zone 20 and illusory graphics field 30 immediate distances are closest-approach distance D
Min, and this closest-approach distance D
MinBe separated by more than the 1 μ m.The real work as electric circuit of semiconductor integrated circuit is to realize by circuitous pattern zone 20, and the 30 pairs of work as circuit in illusory graphics field do not exert an influence.
Below, embodiments of the present invention are described.
At first, narration is as the relation of the gate patterns and the absorptivity of circuitous pattern.As shown in Figure 4, consideration has a determining deviation P, certain graphic width W in one direction
DGCThe periodic circuit figure.At this, suppose the size L of GC21
GCFully big than dominant wavelength.By present inventor's calculating, clear and definite absorptivity at this moment has circuitous pattern dependence as shown in Figure 5.
In Fig. 5, with dominant wavelength spacing P is carried out after the standardization as transverse axis, will be to the graphic width W of spacing P
GCRatio (duty ratio) as the longitudinal axis.As can be seen, absorptivity is along with spacing P changes significantly from this Fig. 5, and absorptivity increases along with reducing of spacing.The increase phenomenon of this absorptivity is represented interference of light effect.At this, on figure coverage rate 50%, the maximum of absorptivity is that about 82%, minimum value is about 68%, and the amplitude of fluctuation of absorptivity is about 14%.In addition, with size L
GCBe dominant wavelength level when following, absorptivity has improved several % degree.
Because light characteristic is identical, so these phenomenons also are the same for illusory graphics field 30.In addition, if the circuitous pattern that is made of STI is carried out identical calculating, then absorptivity changes in about 85% scope about 68% as can be seen.Can consider that various circuitous patterns are combinations of the different size separately of GC and STI.Thus, the absorptivity in the various circuitous patterns changes in about 85% scope about 68%, and the higher limit of absorptivity is about 85%.The spacing P of the illusory graphics field 30 among above-mentioned Fig. 3
D Be 40% of dominant wavelength, the graphic width W of illusory GC31
DGCFor to spacing P
D50%, as shown in Figure 5, absorptivity is about 80%.
According to above-mentioned, in Fig. 3, when not disposing illusory figure in evacuating zone 42, the absorptivity of evacuating in the zone is about 68%.On the other hand, the absorptivity in circuitous pattern zone 20, circuitous pattern zone 20 has feature on below the dominant wavelength, be about 80%～85%.And the light absorption rate variance of evacuating zone 42 and circuitous pattern zone 20 is about 12%～17% degree.Therefore, by the illusory graphics field 30 of configuration in evacuating zone 42, the light absorption rate variance that makes illusory graphics field 30 and circuitous pattern zone 20 is in 5%, thus absorptivity unification on the whole.
If the temperature in the semiconductor integrated circuit is uneven big, the inhomogeneous circuit performance deterioration of the threshold voltage of crystal defect that produces because of thermal stress or circuit then.Particularly, circuit cisco unity malfunction when the threshold voltage of circuit inhomogeneous big.In order to guarantee operate as normal, the temperature inequality need be suppressed in 4～6 ℃.Be accompanied by the miniaturization of circuit in recent years, need do one's utmost to suppress the inhomogeneous of threshold voltage, thereby the temperature inequality must be suppressed in 4 ℃.In order to realize this purpose, the amplitude of fluctuation of absorptivity need be suppressed within the specific limits, thereby the permissible range of this absorptivity can be for as follows.
In semiconductor integrated circuit, owing to evacuate the useless zone that zone be and circuit working has nothing to do, so it is good more to evacuate the more little efficient in zone.Usually, evacuating regional rank maximum also is 10mm.Therefore, as shown in Figure 6, the set that will have the circuitous pattern of feature on below the dominant wavelength level is made as close quarters 41, considers close quarters 41 and evacuates zone 42 and mix situations about existing.At this, evacuating zone 42 be square area, one side length be 10mm.This length is for evacuating other maximum of level in zone 42.
In addition, the absorptivity of close quarters 41 is 85%, and the absorptivity of evacuating zone 42 changes between 65% to 85%.At this moment, with the thermal diffusion equation as fundamental equation, calculating reaches the about 1100 ℃ Temperature Distribution of temperature being up to, from this result of calculation obtain shown in Fig. 7 at close quarters 41 and evacuate the interregional light absorption rate variance in zone 42 and the relation of temperature difference.At this, transverse axis is the light absorption rate variance, and the longitudinal axis is a temperature difference.
According to Fig. 7, can know in order to make temperature difference in 4 ℃, need the light absorption rate variance in 5%.Thus, as illusory figure, can dispose absorptivity and begin in 5%, be i.e. figure below 85 more than 80% from higher limit.The absorptivity of the illusory graphics field 30 in Fig. 3 is about 80%, thereby satisfies this condition.
In addition, in Fig. 3, if illusory graphics field 30 too near circuitous pattern zone 20, then produces leakage current, thereby causes the increase of power consumption or the generation of heat.Therefore, by with closest-approach distance D
MinLeave more than the 1 μ m, can prevent the generation of leakage current.
As mentioned above, according to present embodiment, by illusory graphics field 30 is set except circuitous pattern zone 20 on the interarea 11 of semiconductor substrate in addition, make absorptivity on the semiconductor substrate on the whole near higher limit, realize unification with this, thereby can reduce the inequality of the temperature in the real estate, described circuitous pattern 20 has the integrated circuit pattern of GC21, STI22 etc., the zone of described illusory graphics field 30 for illusory GC31 is periodically disposed with the spacing below 0.4 times of the dominant wavelength of irradiates light.Thus,, also can reduce the temperature inequality, thereby can contribute improving circuit performance even do not postpone the heating-up time of the semiconductor substrate when carrying out photo-annealing.
In addition, illusory in the present embodiment figure is rectangular-shaped, therefore, is convenient to make in the manufacturing process of semiconductor integrated circuit.Also have, illusory GC31 can form simultaneously with the GC21 in circuitous pattern zone 20, therefore, can not increase operation because of forming illusory graphics field 30.
In addition, the present invention is not limited to above-mentioned execution mode, can carry out various distortion in the scope that does not break away from its aim.
For example, absorptivity except above-mentioned, also exists multiple more than 80% and at the illusory figure below 85%.According to above-mentioned Fig. 5, be the point that there is the absorptivity maximum in about 50% place in duty ratio.In Fig. 8, the expression duty ratio is 50% o'clock spacing and the relation between the absorptivity.Can know that from this Fig. 8 if spacing about below 40% in dominant wavelength, then absorptivity is more than 80%.In addition, in the spacing in this scope, according to described Fig. 5, if duty ratio is about more than 30% below 60%, then absorptivity is more than 80%.Also have, if spacing is below 20% of dominant wavelength, then duty ratio about more than 30% in the scope below 80% absorptivity be more than 80%.
Thus, in the illusory GC31 shown in above-mentioned Fig. 3, as long as spacing P
DAt below 40% of dominant wavelength, graphic width W
DGCAt spacing P
DMore than 30% and 80% following just can.At this, the figure coverage rate of the illusory GC31 in illusory graphics field 30 is more than 50% and below 80%.
In addition, above-mentioned conclusion is not only for periodic figure, and for the isolation pattern of one-period amount too.This is to play interference of light effect because have the illusory figure of feature on wavelength level, improves the reason of absorptivity with this.Therefore, as shown in Figure 9, that isolation pattern is also passable as illusory figure.At this, be isolation pattern zone 50 by dotted line institute area surrounded, in this zone 50, can not comprise other illusory figure or circuitous pattern.
This isolation pattern zone 50 is made of illusory GC51, and illusory GC51 is shaped as rectangle on the face of semiconductor substrate.In addition, the width W in isolation pattern zone 50
PBe below 40% of dominant wavelength, size L
DGCBe the size of the degree that do not contact, size W with circuitous pattern or other illusory figure
DGCBe illusory graphics field width W
PMore than 30% and in 80%.At this, because size W
DGCBe below 0.4 times of dominant wavelength, therefore the minimum value of the minor face of illusory GC51 is below 0.3 times of dominant wavelength.In addition, compare, in isolated illusory graphics field 50 with periodic figure, the increase of the absorptivity that causes because of interference of light effect is little of number % degree, but since simple shape therefore make easily, even, also can dispose evacuating under the narrow or complicated situation in zone.
In addition, as aforesaid illusory figure, being shaped as by rectangular shape on the face of semiconductor substrate constitutes.This is that convenience owing to having considered illusory graphic making is made, but illusory figure is not limited to this shape.Even the shape difference of illusory figure, if the coverage rate of the illusory GC in illusory graphics field is identical, the influence of then interference of light effect is almost constant, and absorptivity much at one.
For example, in Figure 10, can dispose criss-cross illusory figure 55 or circular illusory figure 56.At this moment, the folder of illusory figure separately is wide is the length below 0.4 of the dominant wavelength of irradiates light.In addition, the figure coverage rate in illusory graphics field separately is in the scope more than 30% and below 80%.These illusory figure, the absorptivity in each illusory graphics field distribute and are not partial to a direction, thus the high conformity of absorptivity.
In addition, in the photo-annealing with dominant wavelength different with spike RTA, above-mentioned fundamental property is identical, can think that the size of figure is come classification by dominant wavelength substantially.
Second execution mode
Figure 11 is the figure that the figure of the semiconductor device of expression second execution mode disposes.In addition, put on identical Reference numeral, omitted its detailed description for the part identical with Fig. 3.
In the first embodiment, narrate, similarly can consider the circuit that constitutes by illusory STI for the illusory graphics field that constitutes by illusory GC.In Figure 11, the semiconductor integrated circuit that configuration is made of circuitous pattern zone 20 and illusory graphics field 70 on semiconductor substrate interarea 11.Circuitous pattern zone 20 is made of GC21 and STI22.At this, circuitous pattern zone 20 has such feature below dominant wavelength, and the absorptivity in circuitous pattern zone 20 is 80%～85%.In addition, in evacuating the zone, be provided with the illusory graphics field 70. that periodically disposes illusory STI (dummy elements isolation pattern)
At this, get regional periodicity of fully landfill evacuation and the size L of illusory STI71
DSTIIn addition, in the figure, the wide spacing P that is equivalent to of the folder of each illusory STI71
D, spacing P
DSize identical with dominant wavelength, be 1 μ m, the graphic width W of illusory STI71
DSTIBe spacing P
D80%, i.e. 0.8 μ m.At this, the figure coverage rate of the illusory STI71 in illusory graphics field 70 is 80%.
Below, to the present embodiment effect, describe.
As shown in figure 12, consider to have certain spacing P in one direction, certain graphic width W
STIPeriodic circuitous pattern.At this, the size L of STI22
STIBig more a lot of than dominant wavelength.At this moment, absorptivity has circuitous pattern dependence shown in Figure 13.
In Figure 13, spacing P is carried out after the standardization as transverse axis with dominant wavelength, will be to the graphic width W of spacing P
STIRatio (duty ratio) as the longitudinal axis.As can be seen from the figure 13, absorptivity is change significantly along with the variation of spacing P, and absorptivity increases during with pitch smaller.The pitch dependence of this absorptivity is owing to interference of light effect produces.
The maximum of absorptivity is about 85% in Figure 13.According to this Figure 13, equal dominant wavelength and duty ratio is at 80% o'clock at spacing P, absorptivity is about 85%.This is because in described Figure 11, and it equates with the size of illusory graphics field, and is about 85% thereby the absorptivity of illusory graphics field 70 becomes, and becomes the higher limit of absorptivity.Have again, the light absorption rate variance of circuitous pattern zone 20 and illusory graphics field 70 in 5%, thereby the temperature inequality can be suppressed at below 4 ℃.
In addition, the present invention is not limited to above-mentioned execution mode, can carry out various distortion in the scope that does not break away from its aim.
For example, absorptivity also exists a variety of except aforesaid more than 80% and 85% following illusory figure.In described Figure 13, be about 80% for the duty ratio on the maximum point at absorptivity.The spacing when in addition, in Figure 14, representing duty ratio 80% and the relation of absorptivity.As can be seen from Figure 14, if think that absorptivity reaches more than 80%, then need to make spacing about below 200% in dominant wavelength.In addition, according to Figure 13, in the spacing of this scope, duty ratio is about more than 45% and less than 100%, and absorptivity is more than 80%.
Thus, in the illusory figure shown in described Figure 11, the spacing P of illusory STI71
DAt below 200% of dominant wavelength, preferably more than 50% below 140%, graphic width W
DSTIAt spacing P
DJust can more than 45% and less than 100%.At this, the figure coverage rate of the illusory STI71 in nominal region 70 is more than 45% and less than 100%.
In addition, as shown in figure 15, also can be with isolation pattern 81 as illusory figure.At this, the zone that is enclosed in the dotted line is isolation pattern zone 80, should not comprise other illusory figure or circuitous pattern in this zone 80.Isolation pattern zone 80 is made of illusory STI81, and the illusory STI81 on the semiconductor substrate face is shaped as rectangle.In addition, the width W in isolation pattern zone 80
PBe below 200% of dominant wavelength, size L
DSTIWith in the scope that circuitous pattern or other illusory figure contact do not getting bigger scope, the size W of illusory STI81
DSTIBe illusory graphics field width W
PMore than 45% and less than 100%.At this, size W
DSTIBelow the twice for dominant wavelength, therefore, the minor face of illusory STI81 is below the twice of dominant wavelength.
In addition, the shape of illusory figure on the semiconductor substrate face is not limited only to rectangle, also can be cross or circle.
In addition, in Figure 15, size W
DSTIAnd L
DSTIAlso can be below thermal diffusion length, illusory graphics field 80 also can all be made of illusory STI81.At this moment, the coverage rate of illusory STI81 is 100%.At this, be about 1100 ℃ at the Da Wendu that is up to of semiconductor substrate, when irradiation time was a second, thermal diffusion length was about 3mm.In this illusory figure, absorptivity is more than 80%.In fact, in Figure 13, be not limited to spacing, so long as duty ratio is more than 80%, absorptivity just reaches more than 80% so.This is the different reasons that reduce reflection of light with semiconductor substrate of refractive index owing to STI.But, if spacing reaches the twice of dominant wavelength when above, generation light absorption rate variance in illusory figure.If illusory graphics field is below thermal diffusion length, then the temperature inequality that produces because of this light absorption difference is homogenized.
In addition, in the photo-annealing with dominant wavelength different with spike RTA, aforesaid fundamental property is identical, except thermal diffusion length, can think that the size of figure is almost by the classification of dominant wavelength institute.
The 3rd execution mode
Figure 16 is the figure that the figure of the semiconductor device of expression the 3rd execution mode of the present invention disposes.
On semiconductor substrate interarea 11, there is semiconductor integrated circuit inner region 100 as the subregion of semiconductor integrated circuit integral body.This semiconductor integrated circuit inner region 100 is divided into one side is the square area 110 of thermal diffusion length.Configuration is as the illusory graphical set 112 of the set of illusory figure in each square area.At this, the illusory figure of each of illusory graphical set 112 is at the illusory figure described in first or second execution mode before.In addition, the zone of fine circuits graphics field 111 for disposing the fine circuits figure that below dominant wavelength, has feature.At this, in each square area 110, dispose illusory figure in certain mode that adds up to of the coverage rate of shared zone of illusory graphical set 112 and fine circuits graphics field 111.
Below, the effect to present embodiment describes.
In each square area 110, the thermal source at the initial stage in photo-annealing when irradiation distributes by thermal diffusion and homogenizing.Consider this point, even in square area 110, exist absorptivity poor, can the occurrence temperature inequality yet.But, in different square area 100,, then produce the temperature inequality if the difference of the mean value of the absorptivity in zone is big separately.Therefore, if make the mean value of the absorptivity in each square area 110 identical, then can suppress the temperature inequality.The zone that absorptivity is high is the shared zone of fine circuits graphics field 111 and illusory graphical set 112, and this zone is called close quarters.In addition, according to the distribution of close quarters, roughly determine absorptivity, absorptivity height when close quarters is big with the coverage rate of evacuating the zone.
Therefore, certain by the coverage rate that makes close quarters in each square area 110, make the absorptivity unification.By disposing illusory figure in the mode that satisfies this condition, promptly use the illusory figure of limited number, also can realize the unification of absorptivity expeditiously.
In addition, the present invention is not limited to above-mentioned execution mode, in the scope that does not break away from its aim, can carry out various distortion.
For example, as shown in figure 17, dispose illusory figure in the illusory figure coverage rate certain mode in each square area in square area 110.Thus, in each square area 110, it is big that the coverage rate of close quarters becomes, and absorptivity is near higher limit, thereby absorptivity is by unification.At this moment, owing to do not need to calculate the coverage rate of close quarters, therefore make becoming easy.
In addition, the length on each limit of square area can be arbitrarily in the scope below thermal diffusion length.Have, square area also can be rectangular region again, so long as just can below thermal diffusion length in each limit.In addition, illusory figure not necessarily is confined to gate patterns or element separation figure, applicable to the various figures that are formed in the circuitous pattern zone.
Claims (15)
1. semiconductor device, it is characterized in that having through the photo-annealing operation with the irradiates light of dominant wavelength below 1.5 μ m:
The circuitous pattern zone, it forms on semiconductor substrate, has the integrated circuit pattern relevant with circuit working; And
Illusory graphics field, it leaves formation mutually with described circuitous pattern zone on described substrate, the spacing below 0.4 times with described dominant wavelength periodically disposes the dummy gate electrode figure, and the gate patterns that uses in described dummy gate electrode figure and the described integrated circuit pattern has same structure and irrelevant with circuit working.
2. semiconductor device as claimed in claim 1 is characterized in that,
The figure coverage rate of the described dummy gate electrode figure in described illusory graphics field is 30～60%.
3. semiconductor device as claimed in claim 1 is characterized in that,
The spacing of described dummy gate electrode figure is below 0.2 times of described dominant wavelength, and the figure coverage rate is 30～80%.
4. semiconductor device, it is characterized in that having through the photo-annealing operation with the irradiates light of dominant wavelength below 1.5 μ m:
The circuitous pattern zone, it forms on semiconductor substrate, has the integrated circuit pattern relevant with circuit working; And
Illusory graphics field, it leaves formation mutually with described circuitous pattern zone on described substrate, the spacing below 2 times with described dominant wavelength periodically disposes the dummy elements isolation pattern, and the element separation figure that uses in described dummy elements isolation pattern and the described integrated circuit pattern has same structure and irrelevant with circuit working.
5. semiconductor device as claimed in claim 4 is characterized in that,
The figure coverage rate of the described dummy elements isolation pattern in described illusory graphics field is 45～100%.
6. semiconductor device as claimed in claim 4 is characterized in that,
The spacing of described dummy elements separated graphics is 0.5～1.4 times of described dominant wavelength, and the figure coverage rate is 50～100%.
7. as claim 1 or 4 described semiconductor devices, it is characterized in that,
Described dummy gate electrode figure or described dummy elements isolation pattern are rectangle or cross.
8. as claim 1 or 4 described semiconductor devices, it is characterized in that,
Minimum distance between described circuitous pattern zone and the described illusory graphics field is set to more than the 1 μ m.
9. semiconductor device, it is characterized in that having through the photo-annealing operation with the irradiates light of dominant wavelength below 1.5 μ m:
The circuitous pattern zone, it forms on semiconductor substrate, has the integrated circuit pattern relevant with circuit working; And
Illusory graphics field, it leaves formation mutually with described circuitous pattern zone on described substrate, have and the irrelevant illusory figure of circuit working;
Wherein, the wide minimum value of the folder of the described illusory figure in described illusory graphics field is below 2 times of described dominant wavelength.
10. semiconductor device as claimed in claim 9 is characterized in that,
Described illusory figure with described integrated circuit pattern in rectangular-shaped dummy gate electrode figure with same structure of the gate patterns that uses form, the graphic width of the minor face of the wide and described dummy gate electrode figure of the folder of described dummy gate electrode figure is identical, and described graphic width is set to below 0.3 times of described dominant wavelength.
11. semiconductor device as claimed in claim 9 is characterized in that,
Described illusory figure with described integrated circuit pattern in rectangle or foursquare dummy elements isolation pattern with same structure of the element separation figure that uses form, the graphic width of the minor face of the wide and described dummy elements isolation pattern of the folder of described dummy elements isolation pattern is identical, and described graphic width is set to 0.5～1.4 times of described dominant wavelength.
12. semiconductor device as claimed in claim 11 is characterized in that,
The coverage rate of the dummy elements isolation pattern in the described illusory graphics field is 100%, and the long limit of described dummy elements isolation pattern is below thermal diffusion length.
13. each the described semiconductor device as in the claim 1 to 6,9 to 12 is characterized in that,
The lip-deep semiconductor integrated circuit with described substrate form Region Segmentation become each limit below thermal diffusion length square or during rectangular region, the total of the described circuitous pattern zone in each cut zone and the figure coverage rate of described illusory graphics field is roughly certain.
14. each the described semiconductor device as in the claim 1 to 6,9 to 12 is characterized in that,
The lip-deep semiconductor integrated circuit with described substrate form Region Segmentation become each limit below thermal diffusion length square or during rectangular region, the figure coverage rate of the described illusory graphics field in each cut zone is roughly certain.
15. the manufacture method of a semiconductor device is characterized in that,
To as each the described semiconductor device in the claim 1 to 6,9 to 12, be light below the 1.5 μ m by surface irradiation dominant wavelength to described substrate, carry out photo-annealing.
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| JP315056/2007 | 2007-12-05 | ||
| JP2007315056A JP5242145B2 (en) | 2007-12-05 | 2007-12-05 | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103995A (en) * | 2009-12-21 | 2011-06-22 | 台湾积体电路制造股份有限公司 | Method for fabricating an integrated circuit device |
| CN102403205A (en) * | 2010-09-08 | 2012-04-04 | 株式会社东芝 | Semiconductor device manufacturing method |
| CN111668329A (en) * | 2020-06-22 | 2020-09-15 | 三明学院 | Novel photoelectric detector |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI384603B (en) * | 2009-02-17 | 2013-02-01 | Advanced Semiconductor Eng | Substrate structure and package structure using the same |
| WO2011033676A1 (en) * | 2009-09-18 | 2011-03-24 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JP5551409B2 (en) * | 2009-10-23 | 2014-07-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device design method, design apparatus, design program, and semiconductor device |
| JP2011205049A (en) * | 2010-03-26 | 2011-10-13 | Toshiba Corp | Semiconductor integrated circuit |
| JPWO2012160736A1 (en) * | 2011-05-20 | 2014-07-31 | パナソニック株式会社 | Semiconductor device |
| JP5733054B2 (en) * | 2011-06-29 | 2015-06-10 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method |
| JP6012987B2 (en) * | 2012-02-29 | 2016-10-25 | 株式会社東芝 | Manufacturing method of image sensor |
| JP5826672B2 (en) | 2012-02-29 | 2015-12-02 | 株式会社東芝 | Image sensor and manufacturing method thereof |
| US9059126B1 (en) * | 2013-12-23 | 2015-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method of manufacturing the same |
| JP7381276B2 (en) | 2019-09-27 | 2023-11-15 | ラピスセミコンダクタ株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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| JP2000112114A (en) * | 1998-10-08 | 2000-04-21 | Hitachi Ltd | Semiconductor device and production of semiconductor device |
| JP2000138177A (en) | 1998-10-29 | 2000-05-16 | Sharp Corp | Manufacture for semiconductor device |
| US6596604B1 (en) * | 2002-07-22 | 2003-07-22 | Atmel Corporation | Method of preventing shift of alignment marks during rapid thermal processing |
| JP2007250705A (en) * | 2006-03-15 | 2007-09-27 | Nec Electronics Corp | Semiconductor integrated circuit device and method for arranging dummy pattern |
| JP2007311818A (en) * | 2007-07-18 | 2007-11-29 | Renesas Technology Corp | Semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103995A (en) * | 2009-12-21 | 2011-06-22 | 台湾积体电路制造股份有限公司 | Method for fabricating an integrated circuit device |
| CN102103995B (en) * | 2009-12-21 | 2013-02-06 | 台湾积体电路制造股份有限公司 | Method for fabricating an integrated circuit device |
| CN102403205A (en) * | 2010-09-08 | 2012-04-04 | 株式会社东芝 | Semiconductor device manufacturing method |
| CN111668329A (en) * | 2020-06-22 | 2020-09-15 | 三明学院 | Novel photoelectric detector |
| CN111668329B (en) * | 2020-06-22 | 2022-04-05 | 三明学院 | Photoelectric detector |
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| US8101974B2 (en) | 2012-01-24 |
| US20090146310A1 (en) | 2009-06-11 |
| JP5242145B2 (en) | 2013-07-24 |
| JP2009141075A (en) | 2009-06-25 |
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