TWI517360B - Dummy cell pattern for improving device thermal uniformity - Google Patents

Description

A redundant unit pattern that improves the thermal uniformity of components

The present invention relates to the field of semiconductor technology, and more particularly to a redundant cell pattern disposed between functional circuit blocks in a wafer to improve device thermal uniformity, and the present invention is particularly applicable to MOS transistors. The I _ON range makes a significant improvement.

In semiconductor processes, rapid thermal annealing steps are typically utilized to activate, diffuse, or re-crystalize the substrate structure. The aforementioned rapid thermal annealing step is generally performed in a halogen lamp or a laser heating device that directly irradiates radiation onto the surface of the wafer to rapidly change the temperature of the wafer. During the rapid thermal annealing step, different regions or different points within the wafer tend to have temperature deviations, mainly because the stacked materials at different locations are different, resulting in differences in heat absorption and heat dissipation characteristics.

As the size of semiconductor components shrinks, the above temperature deviations have a negative impact on component performance, particularly the electrical performance of components at different locations within the wafer. It is known that variations in the performance of components within a wafer are mainly due to temperature non-uniformity in the front-side anneal of the wafer and the wafer or crystal thereon. The aforementioned temperature deviations may be related to differences in the stacked materials and different pattern densities within the wafer.

In the semiconductor process, in order to avoid the shallow dish effect caused by the mechanical polishing process and to reduce the difference in the pattern density of the elements, a dummy pattern is usually disposed on the diffusion layer or the gate layer. For example, in the shallow trench insulation process, the active region is isolated by a trench structure filled with an insulating oxide. The formation of the insulating trench is first etched into the trench substrate, followed by a thick oxide layer. Then, it is planarized by, for example, a chemical mechanical polishing method or an etch back method.

It is known that the polishing rate or etch rate is related to the pattern density, that is, to the ratio of the area of the wafer occupied by the active region or the diffusion pattern. To ensure that the oxide layer on the wafer or substrate surface can be removed uniformly, it is desirable to have substantially the same pattern density across all areas of the wafer. The layout of the redundant pattern can achieve such an effect. After the redundant pattern is laid, the circuit areas and field areas on the semiconductor substrate will have near pattern density.

However, the layout of the redundant pattern in the past has caused the component performance deviation in the wafer to deteriorate. It is known that semiconductor wafers are composed of millions or more of transistors, and the uniformity of component performance of these transistors is very important for IC manufacturing. It can be seen that there is still a need in the industry for an improved method of homogenizing the performance of components within a wafer or reducing the temperature of the bias within the wafer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a redundant cell pattern disposed between functional circuit blocks within a wafer to improve component thermal uniformity, and in particular to provide significant improvements in the I _ON range between MOS transistors.

According to a preferred embodiment of the present invention, the present invention provides a redundant cell pattern for improving the thermal uniformity of a component, comprising a redundant diffusion pattern disposed in a predetermined area A; a shallow trench isolation region disposed in the predetermined region And surrounding the redundant diffusion pattern; at least one first redundant gate pattern is disposed on the redundant diffusion pattern, the two ends of which extend above the shallow trench isolation region, and the shallow trench isolation region The overlapping regions are C1 and C2; and a second redundant gate pattern is directly disposed on the shallow trench isolation region, and the overlapping region of the second redundant gate pattern and the shallow trench isolation region is C, Wherein the overlap regions C1 and C2, plus the overlap region C, the ratio of the predetermined region A is between 5% and 20%.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention.

In the following, the embodiments of the present invention are set forth, and the specific embodiments may be referred to the corresponding drawings, which form part of the embodiments. At the same time, by way of illustration, the manner in which the invention can be implemented is disclosed. In the following, the details of the embodiments will be clearly described, so that those skilled in the art can implement the invention. The specific embodiments may be practiced without departing from the spirit and scope of the invention, and the structural, logical, and electrical changes are still within the scope of the invention.

FIG. 1 is a schematic top plan view of an integrated circuit wafer 10. The integrated circuit chip 10 may include a plurality of functional circuit blocks 1-7, which may be, but are not limited to, a core circuit, a peripheral circuit, a logic circuit, an analog circuit memory circuit, and the like. Between the functional circuit blocks 1-7 is a non-circuit field area 8. As previously mentioned, a redundant pattern is typically placed in the diffusion region or gate layer in the field region 8 to avoid the shallow dish effect produced by the mechanical polishing process and to reduce the difference in component pattern density. However, the layout of the redundant pattern in the past has caused deterioration of component performance deviation in the wafer, particularly the I _ON range between the MOS transistors in the integrated circuit wafer 10. Hereinafter, the so-called "I _ON range" is defined as the maximum difference value of the on-current of the transistor in the wafer.

Still referring to Fig. 1, the applicant has verified through repeated experiments that after the rapid thermal annealing treatment, the on-current range between the transistors at different points or different positions of the integrated circuit wafer 10 is too large, for example, an arrow. 11 and 31 refer to the functional circuit blocks 1 and 3 respectively. For example, according to the experimental results, the turn-on current of the N-type MOSFET at the point indicated by the arrow 11 can be between 891.4 and 911.4 μA/μm, and the turn-on current of the N-type MOSFET at the point indicated by the arrow 31 can be Between 606.3.4~639.0μA/μm. Having such a large turn-on current range within the wafer has affected the operational performance of the component. The present invention then specifically proposes a solution.

2 is a schematic cross-sectional view of various redundant pattern aspects according to a preferred embodiment of the present invention. As shown in Figure 2, in order to evaluate and analyze the effects of various redundant pattern patterns on the performance of components in the wafer, especially for the I _ON range, the applicant divides the redundant pattern into four basic aspects. ~D. These four basic aspects A to D are formed on the semiconductor substrate 100. The basic pattern A of the redundancy pattern is defined as a first gate layer 120a, such as a polysilicon layer, covering the first diffusion redundancy pattern 100a, and an insulating layer 104 interposed between the first gate layer 120a and Between the first diffusion redundancy patterns 100a. The basic aspect B of the redundancy pattern is defined as a second diffusion redundancy pattern 100b that is not covered by any of the gate layers. The basic pattern C of the redundancy pattern is defined as a second gate layer 120b covering a first shallow trench isolation (STI) pattern 102a. The basic pattern D of the redundancy pattern is defined as a second shallow trench isolation pattern 102b that is not covered by any gate layer. In order to clarify the present invention, the basic patterns A to D of the aforementioned four kinds of redundant patterns can be classified as follows:

Basic Aspect A (or Mask A): The polysilicon 矽 redundant gate pattern is directly above the 矽-based redundant diffusion pattern.

Basic Aspect B (or Mask B): There is no polysilicon 矽 redundant gate pattern directly above the 矽-based redundant diffusion pattern.

Basic Aspect C (or Mask C): The polysilicon 矽 redundant gate pattern is directly on the STI.

Basic aspect D (or Mask D): There is no polysilicon 矽 redundant gate pattern on the STI.

Based on the results of the repeated experiments, the Applicant has found that the basic pattern C of the redundant pattern is basically the main cause of the excessive opening current range of the transistor elements in the wafer. In other words, the larger the ratio of the basic pattern C of the redundant pattern occupying the area of the wafer, the larger the range of the on-current of the transistor elements in the wafer. Applicants also conducted experiments on the reflectivity of the test wafer for the basic patterns A to D of the aforementioned four redundant patterns. The reflectance experiment was carried out in a rapid thermal annealing reaction chamber with an ellisometer lamp having a wavelength of about 810 nm as a heat source. The test wafers have the basic patterns A~D of the four kinds of redundant patterns described above, respectively, processed by a standard rapid thermal annealing program. As a result of the experiment, the reflectance of the basic pattern A of the above four kinds of redundant patterns is about 0.35, the reflectance of the basic state B is about 0.31, and the reflectance of the basic state C is about 0.61, and the reflection of the basic state D is The rate is approximately 0.29. The high reflectance (about 0.61) of the basic state C is not normal compared to the basic states A, B, and D (the average reflectance is about 0.32).

3 is a schematic view showing a redundant cell pattern capable of improving the thermal uniformity of components according to a preferred embodiment of the present invention. For convenience of explanation, only a three-column array pattern composed of a plurality of redundant cell patterns is illustrated in FIG. Those skilled in the art should be able to understand that a plurality of redundant unit patterns can also be combined into other patterns. As shown in FIG. 3, the redundancy unit pattern 200 of the present invention may be a rectangular region having a length L of between 0.5 μm and 2 μm and a width W of between 0.5 μm and 1.5 μm. Of course, those skilled in the art should be able to understand that the redundant unit pattern 200 of the present invention may also have other shapes, such as diamonds, triangles, polygons, and the like. The redundancy unit pattern 200 includes at least a redundant diffusion pattern 202 surrounded by a shallow trench isolation region 204. On the redundant diffusion pattern 202, at least one redundant gate pattern 212, such as a polysilicon pattern, which may be elongated and partially overlaps the redundant diffusion pattern 202, is provided. In addition, the redundancy unit pattern 200 further includes a redundant gate pattern 214, such as a polysilicon pattern, which may be elongated and disposed directly on the shallow trench isolation region 204, wherein the redundant gate pattern 214 does not The redundant diffusion patterns 202 overlap. According to a preferred embodiment of the present invention, the redundant gate pattern 212 and the redundant gate pattern 214 are arranged in parallel with each other. The redundant gate pattern 212 extends over the shallow trench isolation region 204 and the overlap region with the shallow trench isolation region 204 is C1 and C2. According to a preferred embodiment of the present invention, the redundant gate pattern 212 is shallow. The overlapping regions C1 and C2 of the trench insulating region 204, and the area of the overlapping region C of the redundant gate pattern 214 and the shallow trench insulating region 204 occupying the area A of the redundant cell pattern 200 are about 5% to 20%. . In addition, according to a preferred embodiment of the present invention, the three-column array pattern composed of the plurality of redundant cell patterns in FIG. 3 is an interlaced arrangement, in other words, the redundant cell pattern 200 of the first column R1 and the second column R2. The redundant cell patterns are not aligned in the same direction, and the redundant cell patterns of the second column R2 are not aligned in the same direction as the redundant cell patterns of the third column R3.

4 is a schematic view showing a redundant unit pattern capable of improving the thermal uniformity of components according to another preferred embodiment of the present invention. For convenience of description, only three columns consisting of a plurality of redundant unit patterns are illustrated in FIG. Array patterns, those skilled in the art should be able to understand that a plurality of redundant unit patterns can also be combined into other patterns. As shown in FIG. 4, the redundant unit pattern 300 of the present invention may be a rectangular region having a length L of between 0.5 μm and 2 μm and a width W of between 0.5 μm and 1.5 μm. Of course, those skilled in the art should be able to understand that the redundant unit pattern 300 of the present invention may also have other shapes, such as diamonds, triangles, polygons, and the like. The redundancy unit pattern 300 includes at least a redundant diffusion pattern 302 surrounded by a shallow trench isolation region 304. The redundant diffusion pattern 302 is provided with at least a first redundant gate pattern 312a and a second redundant gate pattern 312b, such as a polysilicon pattern, which may be elongated and partially overlapped with the redundant diffusion pattern 302. . In addition, the redundancy unit pattern 300 further includes a redundant gate pattern 314, such as a polysilicon pattern, which may be elongated and disposed directly on the shallow trench isolation region 304, wherein the redundant gate pattern 314 does not The redundant diffusion patterns 302 overlap. In accordance with a preferred embodiment of the present invention, the redundant gate patterns 312a, 312b and the redundant gate patterns 314 are arranged in parallel with each other. The redundant gate pattern 312a extends over the shallow trench isolation region 304, and the overlap region with the shallow trench isolation region 304 is C1 and C2, and the redundant gate pattern 312b extends over the shallow trench isolation region 304. And the overlapping areas with the shallow trench isolation regions 304 are C3 and C4. According to a preferred embodiment of the present invention, the overlapping regions C1 to C4, plus the overlap region C of the redundant gate pattern 314 and the shallow trench insulating region 304 The ratio of the area to the area A of the redundant unit pattern 300 is approximately 5% to 20%. In addition, according to a preferred embodiment of the present invention, the three-column array pattern composed of the plurality of redundant cell patterns in FIG. 4 is an aligned arrangement, in other words, the redundant cell pattern 300 of the first column R1 and the second column R2. The redundant cell patterns are aligned in the same direction, and the redundant cell pattern of the second column R2 is aligned in the same direction as the redundant cell pattern of the third column R3.

Please refer to FIG. 5, which illustrates a partial layout of a wafer according to another preferred embodiment of the present invention. As shown in FIG. 5, the wafer partial layout 400 includes a circuit component arrangement region P1 including at least a gate pattern 402, an active region pattern 404, and an auxiliary pattern 406 around the gate pattern 402. Surrounding the circuit component arrangement region P1 is a first field region P2 in which a plurality of redundant cell patterns 200 as shown in FIG. 3 are disposed, and the redundant cell patterns 200 may be arranged in an interlaced array. Surrounding the first field region P2 is a second field region P3 in which a plurality of redundant cell patterns 300 as shown in FIG. 4 are disposed, and the redundant cell patterns 300 can be arranged in an aligned array.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1~7. . . Functional circuit block

8. . . Field area

10. . . Integrated circuit chip

11. . . arrow

31. . . arrow

100. . . Semiconductor substrate

100a. . . First diffusion redundancy pattern

100b. . . Second diffusion redundancy pattern

102a. . . First shallow trench insulation pattern

102b. . . Second shallow trench insulation pattern

104. . . Insulation

120a. . . First gate layer

120b. . . Second gate layer

200. . . Redundant unit pattern

202. . . Redistributed diffusion pattern

204. . . Shallow trench insulation area

212. . . Redundant gate pattern

214. . . Redundant gate pattern

300. . . Redundant unit pattern

302. . . Redistributed diffusion pattern

304. . . Shallow trench insulation area

312a. . . Redundant gate pattern

312b. . . Redundant gate pattern

314. . . Redundant gate pattern

400. . . Partial layout of the wafer

402. . . Gate pattern

404. . . Active area pattern

406. . . Auxiliary pattern

L. . . Length of redundant unit pattern

W. . . Redundancy unit pattern width

C, C1 ~ C4. . . Overlapping area

R1. . . first row

R2. . . The second column

R3. . . Third column

P1. . . Circuit component configuration area

P2. . . First district

P3. . . Second field

The accompanying drawings, which are set forth in the claims of the claims In the picture:

FIG. 1 is a schematic top plan view of an integrated circuit chip.

2 is a schematic cross-sectional view of various redundant pattern aspects according to a preferred embodiment of the present invention.

Figure 3 is a schematic view showing a redundant unit pattern capable of improving the thermal uniformity of components in accordance with a preferred embodiment of the present invention.

Fig. 4 is a view showing a redundant unit pattern capable of improving the thermal uniformity of components according to another preferred embodiment of the present invention.

Fig. 5 is a view showing a partial layout of a wafer according to another preferred embodiment of the present invention.

200. . . Redundant unit pattern

202. . . Redistributed diffusion pattern

204. . . Shallow trench insulation area

212. . . Redundant gate pattern

214. . . Redundant gate pattern

L. . . Length of redundant unit pattern

W. . . Redundancy unit pattern width

C, C1 ~ C2. . . Overlapping area

R1. . . first row

R2. . . The second column

R3. . . Third column

Claims (13)

A redundant unit pattern for improving the thermal uniformity of a component, comprising: a redundant diffusion pattern disposed in a predetermined area A; a shallow trench isolation region disposed in the predetermined region A and surrounding the redundant diffusion a pattern of at least one first redundant gate pattern disposed on the redundant diffusion pattern, the two ends of which extend over the shallow trench isolation region, and the overlapping regions with the shallow trench isolation region are C1 and C2, respectively; And a second redundant gate pattern is disposed directly on the shallow trench isolation region, and an overlap region of the second redundant gate pattern and the shallow trench isolation region is C, wherein the overlap regions C1 and C2, The ratio of the overlapping area C to the predetermined area A is between 5% and 20%. The redundancy unit pattern for improving the thermal uniformity of the element according to claim 1, wherein the shape of the predetermined area A is selected from the group consisting of a rectangle, a diamond, a triangle, and a polygon. The redundancy unit pattern for improving the thermal uniformity of the component according to claim 1, wherein the first redundant gate pattern and the second redundant gate pattern are both elongated. The redundancy unit pattern for improving the thermal uniformity of an element according to claim 3, wherein the first redundant gate pattern and the second redundant gate pattern are parallel to each other arrangement. The redundancy unit pattern for improving the thermal uniformity of the component according to claim 1, wherein the first redundant gate pattern and the second redundant gate pattern are both polysilicon patterns. The redundancy unit pattern for improving the thermal uniformity of an element according to claim 1, wherein the second redundant gate pattern does not overlap the redundant diffusion pattern. A redundant unit pattern for improving the thermal uniformity of an element according to claim 1, wherein the predetermined area A is a rectangular area having a length L of between 0.5 μm and 2 μm and a width W of between 0.5 μm and 1.5. Mm. The redundant unit pattern for improving the thermal uniformity of the component according to claim 1, further comprising a third redundant gate pattern disposed on the first redundant gate pattern and the second redundant gate Between the pole patterns. The redundancy unit pattern for improving the thermal uniformity of the component according to claim 8, wherein the third redundant gate pattern is disposed on the redundant diffusion pattern, and both ends of the capacitor are extended to the shallow trench isolation region. The overlapping areas with the shallow trench isolation regions are C3 and C4, respectively. A redundant unit diagram for improving the thermal uniformity of an element as described in claim 9 The case where the overlapping areas C1 C C4 and the overlapping area C occupy the predetermined area A is about 5% to 20%. A redundancy pattern comprising: a plurality of redundant cell patterns as described in claim 1 of the patent application, wherein the redundant cell patterns are perpendicular to an extending direction of both ends of the first redundant gate pattern Arrange in a staggered array in the direction. A redundancy pattern comprising: a plurality of redundant cell patterns as described in claim 8 of the patent application, and the redundant cell patterns are arranged in an aligned array. A partial layout of a chip includes: a circuit component arrangement region including at least a gate pattern, an active region pattern, and an auxiliary pattern; a first field region surrounding the circuit component arrangement region, wherein a circuit region is disposed therein a first redundancy pattern, and the first redundancy pattern includes a plurality of redundant cell patterns arranged in an interlaced array; and a second field region surrounding the first field region and having a second portion disposed therein The redundancy pattern is included, and the second redundancy pattern includes a plurality of redundant cell patterns arranged in an aligned array.