CN101447512B - 具有抬高的源/漏区的mos器件 - Google Patents
具有抬高的源/漏区的mos器件 Download PDFInfo
- Publication number
- CN101447512B CN101447512B CN2008101792483A CN200810179248A CN101447512B CN 101447512 B CN101447512 B CN 101447512B CN 2008101792483 A CN2008101792483 A CN 2008101792483A CN 200810179248 A CN200810179248 A CN 200810179248A CN 101447512 B CN101447512 B CN 101447512B
- Authority
- CN
- China
- Prior art keywords
- silicide area
- gate electrode
- gate dielectric
- semiconductor substrate
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 48
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 61
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 48
- 239000010703 silicon Substances 0.000 claims description 48
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- 238000000034 method Methods 0.000 abstract description 25
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 238000000137 annealing Methods 0.000 abstract description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 abstract 2
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 12
- 239000012535 impurity Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 125000001475 halogen functional group Chemical group 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- CVOFKRWYWCSDMA-UHFFFAOYSA-N 2-chloro-n-(2,6-diethylphenyl)-n-(methoxymethyl)acetamide;2,6-dinitro-n,n-dipropyl-4-(trifluoromethyl)aniline Chemical compound CCC1=CC=CC(CC)=C1N(COC)C(=O)CCl.CCCN(CCC)C1=C([N+]([O-])=O)C=C(C(F)(F)F)C=C1[N+]([O-])=O CVOFKRWYWCSDMA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 229910021386 carbon form Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000010813 municipal solid waste Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052704 radon Inorganic materials 0.000 description 1
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一种形成半导体器件的方法，包括：提供半导体衬底；在半导体衬底之上形成栅电介质；在栅电介质上形成栅电极；在栅电介质和栅电极的侧壁上形成薄衬垫；形成邻近薄衬垫的碳化硅(SiC)区；形成包括至少一部分碳化硅区的深源/漏区；覆盖形成金属层，其中介于金属层和深源/漏之间的第一界面高于介于栅电介质和半导体衬底之间的第二界面；对半导体器件进行退火以形成硅化物区。优选地，硅化物区内边缘和栅电极对应边缘之间的水平间距优选为小于大约150。
Description
技术领域
本发明一般地涉及半导体器件，特别涉及具有抬高的源和漏区的金属氧化物半导体(MOS)器件。
背景技术
半导体器件(如金属氧化物半导体器件)的尺寸的减小和固有特性使得集成电路在速度、性能、密度和每单位功能成本在过去的几十年中持续改进。
为了提高MOS器件的性能，可以在MOS管的沟道区引入应力来改进载流子迁移率。一般地，期望在n型金属氧化物半导体(NMOS)器件的沟道区引入从源到漏方向的张应力，在p型金属氧化物半导体(PMOS)器件的沟道区引入从源到漏方向的压应力。
对NMOS器件的沟道区加入张应力通常采用两种方法。一个方法是通过在源和漏区注入碳以形成SiC应力结构。另一个方法是在源和漏区上外延生长SiC应力结构。这样的方法通常包括以下步骤：在半导体衬底上形成栅叠层，在栅叠层的侧壁形成栅衬垫，在硅衬底内对准栅衬垫形成凹槽，以及在凹槽中外延生长SiC应力结构。SiC的晶格常数小于硅，因此对沟道区施加张应力，该沟道区位于源SiC应力结构和漏SiC应力结构之间。
已经发现这两种方法都无益于改进源/漏电阻RSD。由外延生长SiC形成的源/漏区与由向硅衬底注入n型杂质形成的源/漏区具有相当的电阻RSD。由注入碳形成的源/漏区的电阻RSD可能甚至比没有注入碳形成的源/漏区的电阻RSD还要大。
众所周知，源/漏电阻RSD对于驱动电流发挥重要作用。随着集成电路的规模扩大，源/漏电阻RSD相对于沟道电阻RCH逐渐增大。由于器件驱动电流与总电阻(RSD+RCH)成反比，所以驱动电流的增大至少部分地由源/漏电阻RSD的减小造成。当工艺发展到65nm及以后，对沟道施加应力以增大器件驱动电流的有益作用很小以至于该有益作用将不再值得引入产生应力的工艺的复杂度，且可以预计对于45nm及以下的工艺，源/漏电阻RSD将远远超过沟道电阻RCH。对于45nm以后的工艺，源/漏电阻RSD成为进一步改进器件性能的瓶颈。因而需要可以克服前面讨论的缺陷的半导体器件。
发明内容
根据本发明的一个方面，一种形成半导体器件的方法，包括：提供半导体衬底；在半导体衬底之上形成栅电介质；在栅电介质之上形成栅电极；在栅电介质和栅电极的侧壁上形成薄衬垫；邻近薄衬垫形成碳化硅(SiC)区；形成包括至少一部分碳化硅区的深源/漏区；覆盖形成金属层，其中位于金属层和深源/漏之间的第一界面高于位于栅电介质和半导体衬底之间的第二界面；以及对半导体器件退火以形成硅化物区。
根据本发明的另一个方面，一种形成半导体器件的方法，包括：提供半导体衬底；在半导体衬底之上形成栅电介质；在栅电介质之上形成栅电极；在栅电介质和栅电极的侧壁上形成伪薄衬垫；在半导体衬底内沿伪薄衬垫的侧壁形成凹槽；在凹槽内外延生长碳化硅(SiC)区，其中SiC区具有不高于栅电介质和半导体衬底之间的界面的顶面；在SiC区上选择性的形成硅层，其中硅层具有高于上述界面的顶面；去除伪薄衬垫；通过注入硅层形成轻掺杂源/漏(LDD)区；在栅电介质和栅电极的侧壁上形成薄衬垫；在薄衬垫的侧壁上形成伪衬垫；形成包括至少一部分碳化硅区的深源/漏区；去除伪衬垫；以及在SiC区之上形成硅化物区。
根据本发明的又一个方面，一种形成半导体器件的方法，包括：提供半导体衬底；在半导体衬底之上形成栅电介质；在栅电介质之上形成栅电极；在栅电介质和栅电极的侧壁上形成伪薄衬垫；在半导体衬底内沿伪薄衬垫的侧壁形成凹槽；在凹槽中外延生长碳化硅(SiC)区，其中SiC区具有高于栅电介质和半导体衬底之间的界面的顶面；去除伪薄衬垫；通过注入SiC区形成轻掺杂源/漏(LDD)区；在栅电介质和栅电极的侧壁上形成薄衬垫；在薄衬垫的侧壁上形成伪衬垫；形成包括至少一部分SiC区的深源/漏区；去除伪衬垫；以及在SiC区上形成硅化物区。
根据本发明的又一个方面，一种半导体器件，包括：半导体衬底；位于半导体衬底之上的栅电介质；位于栅电介质之上的栅电极；邻近栅电介质并且具有至少一部分在半导体衬底内的SiC区；包括至少一部分SiC区的深源/漏区；以及位于深源/漏区之上的硅化物区，其中硅化物区的内边缘比深源/漏区更接近栅电极。硅化物区的内边缘和栅电极的对应边缘之间的水平间距优选为小于大约
。
根据本发明的又一个方面，一种半导体结构，包括：半导体衬底；位于半导体衬底之上的栅电介质；位于栅电介质之上的栅电极；位于栅电极的侧壁上的薄衬垫；在半导体衬底内并邻近栅电极的SiC应力结构；以及硅化物区，其内边缘基本对准薄衬垫的外边缘，其中硅化物具有基本高于半导体衬底的顶面的底面。硅化物区的内边缘和栅电极的对应边缘之间的水平间距优选为小于大约
。
根据本发明的又一个方面，一种半导体结构，包括：半导体衬底；位于半导体衬底之上的栅电介质；位于栅电介质之上的栅电极；邻近栅电介质并且具有至少一部分在半导体衬底内的碳化硅(SiC)区；深源/漏区；以及位于半导体衬底之上的硅化物区。其中硅化物区内边缘与栅电极的对应边缘之间的水平间距小于大约。
根据本发明的又一个方面，一种半导体结构，包括：半导体衬底，包括埋层氧化层；位于半导体衬底之上的栅电介质；位于栅电介质之上的栅电极；邻近栅电介质并且具有至少一部分在半导体衬底内的碳化硅(SiC)区；包括至少一部分SiC区的深源/漏区，其中深源/漏区和SiC区位于埋层氧化层之上；以及位于深源/漏区之上的硅化物区。其中硅化物区的内边缘和栅电极的对应边缘之间的水平间距小于大约。
本发明的有益效果包括增加了驱动电流和减少了MOS器件的泄漏电流。
附图说明
下面结合附图进行描述，以便更完整地理解本发明及其附加优点，其中：
图1到9A为制造n型金属氧化物半导体(MOS)的中间过程的剖面图；以及
图9B到9D示出了本发明的可选的实施方式。
具体实施方式
以下详述目前优选实施方式的制造和利用。然而，可以理解的是，本发明提供了许多可应用的发明概念，这些概念可广泛地实施于各种特定情况。所讨论的这些具体实施方式仅以具体方式说明本发明的制造和利用，并非用以限制本发明的范围。
本发明提供了一种改进金属氧化物半导体器件的驱动电流并且不增加泄漏电流的新方法。这里示出了本发明的实施例的制造的中间过程。在本发明的所有附图和说明性的实施例中，相同的序号用于标识相同的元件。
参考图1，具有衬底20。在一个实施例中，衬底20由体硅形成。在可选的实施例中，衬底20具有绝缘体上硅(SOI)结构(请参考图9D)。在又一个实施例中，衬底20包括应变硅，其可以非应变或应变地形成在硅锗层上(请参考图9C)。在又一个实施例中，衬底20具有应变绝缘体上硅(SSOI)结构。
浅沟槽隔离(STI)区22形成在衬底20内以隔离器件区域。本领域所知，STI区22可以由刻蚀衬底20以形成凹槽，然后用介质材料填充凹槽而形成。
图2示出了一种栅叠层，包括衬底20上的栅电介质24和栅电极26。栅电介质24优选包括常用的电介质材料如氧化物、氮化物、氧氮化物、高k值材料及其组合物，及其多层。栅电极26可以由多晶硅形成，可以在沉积的时候将杂质掺杂进去，以改进传导性。可选择的，栅电极26由其他常用的导电材料如金属、金属硅化物、金属氮化物及其组合物形成。栅电极26的宽度W优选为小于大约100nm，更优选为小于大约50nm。作为本领域公知技术，栅电介质24和栅电极26可以由在栅电介质层上堆叠栅电极层，然后对堆叠层进行构图而形成。
图3示出了伪薄(栅)衬垫28的形成。全文中，术语“薄衬垫”指厚度小于大约
的衬垫。更加优选的，薄衬垫的厚度介于大约
到大约
之间。伪薄衬垫28可以由单层形成，包括常用的衬垫材料如氮化硅、氮氧化硅、氧化硅、正硅酸乙酯(TEOS)氧化物及其组合物。可选择的，每个伪薄衬垫28为包括多于一层的复合层，例如在大约
的TEOS氧化物之上有大约
的氮化硅。作为本领域公知技术，伪薄衬垫28的形成可以包括形成衬垫层，然后对衬垫层进行构图以去除其水平部分。淀积可以由常用的技术如等离子体增强化学气相淀积(PECVD)、低压化学气相淀积(LPCVD)、次常压化学气相淀积(SACVD)等等来完成。
接下来，也如图3所示，凹槽32形成在衬底20内。优选的，凹槽32通过各向同性或者各向异性的刻蚀基本沿薄衬垫28的边缘形成。凹槽32的深度D1可以介于大约
到大约
之间，然而深度D1可以更大或者更小。在衬底20具有SOI结构的情况下，如图9D所示，薄硅晶种层需要留在凹槽32的底部埋层氧化层206上。
然后凹槽32被填充上以形成碳化硅(SiC)区34，如图4A所示，优选为通过SiC在凹槽32内选择性的外延生长(SEG)。可以在进行SEG过程的同时掺杂n型杂质，如砷。可选择的，在SEG过程中不掺杂n型杂质。在优选的实施例中，SiC区34中碳原子的百分比大于大约1％，更优选的，介于大约1％和大约3％之间。在一个实施例中，SiC区34具有基本与界面36水平的顶面，该界面36位于栅电介质24和其下的衬底20之间。在另一个实施例中，如图4B所示，SiC区34的顶面高于界面36，例如，以介于大约
到大约
之间的距离D2，这样SiC区34成为抬高的区域。在又一个实施例中，SiC区34的顶面低于界面36。
图5示出了硅层38的可选择的形成，例如，通过SEG。优选的，如果SiC区34的顶面与界面36水平或低于界面36，可以选择形成硅层38，且所形成的硅层38的顶面高于界面36。在一个示范性的实施例中，硅层38的顶面高于界面36一个垂直距离，该垂直距离与距离D2处于同样的范围内，如图4B所示，介于大约
到大约
之间。硅层38优选为包括基本纯的硅。有利地，硅层38在SiC区34上的工艺，比外延生长具有硅层38和SiC区34的组合厚度的SiC区34的工艺，耗费较少的工序和复杂度。这是由于外延生长SiC层比硅层更加困难，尤其是如果SiC层具有高碳浓度。另外，在随后进行的硅化工艺中，在硅层上形成硅化物是一项成熟的技术。
图6中，伪薄衬垫28被去除了，可选择的进行预非晶注入(PAI)来减小掺杂沟道效应，提高掺杂活化作用。在优选的实施例中，注入硅、锗和/或碳。在另一个实施例中，使用惰性气体，如氖、氩、氪、氙和氡。PAI阻止了随后掺杂的杂质流经晶体的晶格结构之间的空间并到达大于需要的深度。作为PAI的结果，暴露出的硅层38和/或SiC区34的至少顶部转变为非晶态。
图6还示出了pocked/halo(袋或环)区42的形成，优选为通过注入(如箭头所示)p型杂质，如硼和/或铟。注入可以是倾斜的。pocked/halo区42优选为围绕轻掺杂源/漏(LDD)和深源/漏的侧边缘和结形成，用于限制n型杂质的径向扩散。
轻掺杂源/漏(LDD)区44也形成，优选为通过注入n型杂质，如磷和/或砷。优选的，LDD注入的深度大于硅层38的深度以保证所有的硅层38都被注入。这将防止如果硅层38的底部在之后的硅化过程中没有被硅化，反向电阻会增大。形成pocked/halo区42和LDD区44的细节是本领域公知的，在此不再赘述。
图7示出了薄衬垫46和伪衬垫48的形成。薄衬垫46可以与伪薄衬垫28(参考图2)具有基本相同的厚度，当然衬垫46的厚度也可以大于或小于伪薄衬垫28的厚度。因此，薄衬垫46具有小于大约的厚度，更优选为介于大约
和大约
之间。伪衬垫48可以使用与形成薄衬垫46相类似的方法淀积形成。伪衬垫48的材料优选为不同于薄衬垫46的材料，这样在之后的去除伪衬垫48的步骤中，薄衬垫46可以基本保持完整。优选的，伪衬垫48具有介于大约
到大约
之间的厚度。在一个示范性的实施例中，伪衬垫48的厚度大于薄衬垫46。伪衬垫48将具有至少一部分，或者全部，在硅层38上或凸起的SiC区34上。
图8示出了深源/漏区50的形成，例如，通过注入n型杂质来完成。然后伪衬垫48被去除。伪衬垫48被去除之后，硅化物区52被形成，如图9所示。本领域所公知的，硅化物区52优选为通过覆盖沉积金属薄层，如镍、钴等等来形成。然后加热衬底，使硅与金属在接触面发生反应。反应之后，在硅和金属之间形成一层金属硅化物。没有发生反应的金属使用腐蚀金属但不腐蚀硅化物区52的刻蚀剂选择性的去除。
每个硅化物区52包括两个部分，部分521直接在各自的LDD区44上，部分522在各自的深源/漏区50上。由于深源/漏区50的高浓度，部分522和其下的深源/漏区50之间的接触为欧姆接触。部分521和其下的LDD区44(或硅层38的保留部分)之间由于LDD区44的低杂质浓度可能是肖特基接触，或者是欧姆接触。在说明书全文中，硅化物区52的各自的部分521指金属化源/漏区。
在优选的实施例中，硅层38或SiC区34高于界面36的部分被硅化过程完全消耗了。因此，每个硅化物区52都具有一个高于界面36的顶面，以及一个低于界面36的底面。在另一个实施例中，硅化过程只消耗硅层38的顶部，从而硅化过程之后保留了硅层38的较低部分，如图9B所示。因此，硅化物区52的底面高于界面36。在上述实施例中，硅化物区52仍然是抬高的因为它们比直接形成于衬底20上要高。
图9C和9D示出了本发明的另外的实施例，其中NMOS器件形成于不同类型的衬底上。图9C中，衬底20包括硅衬底201，部分松弛的锗硅(SiGe)层202，完全松弛的锗硅层203，以及二轴应变硅层204。由于硅层204和其下的层之间晶格失配，应变硅层204具有张应力。该张应力通过SiC区34的形成进一步加强。图9D示出了形成于已知的SSOI结构上的NMOS器件，包括半导体衬底205、埋层氧化层206以及应变硅层207。优选的，硅层207内的应力大于大约200MPa，然而更大的应力更佳。
本发明的实施例具有几项有益效果。首先，由于薄衬垫46和伪衬垫的形成，硅化物区52形成于靠近沟道区。这显著减小了源/漏电阻RSD。因此，改进了形成的NMOS器件的驱动电流。本发明的实施例对于65nm及以下工艺是特别有益的，在所述工艺中源/漏电阻RSD成为限制改善驱动电流的主要部分。其次，通过形成SiC区，改善了NMOS器件沟道区的载流子迁移率，从而改善了驱动电流。再次，通过形成外延硅层或者在高于界面36的顶面上形成SiC区来抬高硅化物区52，减小了泄露电流。
虽然本发明以及优点已经详细地被描述，但是，应该明白：在这里，能够进行各种各样的变化、置换和变更，而不会偏离由权利要求确定的本发明的精神和范围。另外，本申请的范围不是为了限定在说明书中所描述的工艺、器件、制造以及物质的构成、设备、方法和步骤的特定实施例。正如本领域技术人员能够容易从本发明的公开内容中理解的，根据本发明可以利用与这里所描述的相应实施方式发挥基本相同的功能或达到基本相同的结果的现有或以后开发的工艺、器件、制造以及物质的构成、设备、方法和步骤。因此，所附的权利要求在它们的范围内包括这些工艺、器件、制造以及物质的构成、设备、方法和步骤。
Claims (14)
1.一种半导体结构，包括：
半导体衬底；
位于所述半导体衬底之上的栅电介质；
位于所述栅电介质之上的栅电极；
邻近所述栅电介质并且具有至少一部分在所述半导体衬底内的碳化硅区；
深源/漏区；
位于所述半导体衬底之上的硅化物区，其中所述硅化物区内边缘与所述栅电极的对应边缘之间的水平间距小于；以及
位于硅化物区和碳化硅区之间的硅层，其中所述硅层具有比碳化硅区小的碳浓度。
2.根据权利要求1所述的半导体结构，进一步包括轻掺杂源/漏区，其内边缘比所述硅化物区的内边缘距离所述栅电极更近，其中所述硅化物区包括直接位于轻掺杂源/漏区上的第一部分，以及直接位于所述深源/漏区上的第二部分。
3.根据权利要求2所述的半导体结构，其中所述硅化物区与轻掺杂源/漏区具有肖特基接触。
4.根据权利要求1所述的半导体结构，其中所述硅化物区被薄衬垫从所述栅电介质和所述栅电极间隔开，所述薄衬垫具有在
到
之间的厚度。
5.根据权利要求1所述的半导体结构，其中所述碳化硅区具有介于百分之一到百分之四之间的碳原子百分比。
6.根据权利要求1所述的半导体结构，其中所述硅化物区具有比所述栅电介质的底面高的底面。
7.一种半导体结构，包括：
半导体衬底；
位于所述半导体衬底之上的栅电介质层；
位于所述栅电介质层之上的栅电极；
位于所述栅电极侧壁上的薄衬垫；
位于所述半导体衬底内并邻近所述栅电极的碳化硅应力结构；
硅化物区，其内边缘对准所述薄衬垫的外边缘，其中所述硅化物区的底面高于所述栅电介质层的底面，并且其中所述硅化物区的内边缘和所述栅电极的对应边缘之间的水平间距小于
；以及
位于所述碳化硅应力结构和所述硅化物区之间的外延硅层。
8.根据权利要求7所述的半导体结构，进一步包括深源/漏区，其中所述深源/漏区比所述硅化物区的内边缘被隔开得离所述栅电极更远。
9.根据权利要求7所述的半导体结构，其中所述薄衬垫具有小于
的厚度。
10.根据权利要求7所述的半导体结构，进一步包括轻掺杂源/漏区，其中所述轻掺杂源/漏区的内边缘对准所述栅电极的边缘。
11.根据权利要求7所述的半导体结构，其中所述硅化物区包括硅和碳，或者所述硅化物区包括硅，并且不含碳。
12.一种半导体结构，包括：
半导体衬底，所述半导体衬底包括埋层氧化层；
位于所述半导体衬底之上的栅电介质；
位于所述栅电介质之上的栅电极；
邻近所述栅电介质并且具有至少一部分在所述半导体衬底内的碳化硅区；
包括至少一部分上述碳化硅区的深源/漏区，其中所述深源/漏区和所述碳化硅区位于所述埋层氧化层之上；
位于所述深源/漏区之上的硅化物区，其中所述硅化物区的内边缘和所述栅电极的对应边缘之间的水平间距小于
；以及
位于所述碳化硅区和所述硅化物区之间的外延硅层。
13.根据权利要求12所述的半导体结构，其中直接位于所述栅电介质之下以及所述埋层氧化层之上的半导体区具有大于200MPa的应力。
14.根据权利要求12所述的半导体结构，其中所述硅化物区包括硅和碳，或者所述硅化物区包括硅，并且不含碳。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/948,823 US20090140351A1 (en) | 2007-11-30 | 2007-11-30 | MOS Devices Having Elevated Source/Drain Regions |
| US11/948,823 | 2007-11-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101447512A CN101447512A (zh) | 2009-06-03 |
| CN101447512B true CN101447512B (zh) | 2012-08-08 |
Family
ID=40674861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101792483A Active CN101447512B (zh) | 2007-11-30 | 2008-12-01 | 具有抬高的源/漏区的mos器件 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20090140351A1 (zh) |
| CN (1) | CN101447512B (zh) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090166625A1 (en) * | 2007-12-28 | 2009-07-02 | United Microelectronics Corp. | Mos device structure |
| WO2009131051A1 (ja) * | 2008-04-21 | 2009-10-29 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| KR20100087256A (ko) * | 2009-01-26 | 2010-08-04 | 인터내셔널 비지네스 머신즈 코포레이션 | 개선된 트랜지스터 소자 및 제조 방법 |
| US8216893B2 (en) * | 2009-01-26 | 2012-07-10 | International Business Machines Corporation | Stress enhanced transistor devices and methods of making |
| US8058134B2 (en) * | 2009-02-19 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Junction profile engineering using staged thermal annealing |
| KR101050405B1 (ko) * | 2009-07-03 | 2011-07-19 | 주식회사 하이닉스반도체 | 스트레인드채널을 갖는 반도체장치 제조 방법 |
| US8022488B2 (en) * | 2009-09-24 | 2011-09-20 | International Business Machines Corporation | High-performance FETs with embedded stressors |
| US8035141B2 (en) * | 2009-10-28 | 2011-10-11 | International Business Machines Corporation | Bi-layer nFET embedded stressor element and integration to enhance drive current |
| CN102194868B (zh) * | 2010-03-16 | 2013-08-07 | 北京大学 | 一种抗辐照的Halo结构MOS器件 |
| KR101714003B1 (ko) * | 2010-03-19 | 2017-03-09 | 삼성전자 주식회사 | 패시티드 반도체패턴을 갖는 반도체소자 형성방법 및 관련된 소자 |
| CN102637730B (zh) * | 2011-10-17 | 2015-06-24 | 上海华力微电子有限公司 | 基于埋层n型阱的异质结1t-dram结构及其形成方法 |
| CN103308772B (zh) * | 2012-03-16 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体检测电路及检测方法 |
| CN103779223B (zh) * | 2012-10-23 | 2016-07-06 | 中国科学院微电子研究所 | Mosfet的制造方法 |
| CN103871887B (zh) * | 2012-12-18 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管、nmos晶体管及其各自的制作方法 |
| CN104253090B (zh) * | 2013-06-26 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的形成方法 |
| CN105702723B (zh) * | 2014-11-27 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其形成方法 |
| US10784781B2 (en) * | 2017-11-29 | 2020-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor having asymmetric threshold voltage, buck converter and method of forming semiconductor device |
| TWI698912B (zh) * | 2018-09-03 | 2020-07-11 | 環球晶圓股份有限公司 | 磊晶基板及其製造方法 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6063681A (en) * | 1998-01-13 | 2000-05-16 | Lg Semicon Co., Ltd. | Silicide formation using two metalizations |
| US6921913B2 (en) * | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004538650A (ja) * | 2001-08-10 | 2004-12-24 | スピネカ セミコンダクター， インコーポレイテッド | 基板とのショットキーコンタクトを形成する高誘電率ゲート絶縁層、ソースおよびドレインを有するトランジスタ |
| US6974737B2 (en) * | 2002-05-16 | 2005-12-13 | Spinnaker Semiconductor, Inc. | Schottky barrier CMOS fabrication method |
| US6873017B2 (en) * | 2003-05-14 | 2005-03-29 | Fairchild Semiconductor Corporation | ESD protection for semiconductor products |
| US20050035369A1 (en) * | 2003-08-15 | 2005-02-17 | Chun-Chieh Lin | Structure and method of forming integrated circuits utilizing strained channel transistors |
| KR100546369B1 (ko) * | 2003-08-22 | 2006-01-26 | 삼성전자주식회사 | 콘택 마진을 확보할 수 있는 실리사이드막을 구비한고집적 반도체 소자 및 그 제조방법 |
| US7262087B2 (en) * | 2004-12-14 | 2007-08-28 | International Business Machines Corporation | Dual stressed SOI substrates |
| US7238580B2 (en) * | 2005-01-26 | 2007-07-03 | Freescale Semiconductor, Inc. | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration |
-
2007
- 2007-11-30 US US11/948,823 patent/US20090140351A1/en not_active Abandoned
-
2008
- 2008-12-01 CN CN2008101792483A patent/CN101447512B/zh active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6063681A (en) * | 1998-01-13 | 2000-05-16 | Lg Semicon Co., Ltd. | Silicide formation using two metalizations |
| US6921913B2 (en) * | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101447512A (zh) | 2009-06-03 |
| US20090140351A1 (en) | 2009-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101447512B (zh) | 具有抬高的源/漏区的mos器件 | |
| US7605407B2 (en) | Composite stressors with variable element atomic concentrations in MOS devices | |
| US7482211B2 (en) | Junction leakage reduction in SiGe process by implantation | |
| US8344447B2 (en) | Silicon layer for stopping dislocation propagation | |
| CN102931222B (zh) | 半导体器件及其制造方法 | |
| US7221006B2 (en) | GeSOI transistor with low junction current and low junction capacitance and method for making the same | |
| US8076189B2 (en) | Method of forming a semiconductor device and semiconductor device | |
| US7538387B2 (en) | Stack SiGe for short channel improvement | |
| US20070298557A1 (en) | Junction leakage reduction in SiGe process by tilt implantation | |
| US9478656B2 (en) | Method for fabricating a field effect transistor with local isolations on raised source/drain trench sidewalls | |
| US7504292B2 (en) | Short channel effect engineering in MOS device using epitaxially carbon-doped silicon | |
| US20080277735A1 (en) | MOS devices having elevated source/drain regions | |
| US8536619B2 (en) | Strained MOS device and methods for forming the same | |
| KR20070029711A (ko) | 트랜지스터 형성 방법 | |
| CN102906880A (zh) | 用于嵌入的源极/漏极硅化物的δ单层掺杂剂外延 | |
| US9209270B2 (en) | MOS devices having non-uniform stressor doping | |
| US8450171B2 (en) | Strained semiconductor device and method of making same | |
| CN106816467A (zh) | 半导体装置及其制造方法 | |
| US8642414B2 (en) | MOS transistor structure with in-situ doped source and drain and method for forming the same | |
| US20110306170A1 (en) | Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process | |
| CN101315886B (zh) | 半导体结构的形成方法 | |
| CN103794559A (zh) | 一种半导体器件及其制备方法 | |
| CN103811420A (zh) | 一种半导体器件的制备方法 | |
| US6900143B1 (en) | Strained silicon MOSFETs having improved thermal dissipation | |
| CN103367226A (zh) | 半导体器件制造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |