CN101446766A

CN101446766A - Exposure and alignment mark on silicon chip

Info

Publication number: CN101446766A
Application number: CNA2007100942879A
Authority: CN
Inventors: 陈华伦; 罗啸; 陈雄斌; 熊涛; 陈瑜
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-11-27
Filing date: 2007-11-27
Publication date: 2009-06-03

Abstract

The invention discloses an exposure and alignment mark on a silicon chip, used for searching and aligning before exposing, comprising linear bulges and grooves, and obviously characterized by the arrangement vertical to the cutting path of the silicon chip. On one hand, the alignment mark can have large spacing between mark lines; on the other hand, the mark lines can extend to the edge of the cutting path in the length direction, which effectively reduces the exposure and alignment error rate of the silicon chip when the cutting path of the silicon chip is reduced.

Description

Exposure alignment mark on the silicon chip

Technical field

The mark that is used for aiming at when the present invention relates to expose on a kind of silicon chip.

Background technology

In fabrication of semiconductor device, exposure is that special pattern is prepared essential on a silicon chip step.And in exposure process, need earlier the anterior layer on the silicon chip (being a lithography layer of front) to be done aligning.The method that has multiple exposure to aim at present, wherein a kind of is by seeking and identification is placed on (as using the Nikon photoetching equipment) that the mark of Cutting Road on the silicon chip (scribe line) lining is realized.Before doing accurate the aligning, rough relatively alignment procedures of one step is arranged usually, make search aim at (searchalignment), it is critical step very that this aims in step, because it is an accurate relatively alignment procedures after silicon chip being done coarse alignment, it can provide coordinate more accurately for the more accurate aligning in back.

The alignment mark that uses during search is aimed at is three lines that are parallel to Cutting Road on the silicon chip.Specifically in silicon chip, be three flash line or ditch line of rabbet joint (see figure 1)s that are parallel to Cutting Road on the silicon chip by preparing in etching on the silicon chip.When silicon chip being done search on time, sensor is collected the signal of these three lines, contrasts the setting in the exposure formula then, searches out the center of mark, further correction is done in the position of silicon chip, so that carry out next step more accurate aligning.

But when Cutting Road was more and more narrow, this alignment methods can run into bigger problem.Be exactly that distance between three lines can be more and more nearer, the value that is a, b, c and d among Fig. 1 can be more and more littler, and two lines of the most close silicon chip Cutting Road also must keep certain distance with silicon chip cut-off rule edge, so the marking signal that sensor detects can be very faint, and the signal of three lines is difficult to distinguish, so when Cutting Road was more and more narrow, the mode probability of errors that this search is aimed at can be than higher, what influence was produced normally carries out.

Summary of the invention

The technical problem to be solved in the present invention provides the exposure alignment mark on a kind of silicon chip, and the problem that error probability uprises is aimed in its search that can effectively avoid causing because of Cutting Road is more and more narrow.

For solving the problems of the technologies described above, the exposure alignment mark on the silicon chip of the present invention, the search alignment procedures before being used for exposing comprises wire projection or groove, wire projection or groove are perpendicular to that Cutting Road arranges.

Exposure alignment mark on the silicon chip of the present invention, spacing between the mark line can be provided with bigger on the one hand, and can be more not crowded because of dwindling of Cutting Road, cause the more weak bad identification of marking signal to be differentiated, mark line can extend to the edge of Cutting Road in the longitudinal direction always on the other hand, and need not resemble in the conventional tag must certain distance be arranged with the Cutting Road edge, so length is long enough still, be unlikely to cause weakening of signal, so reduced the probability that makes a mistake in the silicon wafer exposure aligning effectively.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is existing search alignment mark synoptic diagram;

Fig. 2 is a search alignment mark synoptic diagram of the present invention.

Embodiment

Exposure alignment mark on the silicon chip of the present invention makes traditional search mark (being wire projection or groove) that is parallel to the Cutting Road placement to place perpendicular to the Cutting Road direction into.Fig. 2 is specific embodiment of the present invention, wherein three wire projections that are arranged in parallel or groove vertical with the Cutting Road placement.Figure cathetus expressive notation is a whole piece projection or a groove, and the dotted line expressive notation is made up of the projection of a plurality of segments or groove.Such setting, search on the one hand spacing between the mark line can be provided with bigger, can only be shorter and do not cause searching for mark line because of dwindling of Cutting Road width, cause signal more weak and be unfavorable for that resolution discerns; The length direction of searching for mark line on the other hand can extend to the Cutting Road edge always, do not need to resemble tradition uses must with cut to the edge certain distance arranged, so length long enough still makes sensor can clearly detect the search mark line.So silicon wafer exposure alignment mark of the present invention under the situation that the spacing between the Cutting Road is constantly dwindled, still can have good signal and be identified ability, can reduce the probability that makes a mistake in the silicon wafer exposure search aligning effectively.

Claims

1, the exposure alignment mark on a kind of silicon chip, the search alignment procedures before being used for exposing, described exposure alignment mark comprises wire projection or groove, it is characterized in that: described wire projection or groove are arranged perpendicular to Cutting Road.