CN108803264B - Method for centralized placement of multiple alignment marks on wafer and determination of lithography position - Google Patents
Method for centralized placement of multiple alignment marks on wafer and determination of lithography position Download PDFInfo
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- CN108803264B CN108803264B CN201810588302.3A CN201810588302A CN108803264B CN 108803264 B CN108803264 B CN 108803264B CN 201810588302 A CN201810588302 A CN 201810588302A CN 108803264 B CN108803264 B CN 108803264B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
- G03F9/7023—Aligning or positioning in direction perpendicular to substrate surface
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
Abstract
The invention provides a method for determining the concentrated placement and photoetching positions of a plurality of alignment marks on a wafer, which comprises the following steps: providing a plurality of wafers with an alignment mark; establishing an exposure file to be executed in a photoetching machine; moving each wafer to an exposure stage of a lithography machine; calculating the deviation distance between the center of each wafer alignment signal and the coordinate position of a preset alignment mark; the maximum deviation distance between the center of an alignment signal and the coordinate position of a preset alignment mark in a plurality of wafers is taken as a reference, and when a plurality of alignment marks are intensively placed on the wafer, the distance between adjacent alignment marks is set according to the relation of the maximum deviation distance which is more than 2 times. The invention solves the problems of wrong position identification and wrong position alignment caused when a plurality of photoetching alignment marks are intensively placed on the wafer.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for intensively placing a plurality of photoetching alignment marks on a wafer and determining photoetching positions.
Background
In the field of semiconductor integrated circuit manufacturing technology, the greater the number of semiconductor devices manufactured on a single wafer, the greater the number of integrated circuit chips that can be obtained, and thus, the greater the benefit of the enterprise. How can more semiconductor devices be obtained on a wafer? There are generally two approaches: one is to directly increase the process capability, i.e., reduce the critical dimensions, which is the most efficient practice, but is also a more difficult practice because it requires the ability to increase the equipment, as well as the process development capability. And secondly, the design layout of the semiconductor device is optimized and improved, and more semiconductor devices can be obtained in unit area by combining the improvement of partial process capability. Both of these methods are indeed very effective methods, but are not done when equipment and process capacity reach limits. Many semiconductors have recently begun to reduce the width of the scribe lines, which has been greatly reduced from the first 100um to 80um, and the last 60um and 50um, in order to achieve a greater number of chips, i.e., to reduce the scribe lines between semiconductor devices. However, due to the size of the lithographic marks, the width of the scribe line has not been reduced further downward by the method unless the lithographic alignment marks are not placed on the scribe line. The lithography alignment mark mainly refers to an alignment mark disposed on a wafer, and is generally placed on a scribe line. If the lithographic alignment marks are not placed on the scribe line, they take up only a few of the original area where the semiconductor device was fabricated, and they are placed together in a concentrated manner to save space. However, since these lithographic alignment marks have high similarity regardless of shape and size, when they are densely packed together, the apparatus itself may select a wrong alignment mark to cause misalignment. Thereby causing a lithography position error.
For example: a NIKON lithography machine or the like has a coarse alignment mark (Search mark) and a fine alignment mark (GEA mark). Since the lithographic alignment between layers of a semiconductor device requires high precision, there is an alignment operation before the exposure of the lithography machine. When the wafer reaches the exposure stage, the alignment operation of the wafer is performed. The alignment process comprises the steps of firstly using Search mark to carry out coarse alignment, and then carrying out fine alignment by using EGA mark. FIG. 1 is a schematic diagram of a coarse alignment mark structure of a NIKON lithography machine. Fig. 2 is an alignment signal diagram corresponding to the coarse alignment mark in fig. 1. Referring to fig. 1 and 2, the coarse alignment mark 10 includes a plurality of mark points 11 distributed in a matrix. The coarse alignment mark 10 corresponds to an alignment signal 20, which includes three downward-recessed peak valid signals, as shown in the outer dashed box region in fig. 2, wherein the second recessed peak is the center 21 of the alignment signal 20, i.e., the center of the groove of the middle peak. That is, the fine alignment process is performed based on the coordinate position of the coarse alignment mark. Generally, the deviation between the position of the coarse alignment mark on the wafer and the preset alignment mark coordinate position 30 in the photolithography process is not too large, please refer to fig. 2, where the preset alignment mark coordinate position 30 required by the photolithography process is a circular dot position, and has a certain deviation from the alignment signal center 21. FIG. 3 is a diagram showing the relationship between the alignment signal corresponding to the alignment mark and the coordinate position of the preset alignment mark; referring to fig. 3, when the alignment signal 20 corresponding to the alignment mark deviates from the preset alignment mark coordinate position 30 by a large distance, the rough alignment fails, and the photolithography machine cannot operate normally.
The above is an alignment process with one alignment mark for a single wafer. When a single wafer has a plurality of alignment marks, and the alignment signal corresponding to one of the alignment marks is greatly deviated, if a group of identical or similar coarse alignment signals is left beside the wafer, the wafer may be easily misrecognized, thereby causing a wafer alignment failure or misalignment. FIG. 4 is a schematic diagram illustrating a structure of a single wafer with a plurality of alignment marks spaced apart from each other, and FIG. 5 is a diagram illustrating a relationship between a plurality of alignment signals corresponding to the plurality of alignment marks and a coordinate position of a predetermined alignment mark; referring to fig. 4 and 5, when two adjacent alignment marks of the plurality of alignment marks are densely disposed, the distance between the two adjacent alignment marks is L, and the alignment mark 002 is the actually required lithography alignment position, but because the wafer has a certain position deviation when reaching the exposure stage of the lithography machine, and the preset alignment mark coordinate position 30 during the rough alignment is closer to the alignment signal 40 corresponding to the wrong alignment mark 001, the lithography machine erroneously recognizes that the alignment mark 001 corresponding to the alignment signal 40 closer to the preset alignment mark coordinate position 30 is the rough alignment coordinate position when the alignment signal 50 corresponding to the actually required alignment mark 002 is caused, and thus, the lithography machine generates the wrong alignment of the lithography position.
Disclosure of Invention
The present invention provides a method for collectively placing a plurality of alignment marks on a wafer and determining a lithography position, so as to solve the problems of incorrect position identification and incorrect position alignment caused when the plurality of alignment marks are collectively placed on the wafer.
In order to solve the above technical problem, the present invention provides a method for collectively placing a plurality of alignment marks on a wafer, comprising the steps of:
providing a plurality of wafers with an alignment mark;
establishing an exposure file to be executed in a photoetching machine;
moving each wafer to an exposure platform of a photoetching machine according to the preset alignment mark coordinate position of the wafer in the exposure file;
the photoetching machine generates corresponding alignment signals according to the alignment marks of each wafer;
calculating the deviation distance between the center of each wafer alignment signal and the coordinate position of a preset alignment mark;
the maximum deviation distance between the center of an alignment signal and the coordinate position of a preset alignment mark in a plurality of wafers is taken as a reference, and when a plurality of alignment marks are intensively placed on the wafer, the distance between adjacent alignment marks is set according to the relation of the maximum deviation distance which is more than 2 times.
Further, the method for collectively placing the plurality of alignment marks on the wafer provided by the invention repeatedly calculates the deviation distance between the center of the alignment signal of each wafer and the coordinate position of the preset alignment mark, and sets the distance between the adjacent alignment marks according to the maximum deviation distance which is more than 2 times when the plurality of alignment marks on the wafer are collectively placed by taking the maximum deviation distance between the center of the alignment signal and the coordinate position of the preset alignment mark in multiple calculations as a reference.
Further, according to the centralized placement method of the plurality of alignment marks on the wafer, provided by the invention, when the maximum deviation distance is less than 80 micrometers, the calculation is carried out according to the custom deviation distance above 80 micrometers.
Furthermore, in the centralized placement method of multiple alignment marks on a wafer provided by the invention, the multiple wafers with one alignment mark refer to more than two wafers with the same pattern, and only one alignment mark is arranged in a certain distance range.
Further, the present invention provides a method for collectively placing a plurality of alignment marks on a wafer, wherein the distance range is greater than or equal to 500 μm.
Furthermore, the present invention provides a method for collectively placing a plurality of alignment marks on a wafer, wherein the plurality of alignment marks on the wafer refer to a wafer having more than two alignment marks.
Further, according to the method for collectively placing the plurality of alignment marks on the wafer, provided by the invention, the alignment marks are rough alignment marks in a photoetching process.
In order to solve the above technical problem, the present invention further provides a method for determining the lithography positions of a plurality of alignment marks on a wafer, wherein according to the method for collectively placing a plurality of alignment marks on a wafer, the positions of adjacent alignment marks are set, a new exposure file is executed, the wafer is moved to an exposure stage, a lithography machine automatically collects a plurality of alignment signals of the wafer, and automatically identifies the lithography position of the exposure file to be currently executed by the wafer, which is corresponding to the center of the alignment signal close to the coordinate position of the preset alignment mark.
Further, according to the method for determining the lithography positions of the plurality of alignment marks on the wafer, the step of automatically identifying the lithography position of the exposure file to be executed on the wafer corresponding to the alignment mark close to the preset alignment mark coordinate position is a rough alignment process, and then a fine alignment process is executed.
Furthermore, according to the method for determining the photoetching positions of the alignment marks on the wafer, provided by the invention, after the fine alignment process is executed, the exposure process is executed according to the exposure file to be executed.
Compared with the prior art, the invention provides a method for intensively placing a plurality of alignment marks on a wafer and a method for determining a photoetching position, which are implemented by executing the same exposure file on a plurality of wafers with only one alignment mark, calculating the deviation distance between the preset alignment mark coordinate position in the exposure file and an alignment signal generated by each wafer alignment mark, finding out the maximum deviation distance in the wafer, then setting the spacing position between adjacent alignment marks in the plurality of alignment marks on the wafer by taking the maximum deviation distance as a reference, namely setting the spacing between the adjacent alignment marks according to the relationship of the maximum deviation distance larger than 2 times instead of the centralized setting of any spacing, and reflecting the physical position relationship between the adjacent alignment signals, wherein the spacing between the two alignment signals is also larger than 2 times, and when the alignment signals corresponding to the alignment marks of the exposure file to be executed in the wafer with the plurality of alignment marks and the alignment signals corresponding to the alignment marks are intensively set in any spacing When the coordinate position of the preset alignment mark generates deviation, because the deviation distance is less than or equal to the maximum deviation distance, and the distance between the other group of alignment signals and the coordinate position of the preset alignment mark is greater than the maximum deviation distance, so that the adjacent alignment marks form a relation greater than 2 times, the generated deviation alignment signal is still nearest to the coordinate position of the preset alignment mark, and therefore, the alignment mark corresponding to the alignment signal close to the coordinate position of the preset alignment mark can be accurately determined as the photoetching position of the exposure file to be executed currently on the wafer. Therefore, the invention solves the problems of wrong position identification and wrong position alignment caused when a plurality of alignment marks are intensively arranged on the wafer.
Drawings
FIG. 1 is a schematic structural diagram of a coarse alignment mark of a lithography machine;
FIG. 2 is a waveform diagram of an alignment signal corresponding to the coarse alignment mark of FIG. 1;
FIG. 3 is a waveform diagram of a relationship between a coordinate position deviation of an alignment signal corresponding to a single coarse alignment mark and a preset alignment mark;
FIG. 4 is a schematic diagram of a structure of a plurality of adjacent alignment marks on a wafer;
FIG. 5 is a waveform diagram illustrating the relationship between the adjacent alignment signals corresponding to a plurality of alignment marks and the coordinate positions of the predetermined alignment marks;
FIG. 6 is a waveform diagram of the maximum deviation distance between the coordinate positions of a single alignment mark and a preset alignment mark;
FIG. 7 is a schematic diagram of a structure of the present invention in which adjacent alignment marks are collectively placed;
FIG. 8 is a waveform diagram of alignment signals corresponding to adjacent alignment marks and coordinates of a predetermined alignment mark according to the present invention;
FIG. 9 is a flowchart illustrating a method for collectively placing a plurality of alignment marks on a wafer according to an embodiment of the invention.
FIG. 10 is a flowchart of a method for determining lithographic positions of a plurality of alignment marks on a wafer according to an embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
referring to fig. 9, an embodiment of the present invention provides a method for collectively placing a plurality of alignment marks on a wafer, including:
in step 801, a plurality of wafers having an alignment mark are provided. The alignment mark refers to a lithography alignment mark.
In step 804, the photolithography machine generates a corresponding alignment signal according to the alignment mark of each wafer.
In order to further increase reliability and accuracy, the embodiment of the invention can repeatedly calculate the deviation distance between the center of the alignment signal of each wafer and the coordinate position of the preset alignment mark, and when a plurality of alignment marks are intensively placed on the wafer, the distance between the adjacent alignment marks is set according to the maximum deviation distance which is more than 2 times by taking the maximum deviation distance between the center of the alignment signal and the coordinate position of the preset alignment mark in multiple calculations as a reference. That is, the alignment signal of each wafer is collected several times to find the time with the largest deviation distance.
As a preferred implementation manner, in the method for collectively placing a plurality of alignment marks on a wafer according to the embodiments of the present invention, the plurality of wafers having one alignment mark refer to more than two wafers having the same pattern, and only one alignment mark is located within a certain distance range. For example, two, three, four, five, etc. I.e., more than two sheets including the same number. The more the quantity, the more accurate the reliability, and the higher the credibility. And when the maximum deviation distance is less than 80 micrometers, the deviation distance is customized according to the deviation distance of more than 80 micrometers. When the deviation distances are all smaller than 80 microns, the maximum deviation distance can be calculated according to custom deviation distances such as 80 microns, 90 microns, 100 microns and 120 microns. That is, when the maximum deviation distance is less than 80 micrometers, the maximum deviation distance is calculated as greater than or equal to 80 micrometers.
As a preferred implementation manner, in the method for collectively placing a plurality of alignment marks on a wafer according to the embodiments of the present invention, the plurality of wafers having one alignment mark refer to more than two wafers having the same pattern, and only one alignment mark is located within a certain distance range. The distance range is greater than or equal to 500 micrometers.
In a preferred embodiment, the present invention provides a method for collectively placing a plurality of alignment marks on a wafer, where the plurality of alignment marks on the wafer include more than two alignment marks. Including but not limited to two alignment marks, which may be three, four, five, etc. It is only necessary to satisfy the above-described setting relationship of the adjacent alignment marks. That is, more than two include the present number.
In the embodiment of the invention, the alignment mark is a coarse alignment mark in a photoetching process. Referring to fig. 8, in the method for collectively placing a plurality of alignment marks on a wafer according to the embodiment of the present invention, the alignment signals are odd waveform signals. The standard for the alignment signal is three waveform signals. As indicated by the dashed boxes of alignment signal 411 and alignment signal 412, respectively, represent a set of alignment signals.
As a preferred implementation manner, in the method for collectively placing a plurality of alignment marks on a wafer according to the embodiments of the present invention, the center of the alignment signal is a waveform signal located at the center of odd number of waveform signals. Referring to FIG. 8, the two sets of alignment signals 411 and 412 have a waveform signal sinking downward in the middle of the alignment signals.
Referring to fig. 6 and 8, in the method for collectively placing a plurality of alignment marks on a wafer according to an embodiment of the present invention, the alignment signals are concave spike-shaped signals.
As a preferred implementation manner, the embodiment of the present invention provides a method for collectively placing a plurality of alignment marks on a wafer, where the alignment marks are coarse alignment marks in a lithography apparatus.
As a preferred implementation manner, in the method for collectively placing a plurality of alignment marks on a wafer according to the embodiment of the present invention, a lithography apparatus used in a lithography process is a lithography machine having a coarse alignment mark and a fine alignment mark. For example: nikon lithography machine.
Referring to fig. 10, an embodiment of the present invention further provides a method for determining photolithography positions of a plurality of alignment marks on a wafer, where positions of adjacent alignment marks are set according to the method for collectively placing a plurality of alignment marks on a wafer, a new exposure file is executed, the wafer moves to an exposure stage, a photolithography machine automatically collects a plurality of alignment signals of the wafer, and automatically identifies a photolithography position of an exposure file to be executed by the wafer, where the alignment mark corresponding to a center of the alignment signal near a coordinate position of a preset alignment mark is located. The method comprises the following specific steps:
At step 904, the photolithography machine generates a corresponding alignment signal according to the alignment mark of each wafer.
In step 907, the photolithography machine generates a plurality of alignment signals according to the plurality of alignment marks of the single wafer.
in step 909, the lithography machine automatically identifies and determines the lithography position of the exposure file to be executed currently on the wafer corresponding to the alignment signal center close to the preset alignment mark coordinate position. Referring to fig. 8, after the predetermined alignment mark coordinate position of the wafer is 300, the alignment signal corresponding to the alignment mark 401 is 411, the alignment mark corresponding to the alignment mark 402 is 412, and the distance between adjacent alignment marks is set to be greater than 2 times, since the deviation distance between the alignment signal 411 and the predetermined alignment mark coordinate position 300 is smaller than or equal to the maximum deviation distance, i.e., L1 is smaller than or equal to a, and the deviation distance between the alignment signal 412 and the predetermined alignment mark coordinate position 300 is greater than the maximum deviation distance, i.e., L2> a, the alignment signal 411 always approaches the predetermined alignment mark coordinate position 300, so as to determine the alignment mark 401 corresponding to the alignment signal 411 as the lithography position corresponding to the exposure file to be executed.
As a preferred implementation manner, in the method for determining the lithography positions of the plurality of alignment marks on the wafer according to the embodiment of the present invention, the step of automatically identifying the lithography position of the alignment mark corresponding to the center of the alignment signal close to the coordinate position of the preset alignment mark is a rough alignment process, and then a fine alignment process is performed.
As a preferred embodiment, in the method for determining the lithography positions of the plurality of alignment marks on the wafer according to the embodiment of the present invention, after the fine alignment process is performed, an exposure process is performed according to an exposure file to be performed.
The invention provides a method for determining the centralized rotation and photoetching positions of a plurality of alignment marks on a wafer, which is characterized in that the same exposure file is executed for a plurality of wafers with only one alignment mark, the deviation distance between the preset alignment mark coordinate position in the exposure file and an alignment signal generated by each wafer alignment mark is calculated, the maximum deviation distance in the wafer is found, then the maximum deviation distance is taken as the reference, the distance position between adjacent alignment marks in the plurality of alignment marks on the wafer is set, namely the distance between the adjacent alignment marks is set according to the relation of the maximum deviation distance larger than 2 times, but not the centralized setting of any distance, the physical position relation of the adjacent alignment marks is reflected, when the corresponding adjacent alignment signals are reflected, the distance between the two alignment signals is also larger than 2 times, and when the alignment signals corresponding to the alignment marks of the exposure file to be executed in the wafer with the plurality of alignment marks are located with the preset alignment marks When the mark position deviates, because the deviation distance is less than or equal to the maximum deviation distance, and the distance between the other group of alignment signals and the preset alignment mark coordinate position is greater than the maximum deviation distance, so that the adjacent alignment marks form a relationship greater than 2 times, the deviated alignment signals are still nearest to the preset alignment mark coordinate position, and therefore, the alignment mark corresponding to the alignment signal close to the preset alignment mark coordinate position can be accurately determined as the photoetching position of the exposure file to be executed currently on the wafer. Therefore, the invention solves the problems of wrong position identification and wrong position alignment caused when a plurality of alignment marks are intensively arranged on the wafer.
The present invention is not limited to the above-described embodiments, and various changes and modifications within the scope of the present invention are within the scope of the present invention.
Claims (10)
1. A method for collectively placing a plurality of alignment marks on a wafer is characterized by comprising the following steps:
providing a plurality of wafers with an alignment mark;
establishing an exposure file to be executed in a photoetching machine;
moving each wafer to an exposure platform of a photoetching machine according to the preset alignment mark coordinate position of the wafer in the exposure file;
the photoetching machine generates corresponding alignment signals according to the alignment marks of each wafer;
calculating the deviation distance between the center of each wafer alignment signal and the coordinate position of a preset alignment mark;
the maximum deviation distance between the center of an alignment signal and the coordinate position of a preset alignment mark in a plurality of wafers is taken as a reference, and when a plurality of alignment marks are intensively placed on the wafer, the distance between adjacent alignment marks is set according to the relation of the maximum deviation distance which is more than 2 times.
2. The method as claimed in claim 1, wherein the deviation distance between the center of the alignment signal of each wafer and the coordinate position of the predetermined alignment mark is repeatedly calculated, and the distance between the adjacent alignment marks is set according to the maximum deviation distance greater than 2 times when the alignment marks are centrally placed on the wafer, based on the maximum deviation distance between the center of the alignment signal and the coordinate position of the predetermined alignment mark in the multiple calculations.
3. The method as claimed in claim 2, wherein the maximum deviation distance is less than 80 μm, and the method is calculated according to a custom deviation distance greater than 80 μm.
4. The method as claimed in claim 1, wherein the plurality of wafers having one alignment mark are two or more wafers having the same pattern and only one alignment mark is located within a certain distance.
5. The method of claim 4, wherein the distance range is greater than or equal to 500 μm.
6. The method as claimed in claim 1, wherein the alignment marks are more than two on the wafer.
7. The method of claim 1, wherein the alignment mark is a coarse alignment mark in a photolithography process.
8. A method for determining the lithography position of multiple alignment marks on a wafer, according to any one of claims 1 to 7, wherein the method for collectively placing multiple alignment marks on a wafer sets the position of adjacent alignment marks, executes a new exposure file, moves the wafer to an exposure stage, automatically collects multiple alignment signals of the wafer by a lithography machine, and automatically identifies the lithography position of the exposure file to be currently executed by the wafer corresponding to the alignment signal center close to the preset alignment mark coordinate position.
9. The method as claimed in claim 8, wherein the step of automatically identifying the lithography position of the alignment mark corresponding to the center of the alignment signal close to the coordinate position of the predetermined alignment mark is a rough alignment process, and then a fine alignment process is performed.
10. The method of claim 9, wherein after performing the fine alignment process, performing an exposure process according to an exposure file to be performed.
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| CN109633209A (en) * | 2019-01-31 | 2019-04-16 | 长江存储科技有限责任公司 | Test sample and preparation method thereof |
| CN112269304B (en) * | 2020-12-28 | 2021-04-27 | 晶芯成(北京)科技有限公司 | Method and system for determining exposure position |
| CN114326337B (en) * | 2021-12-24 | 2023-07-28 | 粤芯半导体技术股份有限公司 | Photoetching alignment method |
| CN114038776B (en) * | 2022-01-11 | 2022-06-03 | 广州粤芯半导体技术有限公司 | Method for solving alignment deviation caused by wafer warping deformation |
| CN117492336B (en) * | 2024-01-02 | 2024-04-09 | 天府兴隆湖实验室 | Alignment mark and pattern alignment method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445819A (en) * | 2002-03-17 | 2003-10-01 | 联华电子股份有限公司 | Folded vernier pattern and measurement method for measuring alignment accuracy rating between overlapped multiple layers |
| CN101515116A (en) * | 2008-02-21 | 2009-08-26 | Asml荷兰有限公司 | Mark structure for coarse wafer alignment and method for manufacturing such a mark structure |
| CN103858208A (en) * | 2011-08-10 | 2014-06-11 | 株式会社V技术 | Alignment device and alignment mark for optical exposure device |
| CN105892238A (en) * | 2011-08-31 | 2016-08-24 | Asml荷兰有限公司 | Method of Determining Focus Corrections, Lithographic Processing Cell and Device Manufacturing Method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9543223B2 (en) * | 2013-01-25 | 2017-01-10 | Qoniac Gmbh | Method and apparatus for fabricating wafer by calculating process correction parameters |
| CN104422396B (en) * | 2013-08-29 | 2018-07-06 | 鸿富锦精密工业（深圳）有限公司 | Assembling product gap three dimensional analysis system and method |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445819A (en) * | 2002-03-17 | 2003-10-01 | 联华电子股份有限公司 | Folded vernier pattern and measurement method for measuring alignment accuracy rating between overlapped multiple layers |
| CN101515116A (en) * | 2008-02-21 | 2009-08-26 | Asml荷兰有限公司 | Mark structure for coarse wafer alignment and method for manufacturing such a mark structure |
| CN103858208A (en) * | 2011-08-10 | 2014-06-11 | 株式会社V技术 | Alignment device and alignment mark for optical exposure device |
| CN105892238A (en) * | 2011-08-31 | 2016-08-24 | Asml荷兰有限公司 | Method of Determining Focus Corrections, Lithographic Processing Cell and Device Manufacturing Method |
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