CN100590829C - Method for measuring extent pattern drifting quantity - Google Patents
Method for measuring extent pattern drifting quantity Download PDFInfo
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- CN100590829C CN100590829C CN200710041946A CN200710041946A CN100590829C CN 100590829 C CN100590829 C CN 100590829C CN 200710041946 A CN200710041946 A CN 200710041946A CN 200710041946 A CN200710041946 A CN 200710041946A CN 100590829 C CN100590829 C CN 100590829C
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Abstract
The invention discloses a method for measuring epitaxial pattern shift, which comprises the steps of processing a silicon wafer before epitaxy to form a buried layer window; conducting epitaxial process, at which the shift of a photoetching alignment mark and the buried layer window occurs; rubber coating, aligning and exposing the silicon wafer by using the mask plate of the original buried layerwindow; slicing the silicon wafer along X-axis and dyeing; and measuring the epitaxial pattern offset and the thickness of an epitaxial layer, so as to obtain the epitaxial pattern shift. The inventive method can successfully measure the epitaxial pattern shift on a single silicon wafer epitaxial furnace.
Description
Technical field
The present invention relates to the epitaxy technique in a kind of integrated circuit manufacturing, particularly relate to a kind of method of measurement of extent pattern drifting quantity.
Background technology
Pattern drifting (pattern shift) is a FAQs in the epitaxy technique, and it is meant that the figure (pattern) on the silicon chip (wafer) is subjected to displacement with respect to buried layer (buried layer) after the extension.Pattern drifting accurately makes troubles the location for usually the figure of subsequent technique.
See also Fig. 1, Fig. 1 is the principle schematic of extent pattern drifting.What Fig. 1 (a) showed is the preceding silicon chip 10 of epitaxial growth, and a buried layer window 11 is arranged on the silicon chip 10, and the buried layer window is for 11 times a buried layer 12.Fig. 1 (b) shows is silicon chip 10 after the epitaxial growth, and an epitaxial loayer 20 is arranged on the silicon chip 10, and a buried layer window 21 is arranged on the epitaxial loayer 20, and the buried layer window 21 on the epitaxial loayer 20 is compared with the former buried layer window 11 on the silicon chip 10, and tangible skew has taken place.
In order to guarantee the accurate of subsequent optical carving technology, must know extent pattern drifting quantity, thereby skew is compensated.The measurement pattern drift value adopts paster method usually at present, and paster method is to stick half sheet silicon chip on the silicon chip with buried layer window, and then carries out epitaxy technique; After the epitaxial growth, the part that is touched by half sheet silicon chip is not because there is grown epitaxial layer, so pattern drifting does not take place; The part that is touched by half sheet silicon chip is not because grown epitaxial loayer, so pattern drifting has taken place; The microscope that use has a measurement function can be measured the drift value of epitaxial patterns.
The shortcoming of paster method has two: one, can't carry out paster on the monolithic stove, can only carry out on ladle furnace; The 2nd, the success rate of paster is extremely low on the ladle furnace, and the half sheet silicon chip that sticks often drops, and therefore must repeat repeatedly paster just might successfully carry out the measurement of pattern drifting quantity.
Summary of the invention
Technical problem to be solved by this invention provide a kind of that can on the monolithic stove, realize, can once successful epitaxy technique in the method for measurement of pattern drifting quantity.
For solving the problems of the technologies described above, the technical scheme that the method for measurement of extent pattern drifting quantity of the present invention adopts is:
The 1st step, silicon chip is carried out technology before the extension, form the buried layer window;
In the 2nd step, carry out epitaxy technique;
The 3rd step, resist coating, drying glue uses the mask that forms the buried layer window in the 1st step that silicon chip is aimed at, exposed;
In the 4th step, silicon chip is cut into slices dyeing along X-axis;
In the 5th step, measure epitaxy layer thickness, figure left side drift value, the right drift value of figure, according to formula
Calculate the extent pattern drifting rate.
The 1st step of the method for measurement of above-mentioned extent pattern drifting quantity is carried out technology before the extension to silicon chip, forms the buried layer window and comprises:
In the 1.1st step, on silicon chip, grow
The oxide layer of thickness;
The 1.2nd step, resist coating, photoetching is used to do to carve to form lithography alignment mark (Zero Mask);
The 1.3rd step, remove photoresist, remove oxide layer;
The 1.4th step, resist coating, photoetching forms the buried layer window;
In the 1.5th step, carry out antimony (Sb) at the buried layer window and inject;
The 1.6th step, remove photoresist, boiler tube spreads propelling, annealing, growth oxide layer;
In the 1.7th step, oxide layer is removed, and cleans.
The technique effect that the present invention can reach is to go out extent pattern drifting quantity by one-shot measurement, and realizes the measurement of extent pattern drifting on the monolithic stove.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the principle schematic of extent pattern drifting;
Fig. 2 is the method for measurement schematic diagram of extent pattern drifting quantity of the present invention;
Fig. 3 is the method for measurement flow chart of extent pattern drifting quantity of the present invention;
To be the present invention carry out technology before the extension to silicon chip to Fig. 4, forms the flow chart of buried layer window.
Reference numeral is among the figure: the 10-silicon chip; 11-buried layer window; The 12-buried layer; The 20-epitaxial loayer; 21-buried layer window; The 30-photoresist layer; A-figure left side side-play amount; The right side-play amount of b-figure; The c-epitaxy layer thickness.
Embodiment
Please consult Fig. 2 and Fig. 3 simultaneously, the method for measurement concrete steps of extent pattern drifting quantity of the present invention are as follows:
The 1st step saw also Fig. 2 (a), and silicon chip 10 is carried out technology before the extension, formed buried layer window 11 (BL or NBL) on silicon chip 10;
The 2nd step, see also Fig. 2 (b), silicon chip 10 is carried out epitaxy technique, buried layer window 21 behind the epitaxy technique on the epitaxial loayer 20 is compared with the former buried layer window 11 on the silicon chip 10 obvious skew has been taken place, and the photoetching alignment mark behind the epitaxy technique on the epitaxial loayer 20 is compared with the former photoetching alignment mark on the silicon chip 10 skew (not shown) has also been taken place;
The 3rd step saw also Fig. 2 (c), coated photoresist on this silicon chip 10, and drying glue forms photoresist layer 30; Use the mask that forms buried layer window 11 in the 1st step that this silicon chip 10 is aimed at, exposed then, this moment is owing to skew has also taken place in photoetching alignment mark after the epitaxial growth, so exposed areas is exactly the buried layer window 21 after the skew; Black region among Fig. 2 is exposed areas, and the buried layer window 21 after this zone and the skew coincides together;
The 4th step, this silicon chip 10 is cut along X-axis, obtain comprising the section of photoresist layer 30, epitaxial loayer 20, silicon wafer layer 10, with above-mentioned section dyeing, so that clear each layer of identification;
In the 5th step, use microscope to measure epitaxy layer thickness c, figure left side drift value a, the right drift value b of figure, according to formula with measurement function
Calculate the extent pattern drifting rate.
See also Fig. 4, the 1st in the method for measurement of above-mentioned extent pattern drifting quantity step is carried out technology before the extension to silicon chip, forms the buried layer window and is realized by following steps again:
In the 1.1st step, on silicon chip, grow
The oxide layer of thickness;
The 1.2nd step, resist coating, photoetching uses dry carving technology to form the lithography alignment mark, and the lithography alignment mark is to be used for the accurately mark of location in the subsequent technique;
The 1.3rd step, remove photoresist, remove oxide layer;
The 1.4th step, resist coating, photoetching forms the buried layer window;
In the 1.5th step, carry out antimony (Sb) at the buried layer window and inject dosage (atoms/cm
2) be 2E15;
The 1.6th step, remove photoresist, boiler tube spreads and advances 30 minutes, annealing, growth
The oxide layer of thickness;
In the 1.7th step, oxide layer is removed, and cleans.
Claims (5)
1. the method for measurement of an extent pattern drifting quantity, it is characterized in that: this method comprises the steps:
The 1st step, silicon chip is carried out technology before the extension, form the buried layer window;
In the 2nd step, carry out epitaxy technique;
The 3rd step, resist coating, drying glue uses the mask that forms the buried layer window in the 1st step that silicon chip is aimed at, exposed;
In the 4th step, silicon chip is cut into slices dyeing along X-axis;
In the 5th step, measure epitaxy layer thickness, figure left side drift value, the right drift value of figure, according to formula
2. the method for measurement of extent pattern drifting quantity according to claim 1 is characterized in that: wherein the 1st step was carried out technology before the extension to silicon chip, formed the buried layer window and comprised the steps:
The 1.1st step, the oxide layer of the some thickness of growth on silicon chip;
The 1.2nd step, resist coating, photoetching is used to do to carve to form the lithography alignment mark;
The 1.3rd step, remove photoresist, remove oxide layer;
The 1.4th step, resist coating, photoetching forms the buried layer window;
In the 1.5th step, carry out ion at the buried layer window and inject;
The 1.6th step, remove photoresist, boiler tube spreads and advances the some time, annealing, the oxide layer of some thickness of growing;
In the 1.7th step, oxide layer is removed, and cleans.
3. the method for measurement of extent pattern drifting quantity according to claim 2, it is characterized in that: wherein the thickness of oxide layer of the 1.1st one-step growth is 200
4. the method for measurement of extent pattern drifting quantity according to claim 2 is characterized in that: wherein the ion that injects was an antimony the 1.5th step, and dosage is 2E15atoms/cm
2
5. the method for measurement of extent pattern drifting quantity according to claim 2 is characterized in that: wherein to spread the time of propelling be 30 minutes to the 1.6th step boiler tube, and the thickness of oxide layer of growth is 500
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN200710041946A CN100590829C (en) | 2007-06-13 | 2007-06-13 | Method for measuring extent pattern drifting quantity |
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| CN200710041946A CN100590829C (en) | 2007-06-13 | 2007-06-13 | Method for measuring extent pattern drifting quantity |
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| CN101325168A CN101325168A (en) | 2008-12-17 |
| CN100590829C true CN100590829C (en) | 2010-02-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102005369B (en) * | 2010-09-10 | 2015-08-12 | 上海集成电路研发中心有限公司 | A kind of lithography alignment method for epitaxy technique |
| CN102788556A (en) * | 2012-08-24 | 2012-11-21 | 中国电子科技集团公司第二十四研究所 | Method for measuring drift amount of buried graph after epitaxial growth |
| CN103681240B (en) * | 2013-12-12 | 2016-03-02 | 杭州士兰集成电路有限公司 | Epitaxial temperature test monitoring structure and formation method |
| CN105870031B (en) * | 2016-04-19 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | epitaxial growth monitoring pattern and monitoring method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER NAME: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |