CN102034685B - Method for using post-epitaxial photoetching to align zero-level marks - Google Patents
Method for using post-epitaxial photoetching to align zero-level marks Download PDFInfo
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- CN102034685B CN102034685B CN2009100579460A CN200910057946A CN102034685B CN 102034685 B CN102034685 B CN 102034685B CN 2009100579460 A CN2009100579460 A CN 2009100579460A CN 200910057946 A CN200910057946 A CN 200910057946A CN 102034685 B CN102034685 B CN 102034685B
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Abstract
The invention discloses a method for using post-epitaxial photoetching to align zero-level marks, comprising the following steps: step 1, carrying out zero-level photoetching on a silicon wafer, carrying out exposure only on a first group of exposure units of the silicon wafer, then photoetching and forming a first group of zero-level marks; step 2, carrying out ion implantation on a silicon substrate; step 3, carrying out zero-level photoetching on the silicon wafer, carrying out exposure only on a second group of exposure units of the silicon wafer, then photoetching and forming a second group of zero-level marks, wherein the first group of exposure units and the second group of exposure units are not coincided completely; step 4, cleaning the silicon wafer, and carrying out epitaxial growth on the silicon wafer; and step 5, carrying out photoetching on an epitaxial layer and aligning the photoetching in the step to the second group of zero-level marks. In the method, twice zero-level photoetching and etching is adopted to form two groups of zero-level marks so as to be respectively used for pre-epitaxial and post-epitaxial alignment. Therefore, not only the need of pre-epitaxial photoetching alignment is guaranteed, but also a group of brand-new zero-level marks for use of post-epitaxial photoetching is provided.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing process, particularly relate to the alignment methods in a kind of photoetching process.
Background technology
Photoetching is the technical process that the circuit structure of the last graphic form of mask (mask) is transferred to the silicon chip surface that scribbles photoresist through steps such as aligning, exposure, developments.Photoetching process can form one deck photoresist masking figure at silicon chip surface, and its subsequent technique is that etching or ion inject.
During semiconductor integrated circuit is made, usually need be through photo-mask process repeatedly.The photoetching that wherein forms silicon chip ground floor (orlop) figure is called zero layer photoetching.Zero layer photoetching is called zero layer mark with the formed silicon chip ground floor of etching figure, the usefulness of aiming at when zero layer mark is the follow-up photoetching of confession.
After forming zero layer mark, often followed epitaxy technique, promptly grow from several microns to tens microns even thicker epitaxial loayer at silicon chip surface.After epitaxy technique was accomplished, zero layer mark covered by epitaxial loayer, just occurred two kinds of situation here.
First kind of situation be not after zero layer photoetching and etching, before the epitaxial growth, have other technology.The exemplary of this situation is as shown in Figure 1, and the method for delaying lithography alignment zero layer mark outward comprises:
In the 1st step, silicon substrate is carried out ion inject.Specifically comprise again:
In the 1.1st step, deposit thin film on silicon substrate, this layer film are used to make the range that follow-up ion injects can dark excessively (this step deposition film can not omit).
The 1.2nd step, silicon substrate is carried out photoetching, formed photoresist masking figure exposes ion and injects window, and all the other area of silicon wafer are covered by photoresist.
In the 1.3rd step, inject window at ion and carry out the ion injection.
In the 1.4th step, silicon chip is annealed.
The 1.5th step, a step or the multistep in above-mentioned repeatedly the 1.1st step to the 1.4th step.
The 2nd step, shown in Fig. 1 left side, silicon substrate 10 is carried out zero layer photoetching and etching, form zero layer mark 11 (exemplarily being expressed as the groove form in the drawings).
In the 3rd step, shown in Fig. 1 right side, cleaning silicon chip carries out epitaxial growth to silicon chip, and zero layer mark 11 covered by epitaxial loayer 12.
In the 4th step, epitaxial loayer is carried out photoetching, this step lithography alignment zero layer mark 11.Owing to after zero layer mark 11 forms, directly carry out epitaxial growth, zero layer mark, 11 forms before the epitaxial growth are intact, so zero layer mark 11 still can clearly be differentiated after the epitaxial growth.
Second kind of situation is after zero layer photoetching and etching, before the epitaxial growth, exist some technologies that are used to adjust device performance (like film growth, ion injection, annealing etc.).The exemplary of this situation is as shown in Figure 2, and the method for delaying lithography alignment zero layer mark outward comprises:
The 1st step, shown in Fig. 2 upper left side, silicon substrate 10 is carried out zero layer photoetching and etching, form zero layer mark 11 (exemplarily being expressed as the groove form in the drawings).
The 2nd step, shown in the downside of Fig. 2 left side, silicon substrate 10 to be carried out ion inject, concrete steps are identical with the 1st step in above-mentioned first kind of situation.Owing to receive the influence of technologies such as film growth, ion injection, annealing, the form of zero layer mark 11 is destroyed.
In the 3rd step, shown in Fig. 2 right side, cleaning silicon chip carries out epitaxial growth to silicon chip, and zero layer mark 11 covered by epitaxial loayer 12.
In the 4th step, epitaxial loayer is carried out photoetching, this step lithography alignment zero layer mark 11.The form of zero layer mark 11 is destroyed before epitaxial growth this moment, so zero layer mark, 11 distortion even can't measure after the epitaxy technique.
Obviously, no matter engineers hopes that under any situation, zero a layer mark all can be known identification after silicon chip carried out epitaxial growth.But for above-mentioned second kind of situation, how to overcome after zero layer photoetching and the etching, epitaxial growth technogenic influence before, be a problem of needing solution badly.
Summary of the invention
Technical problem to be solved by this invention provides a kind of silicon chip when the laggard capable photoetching of epitaxial growth, and the method for this step lithography alignment zero layer mark, the core of this method are to make zero layer mark still can know identification through behind the epitaxy technique.
For solving the problems of the technologies described above, the method that the present invention delays lithography alignment zero layer mark outward comprises the steps:
The 1st step, silicon chip is carried out zero layer photoetching, only first group of exposing unit at silicon chip makes public, and etching forms first group zero layer mark then;
In the 2nd step, silicon substrate is carried out ion inject;
The 3rd step, again silicon chip is carried out zero layer photoetching, only second group of exposing unit at silicon chip makes public, and etching forms second group zero layer mark then;
Said first group of exposing unit do not overlap with second group of exposing unit fully;
In the 4th step, cleaning silicon chip carries out epitaxial growth to silicon chip;
In the 5th step, epitaxial loayer is carried out photoetching, second group zero layer mark of this step lithography alignment.
The present invention adopts twice zero layer photoetchings and etching to form two groups zero layer mark, is respectively applied for before the extension and the aligning of delaying outward.So both guarantee the needs of the preceding lithography alignment of extension, and provided one group of zero brand-new layer mark to supply the outer photoetching use of delaying again.
Description of drawings
Fig. 1 is a kind of existing outer sketch map of delaying the method for lithography alignment zero layer mark;
Fig. 2 is the another kind of existing outer sketch map of delaying the method for lithography alignment zero layer mark;
Fig. 3 is the sketch map of exposing unit on the silicon chip;
Fig. 4 is the sketch map that the present invention delays the method for lithography alignment zero layer mark outward.
Description of reference numerals among the figure:
10 is silicon substrate; 11 is zero layer mark; 12 is epitaxial loayer;
1 is silicon chip; 2 is exposing unit; 21 is first group of exposing unit; 22 is second group of exposing unit.
Embodiment
See also Fig. 3, have a plurality of exposing units 2 on the silicon chip 1, each exposing unit 2 is the identical square of size.In the existing method, all exposing units 2 on the silicon chip 1 are carried out zero layer photoetching and etching, thereby on whole silicon wafer 1, form zero layer mark.When the subsequent optical carving technology needs aligned at zero layer mark, be not with all exposing units 2 in zero a layer mark all aim at, and just select zero layer markers align in several exposing units 2.
See also Fig. 4, the method that the present invention delays lithography alignment zero layer mark outward comprises the steps:
In the 1st step, shown in Fig. 4 left side, silicon chip 1 (silicon substrate) is carried out zero layer photoetching.Earlier at silicon chip 1 surface coated photoresist, only first group of exposing unit 21 of silicon chip 1 made public then, the back of developing exposes etching window in the zone of first group of exposing unit 21, all the other zones still by the photoresist covering as etching barrier layer.Then etching forms first group zero layer mark in etching window, removes photoresist after etching is accomplished.
Usually when lithography alignment; General technology at least need with zero layer markers align in 5 exposing units; Precision process at least need with zero layer markers align in 8 exposing units, therefore the number of exposing units in first group of exposing unit 21 should be preferably more than 8 more than 5.
In the 2nd step, silicon substrate is carried out ion inject.Specifically comprise again:
In the 2.1st step, deposit thin film on silicon substrate, this layer film are used to make the range that follow-up ion injects can dark excessively (this step deposition film can not omit).
The 2.2nd step, silicon substrate is carried out photoetching, first group zero layer mark of this step lithography alignment, formed photoresist masking figure exposes ion and injects window, and all the other area of silicon wafer are covered by photoresist.
In the 2.3rd step, inject window at ion and carry out the ion injection.
In the 2.4th step, silicon chip is annealed.
In the 2.5th step, the step or the multistep that repeat in above-mentioned the 2.2nd step to the 2.4th step are accomplished until all ion implantation technologies.When repetition the 2.2nd goes on foot photoetching, still aim at first group zero layer mark.
In the 3rd step, shown in Fig. 4 right side, again silicon chip 1 is carried out zero layer photoetching.Earlier at silicon chip 1 surface coated photoresist, only second group of exposing unit 22 of silicon chip 1 made public then, the back of developing exposes etching window in the zone of second group of exposing unit 22, all the other zones still by the photoresist covering as etching barrier layer.Then etching forms second group zero layer mark in etching window, removes photoresist after etching is accomplished.
Similar with first group of exposing unit 21, the number of exposing units in second group of exposing unit 22 also should be preferably more than 8 more than 5.But require second group of exposing unit 22 not overlap fully, promptly have no common factor with first group of exposing unit 21.
In the 4th step, cleaning silicon chip carries out epitaxial growth to silicon chip.
In the 5th step, epitaxial loayer is carried out photoetching, second group zero layer mark of this step lithography alignment.
Why said method requires second group of exposing unit not overlap fully with first group of exposing unit in the 3rd step, is in order to make second group zero clear, the easy identification of layer mark.Because the figure of zero layer mark is all the same in each exposing unit; If exposure, etching once more on the first group of exposing unit that forms odd layer mark; Second group zero layer mark and first group of zero layer of situation that is marked with minor deviations can take place unavoidably, and this aligning to the subsequent optical carving technology is disadvantageous.
The said method mask that photoetching is adopted in the 3rd step, identical with the mask that photoetching in the 1st step is adopted.The mask here is corresponding with an exposing unit, promptly adopts this mask only can make an exposing unit exposure at every turn.
The etching of said method in the 3rd step, the etching with in the 1st step can adopt identical etching parameters, also can be different.Etching in the 3rd step can be considered that outer delaying requires the clear factor of recognizing, and process conditions are carried out some adjustment and optimization; For example require that groove width is wideer, the etching section of groove is more vertical etc.
The present invention delays the method for lithography alignment zero layer mark outward, and traditional once zero layer photoetching is become twice zero layer photoetchings, thereby forms two groups zero layer mark.First group zero layer is labeled as the preceding photoetching of extension as aiming at foundation, and second group zero layer is labeled as the outer photoetching of delaying as the aligning foundation.This method has fully guaranteed the needs of the forward and backward lithography alignment of extension, and second group zero layer is marked at outer delaying still and can knows identification, thereby increased substantially the outer precision of delaying lithography alignment.
Claims (6)
1. a method of delaying lithography alignment zero layer mark outward is characterized in that, comprises the steps:
The 1st step, silicon chip is carried out zero layer photoetching, only first group of exposing unit at silicon chip makes public, and etching forms first group zero layer mark then;
In the 2nd step, silicon substrate is carried out ion inject;
The 3rd step, again silicon chip is carried out zero layer photoetching, only second group of exposing unit at silicon chip makes public, and etching forms second group zero layer mark then;
Said first group of exposing unit do not overlap with second group of exposing unit fully;
In the 4th step, cleaning silicon chip carries out epitaxial growth to silicon chip;
In the 5th step, epitaxial loayer is carried out photoetching, second group zero layer mark of this step lithography alignment.
2. the outer method of delaying lithography alignment zero layer mark according to claim 1 is characterized in that said first group of exposing unit and second group of exposing unit all comprise 5 exposing units at least.
3. the outer method of delaying lithography alignment zero layer mark according to claim 1 is characterized in that said first group of exposing unit and second group of exposing unit all comprise 8 exposing units at least.
4. the outer method of delaying lithography alignment zero layer mark according to claim 1 is characterized in that, the zero layer photoetching of said method in the 3rd step with the zero layer photoetching of said method in the 1st step, adopts identical mask.
5. the outer method of delaying lithography alignment zero layer mark according to claim 1 is characterized in that, said the 2nd step of method specifically comprises again:
In the 2.2nd step, silicon substrate is carried out photoetching form ion injection window, first group zero layer mark of this step lithography alignment;
In the 2.3rd step, inject window at ion and carry out the ion injection;
In the 2.4th step, silicon chip is annealed;
The 2.5th step repeated above-mentioned the 2.2nd step to the 2.4th step, accomplished until all ion implantation technologies.
6. the outer method of delaying lithography alignment zero layer mark according to claim 5 is characterized in that, said the 2nd step of method specifically comprises again:
The 2.1st step, deposit thin film on silicon substrate; This step is before the 2.2nd step.
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| CN105140163A (en) * | 2015-07-22 | 2015-12-09 | 上海华力微电子有限公司 | Method for improving photolithography alignment and overlaying accuracy |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131218 |
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Effective date of registration: 20131218 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |