CN101419920A - 用于制造半导体元器件的方法以及因之的结构 - Google Patents
用于制造半导体元器件的方法以及因之的结构 Download PDFInfo
- Publication number
- CN101419920A CN101419920A CNA2008102110496A CN200810211049A CN101419920A CN 101419920 A CN101419920 A CN 101419920A CN A2008102110496 A CNA2008102110496 A CN A2008102110496A CN 200810211049 A CN200810211049 A CN 200810211049A CN 101419920 A CN101419920 A CN 101419920A
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- leadframe leads
- type surface
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- semiconductor components
- metallic base
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 157
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 239000001913 cellulose Substances 0.000 claims abstract description 5
- 229920002678 cellulose Polymers 0.000 claims abstract description 5
- 239000004033 plastic Substances 0.000 claims abstract description 5
- 229920003023 plastic Polymers 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 53
- 238000010276 construction Methods 0.000 claims description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 238000000465 moulding Methods 0.000 claims description 16
- 239000000203 mixture Substances 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 230000002209 hydrophobic effect Effects 0.000 claims description 4
- 239000000123 paper Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 description 122
- 229910052755 nonmetal Inorganic materials 0.000 description 42
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 10
- 229910052759 nickel Inorganic materials 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000004094 surface-active agent Substances 0.000 description 5
- 230000006353 environmental stress Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000835 fiber Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000565 sealant Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 2
- VZCYOOQTPOCHFL-OWOJBTEDSA-N Fumaric acid Chemical compound OC(=O)\C=C\C(O)=O VZCYOOQTPOCHFL-OWOJBTEDSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002738 chelating agent Substances 0.000 description 2
- 238000001311 chemical methods and process Methods 0.000 description 2
- 239000008139 complexing agent Substances 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229960001484 edetic acid Drugs 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- -1 for example Chemical class 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004823 Reactive adhesive Substances 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000001530 fumaric acid Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010948 rhodium Substances 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- VZCYOOQTPOCHFL-UHFFFAOYSA-N trans-butenedioic acid Natural products OC(=O)C=CC(O)=O VZCYOOQTPOCHFL-UHFFFAOYSA-N 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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Abstract
一种制造半导体元器件的方法,所述半导体元器件包括引线框架,所述引线框架具有非金属基础结构和中间的引线框架结构。除了别的材料以外,所述非金属基础结构可以是纸、纤维素或塑料。一层导电材料形成在非金属基础结构上。从该层导电材料形成电路元件连接结构和多个引线框架引线。电路元件被耦合到电路元件连接结构,并且被电耦合到多个引线框架引线。电路元件被封装,并且至少非金属基础结构被去除。可选择地,多个引线框架引线可形成在所述导电层之上,并且电路元件被置于该导电层之上。所述电路元件被电耦合到多个引线框架引线上并被封装。非金属基础结构和导电层被去除。
Description
技术领域
本发明一般涉及半导体元器件,更具体地,涉及半导体元器件中使用的引线框架。
背景技术
半导体元器件制造商一直力求在降低他们的制造成本的同时,提高他们产品的性能。半导体元器件制造中的一个成本密集领域是封装含有半导体器件的半导体芯片(chip)。如本领域技术人员所周知的是,分立的半导体器件和集成电路从半导体晶圆制造而来,该半导体晶圆随后被单一元件化(singulated)或被切成小块以生产半导体芯片。通常,一个或更多半导体芯片通过使用焊接晶片(die)连接材料连接到金属引线框架,并且被封装到模制材料(mold compound)内,以提供对环境应力和机械应力的防护。
在半导体芯片被封装并被单一元件化为半导体元器件之后,引线框架中用于支撑的部分被丢弃。由于大部分金属被用于在制造步骤中提供支撑,所以大部分金属被丢弃。因此,一种降低半导体元器件成本的方法是引线框架采用低成本的金属。然而,金属的选择受到其机械特性和性能指标,例如金属的热导率和导电率的强烈影响。在机械强度,热导率和导电率之间提供可接受的平衡的金属为铜。铜的一个缺点是其价格在持续上升,这增加了半导体元器件的成本。
因此,具有包括低成本引线框架的半导体元器件以及制造包括所述低成本引线框架的所述半导体元器件的方法将是有优势的。
附图说明
结合附图阅读以下发明详述能更好地理解本发明,其中相似的参考符合表示相似的元件,且其中:
图1是根据本发明实施方式的、用于在制造半导体元器件时使用的引线框架的一部分的截面图;
图2是图1的引线框架部分在后续制造阶段的截面图。;
图3是图2的引线框架部分在后续制造阶段的截面图;
图4是图3的引线框架部分在后续制造阶段的截面图;
图5是包括图4的引线框架部分的引线框架在后续制造阶段的俯视图;
图6是多个半导体元器件沿图7中截面线6-6截取的截面图;
图7是根据本发明实施方式的图6的多个半导体元器件的俯视图;
图8是包括图6的引线框架部分的引线框架组件在后续制造阶段的截面图;
图9是根据本发明另一实施方式的处于制造阶段的多个半导体元器件的俯视图;
图10是图9中的单一元件化的半导体元器件在后续制造阶段的截面图;
图11是根据本发明另一实施方式的、用于在半导体元器件制造中使用的引线框架的截面图;
图12是根据本发明另一实施方式的处于制造阶段的多个半导体元器件的俯视图,其中半导体元器件包括图11的引线框架;
图13是包括图11引线框架的引线框架组件在后续制造阶段的截面图;
图14是图13的单一元件化的半导体元器件在后续制造阶段的截面图;
图15是根据本发明另一实施方式的用于在半导体元器件制造中使用的引线框架的截面图;
图16是图16的引线框架在后续制造阶段的截面图;
图17是根据本发明另一实施方式的处于制造阶段的多个半导体元器件的俯视图,其中的半导体元器件包括图16的引线框架;
图18是包括图16引线框架的引线框架组件在后续制造阶段的截面图;以及
图19是图18中的单一元件化的半导体元器件在后续制造阶段的截面图。
具体实施方式
一般地,本发明提供了使用引线框架的半导体元器件,所述引线框架包含非金属衬底层,在非金属衬底的至少一个表面上具有金属层。该非金属衬底也被称为非金属基础结构。根据本发明的实施方式,半导体元器件制造中使用的引线框架在两层导电材料之间包含低成本的非金属基础结构。例如,非金属支撑结构的材料可以是纤维素、纸、塑料,或其它能够经受高温处理、与形成导电层相关的化学过程,以及与切割和冲压金属层相关的压力的材料。用于导电层的合适的金属包括铜、镍或类似金属。电路元件连接结构和引线框架引线可以从一个或多个导电层形成。当半导体晶片被连接至其时,电路元件连接结构也被称作半导体晶片连接垫或电路元件连接垫;或者当无源电路元件被连接至其时,电路元件连接结构也被称为无源器件连接垫或无源电路元件垫。应该注意到,电路元件连接结构、无源器件连接垫,以及引线框架引线形成于非金属衬底之上而非是非金属衬底的一部分。半导体晶片被耦合到电路元件连接结构,而半导体晶片上的键合垫通过引线键合(wirebond)被耦合到引线框架引线,并且被封装进模制材料之内,以形成中间结构。在用模制材料保护半导体晶片和引线框架引线后,非金属基础结构和至少一层导电材料被去除。
根据本发明的其他实施方式,引线框架引线形成于非金属基础结构上的其中一个导电层之上,并且半导体晶片被连接到非金属基础结构之上的导电材料的一部分。半导体晶片被连接在其上的区域被称作半导体晶片连接区域或电路元件连接区域。半导体晶片上的键合垫被通过引线键合连接到引线框架引线。半导体晶片、引线框架引线和引线键合被密封剂或模制材料保护,以形成中间结构,并且非金属支撑结构和位于非金属支撑结构大部分表面上的导电材料层被去除。
根据本发明的其它实施方式,包括位于两层导电材料之间的低成本的不导电材料的引线框架被用来形成封装,比如,例如,有引线或无引线的四列扁平式封装;微引线框架封装,包括微引线框架四列封装和微引线框架双列封装;双列直插封装;四列直插封装,或其它类似封装。
根据本发明的其它实施方式,引线框架包括非金属支撑结构,电路元件连接结构和引线框架引线被压入该非金属支撑结构里。非金属支撑结构可以是纤维素、纸、塑料,或其它能够经受高温处理、与形成导电层相关的化学过程,以及与切割和冲压金属层相关的压力的材料。电路元件连接结构可以包括,例如,导电垫,无源器件垫,电路元件连接垫,或无源器件连接垫。电路元件连接结构也被称为半导体晶片连接区域或半导体晶片连接部位。用于导电层的合适的材料包括铜、镍,或其它类似材料。半导体晶片被耦合到导电层,而半导体晶片上的键合垫被通过引线键合耦合到引线框架引线。半导体晶片和引线框架引线被模制材料保护,以形成中间结构,且非金属基础结构被去除。
图1是根据本发明实施方式的、在制造半导体元器件10(图8中显示)时被用作引线框架的一部分的非金属支撑结构12的截面图。优选地,非金属支撑结构12包括纤维结构,该纤维结构具有顶表面14、底表面16,且厚度在大约100微米(μm)到大约2,500μm之间。表面14和16也分别被称为顶表面和底表面。举例来说,纤维结构是基于纤维素的材料,比如纸。用于非金属支撑结构12的其它合适的材料包括纸板、塑料、有机基板或类似材料。非金属支撑结构12也被称为非金属基础结构。表面14和16被用表面活性剂处理,比如,例如,被用树脂处理,以在表面14和16上分别形成防水层18和20。树脂是一种用反丁烯二酸处理树脂酸而形成的防水材料。优选地,树脂呈弱酸性,pH值在大约4到大约6.5之间。本发明不受树脂的pH值的限制。防水层18和20中的树脂分子是双性分子,具有相对的两端,一端亲水,与之相对的另一端疏水。亲水端面向表面14和16,而疏水端远离表面14和16延伸。层18和20的疏水端排斥水,从而减少非金属支撑结构12对水的吸收。在非金属支撑结构12上形成层18和20被称为施胶或重施胶(hard sizing)。
参照图2,厚度在大约20μm到大约50μm之间的一层导电材料22形成于防水层18之上,而厚度在大约20μm到大约50μm之间的一层导电材料24形成于防水层20之上。根据本发明的实施方式,导电层22和24是一种金属,比如,例如,由非电镀镀铜技术或非电镀镀镍技术形成的铜或镍。铜可以使用这样的含铜镀液镀在防水层18和20之上,该含铜镀液包含作为铜源的硫酸铜(II)、作为化学还原剂的甲醛,以及用以将铜保持在溶液中的络合剂或螯合剂。合适的络合剂或螯合剂包括酒石酸离子、乙二胺四乙酸(EDTA)、胺、胺衍生物、乙醇酸,或者类似物质。镀液的pH值优选地保持在大于大约十一(11)的值,因为甲醛的还原能力随着pH值增加而增加。除了镀液含镍而非铜之外,镀镍的镀液与镀铜的镀液相似。层18和20的防水性质使得非金属支撑结构12的表面在镀金属过程使用的化学溶液中排斥水。这便于在模制过程之后除去导电材料。
可选择地,导电层22和24可以通过烫金工艺或电镀工艺形成。可以被用来形成导电层22和24的金属包括金、银、铑、铬、锌、锡,其合金,或金属基复合材料。
现在参照图3,一层光刻胶在导电层22上形成,并且被形成图案以形成遮蔽结构28,该遮蔽结构具有开口30,暴露出导电层22的部分区域。
图4是引线框架引线34的截面图,通过例如使用一种电镀技术,引线框架引线34被形成于导电层22被暴露出的部分上。根据本发明的实施方式,引线框架引线34包含一个双层结构,其中第二导电材料层38形成于第一导电材料层36之上,第一导电材料层36形成于导电层22之上。导电层36的材料可以是厚度在大约5μm到大约25μm之间的金或镍,导电层38的材料可以是厚度在大约0.2μm到大约1μm之间的银或镍。举例来说,导电层36为金而导电层38的材料为银。在引线框架引线34形成之后,遮蔽结构28被去除。
图5是导电层22和引线框架引线34的俯视图。更具体地说,图5显示多个半导体元器件区40,该半导体元器件区包括半导体晶片连接区域42和引线框架引线34。半导体晶片连接区域42也被称为半导体晶片连接结构、电路元件连接区域或电路元件连接结构,而引线框架引线34也被称作输入/输出垫。半导体元器件10可以从每个半导体元器件区40制造。非金属支撑结构12、防水层18和20、导电层22和24、半导体晶片连接区域42,以及引线框架引线34共同形成引线框架45。应该指出,引线框架通常包括排列成M乘N外围阵列的多个半导体元器件区,其中M是阵列的行数,而N是阵列的列数。本发明不受上述行数和列数的限制。图5中所示的是一个2乘2的半导体元器件区阵列,其中每行显示两个半导体元器件区40,每列显示两个半导体元器件区40。
图6是引线框架45沿图7的截面线6-6截取的截面图。图6显示了通过晶片连接材料60耦合到半导体晶片连接区域42的半导体晶片58。每个半导体晶片58具有顶或活性表面(active surface)62,以及底或配合表面64。多个键合垫68被布置在活性表面62上。配合表面64被置于晶片连接材料60中,而晶片连接材料60被置于半导体晶片连接区域42上。用于晶片连接材料60的合适的材料包括环氧树脂、聚酰亚胺、热塑软膏、热塑薄膜,或类似材料。晶片连接材料60可以被置于半导体晶片连接区域42的表面上,或者被层压到半导体晶片58的背面,并被B-阶固化。
引线键合66将键合垫68连接到对应的引线框架引线34。引线键合也被称作键合线或互连线。优选地,单个引线键合将引线框架引线连接到对应的键合垫。然而,本发明不限于此。例如,一个或更多键合垫可以被连接到单个引线框架引线。图7是分别耦合到半导体晶片连接区域42的半导体晶片58和通过引线键合66耦合到引线框架引线34的键合垫68的俯视图。图7中,对于每个半导体元器件区40展示和描绘了十六个键合垫68、十六条引线框架引线34,以及十六条引线键合66。然而,应该了解,本发明并不受键合垫68、引线框架引线34以及引线键合66的个数的限制。另外,可以配置引线框架引线34的形状,以便通过引线键合66将多个键合垫68耦合到单个引线框架引线34。形成引线键合的技术对于本领域的技术人员是已知的。虽然已描述单个半导体晶片被连接到引线框架45的每个半导体晶片连接区域42,但本发明并不限于此。可以配置引线框架以让多个半导体晶片连接到半导体晶片连接区域,或者可以有多个半导体晶片连接区域,其中每个半导体晶片连接区域包括一个或更多半导体晶片。
如参照图3所述的,引线框架45包括多个活性区,半导体元器件从这些活性区制造。在引线键合形成之后,在其上安装了半导体晶片的非金属支撑结构12、引线框架引线44以及引线键合66被布置在模具中,以用密封剂或模制材料70封装半导体晶片58、引线框架引线44以及引线键合66,该密封剂或模制材料保护半导体元器件免受机械或环境应力影响。
图8是由模制材料70封装的半导体晶片连接区域42、半导体晶片58,引线框架引线44的截面图,它们构成引线框架组件72。通过例如使用晶圆平坦化工艺,如化学-机械平坦化工艺去除导电层24、防水层20、非金属支撑结构12以及防水层18来使导电层22暴露,并例如通过使用化学-机械平坦化工艺、湿法刻蚀工艺及其组合或类似技术来去除导电层22。去除导电层22使得半导体晶片连接区域42中半导体晶片58下面的铜通过模制材料70与引线框架引线34分隔开或与之电绝缘。接着,单个半导体元器件10被从引线框架组件72单一元件化。图8所示的引线框架组件72具有两个半导体元器件10,使得它可以被单一元件化为两个单独的半导体元器件。应该注意,本发明并不限于将单个半导体晶片耦合到半导体晶片连接区域42,且无源器件以及有源器件可以被连接到半导体晶片连接区域42。
图9是根据本发明另一实施方式的、在制造半导体元器件100(如图10所示)时被用作引线框架的一部分的非金属支撑结构12的俯视图。图9中所示的是包括半导体晶片连接区域42和引线框架引线34的多个半导体元器件区102。另外,半导体元器件区102包括无源器件连接区域104,该区域具有可以在制造引线框架引线34时被制造的引线框架引线106和108。半导体元器件100可以从每个半导体元器件区102制造。非金属支撑结构12、防水层18和20、导电层22和24、引线框架引线34、半导体晶片连接区域42、无源器件连接区域104以及引线框架引线106和108共同形成引线框架110。
半导体晶片58被耦合到半导体晶片连接区域42,并且键合垫68通过引线键合66被耦合到对应的引线框架引线34。无源器件或无源电路元件112在无源器件连接区域104中被耦合到引线框架引线106和108。更具体地说,无源器件112的接触端116和118采用例如焊接连接到引线框架引线106和108。无源器件112覆盖引线框架引线106和108的某些部分。引线框架引线106可以通过引线键合,例如引线键合114,连接到一个或更多引线框架引线34。引线框架引线108也可以被连接到一个或更多引线框架引线34,或者它们可以被耦合成接收来自半导体元器件100的外部的源的电信号。应该了解,无源器件或无源电路元件112可以是电感、电阻、电容,或其组合。在无源器件连接区域104中可以形成多于两个引线框架引线,以便可以从无源器件连接区域104制造多个无源器件。可选择地,可以制造多个如区域104的无源器件连接区域作为引线框架的一部分。
图10是单一元件化后的半导体元器件100的截面图。图10所示的是相互连接并且被封装在封装材料或模制材料70之内的半导体晶片58和无源电路元件112。键合垫68被通过引线键合66连接到对应的引线框架引线34。无源电路元件112的接触端116和118被分别耦合到引线框架引线106和108,其中引线框架引线106通过引线键合114被耦合到引线框架引线34。因此,半导体元器件100包含被电连接到半导体晶片58的无源电路元件112。
图11是根据本发明另一实施方式的、在制造半导体元器件150(如图14所示)时被用作引线框架的一部分的非金属支撑结构12的截面图。非金属支撑结构12已参照图1被描述。应该注意,用表面活性剂比如树脂处理表面14和16是任选的步骤。根据参照图11所描述的实施方式,优选地,表面14和16不用表面活性剂处理。电路元件连接结构或导电晶片连接垫152被压进非金属支撑结构12,并且导电引线框架引线154被压进非金属支撑结构12中与导电晶片连接垫152相邻的部分。电路元件连接结构152也被称为导电晶片连接垫、半导体晶片连接区域、半导体晶片连接垫或半导体晶片连接结构。导电晶片连接垫152和引线框架引线154可以通过冲压工艺、穿孔工艺、对导电晶片连接垫152和引线框架引线154施加恒定压力或其它类似工艺而被压进非金属支撑结构12。导电晶片连接垫152和引线框架引线154被压进非金属支撑结构12的深度由它们的厚度以及它们的表面被要求高于非金属支撑结构12的表面14的高度决定。引线框架引线154具有凹槽或缺口156,它们被用作模具锁定(mold lock)特征。应该注意,模具锁定特征的存在是任选的。可选择地,可以在非金属支撑结构12中形成孔或者开口,其尺寸被设置以接受导电晶片连接垫152和引线框架引线154。粘合材料可以被放置在开口中,并且导电晶片连接垫152和引线框架引线154可以被放在其对应的孔中,接着凝固或固化粘合材料。可选择地,导电晶片连接垫152和引线框架引线154可以通过粘合带被连接到非金属支撑结构12,或者可以调整开口尺寸以使导电晶片连接垫152和引线框架引线154通过摩擦配合保持在开口中。
根据本发明的实施方式,导电晶片连接垫152为立方形,边长约1,800μm,厚度约200μm。应该注意,本发明不受导电晶片连接垫152顶表面的形状或图形限制。例如,它可以为三角形、长方形、五边形、多边形、圆形、椭圆形或其它类似形状。另外,本发明不受导电晶片连接垫152的尺寸限制。类似地,引线框架引线154可以为立方形,并且其顶表面可以为三角形、长方形、五边形、多边形、圆形、椭圆形或其它类似形状。举例来说,引线框架引线154的边长大约150μm,引线框架引线154的厚度大约200μm。
图12是非金属支撑结构12的俯视图,导电层152和引线框架引线154被嵌入其中。更具体地说,图12显示包含半导体晶片连接垫152和引线框架引线154的多个半导体元器件区158。半导体元器件150可以从每个半导体元器件区158制造。非金属支撑结构12、导电晶片连接垫152以及引线框架引线154共同形成引线框架160。图12所示的是半导体元器件区158的2乘2外围阵列。半导体晶片58被通过图13所示的晶片连接材料60耦合到导电晶片连接垫152。半导体晶片58和晶片连接材料60已参照图5描述。
引线键合66将键合垫68连接到对应的引线框架引线154。优选地,单个引线键合将引线框架引线连接到对应的键合垫。然而,本发明不限于此。例如,一个或更多键合垫可以被连接到单个引线框架引线。根据图12所示的实施方式,半导体芯片58被耦合到每个半导体晶片连接区域152,并且键合垫68通过引线键合66被耦合到对应的引线框架引线154。虽然已参照图12展示和描述了十六条引线框架引线154、十六条引线键合66以及十六个键合垫68,但应该了解,本发明不受引线框架引线154、引线键合66以及键合垫68的数目的限制。单个半导体晶片已被描述为连接到引线框架160,然而本发明并不限于此。可以配置引线框架以让多个半导体晶片连接到半导体晶片连接垫或多个半导体晶片连接垫,其中每个半导体晶片连接垫包括一个或更多半导体晶片。
图13是引线框架160沿图12的截面线13-13截取的截面图。图13显示通过晶片连接材料60耦合到导电层152的半导体晶片58,以及将键合垫68连接到对应的引线框架引线154的引线键合66。引线框架160被布置在模具中(图中未示),并且模制材料被注入该模具以形成半导体晶片58、引线键合66、导电晶片连接垫152以及引线框架引线154之上的密封剂70,以形成引线框架组件162。模制材料70保护半导体晶片58、引线键合66、导电晶片连接垫152以及引线框架引线154,使不受机械和环境应力影响。
现在参照图14,非金属支撑结构12已从引线框架组件162去除,并且引线框架组件162的余留部分被单一元件化,以形成多个半导体元器件150。单个半导体元器件150显示在图14中。
图15是根据本发明另一实施方式的、在制造半导体元器件200(如图19所示)时被用作引线框架的一部分的非金属支撑结构12的截面图。非金属支撑结构12已参照图1被描述。应该注意,用表面活性剂比如树脂处理表面14和16是任选的步骤。根据参照图15所描述的实施方式,优选地,表面14和16不用表面活性剂处理。使用粘合材料204将厚度在50μm到100μm之间的一层导电材料202层压到非金属支撑结构12的表面14上。用于导电层202的合适的材料包括铜、铝、金或其它类似材料。合适的粘合材料204包括环氧树脂、硅烷活性粘合剂或其它类似材料。应该注意,也可以使用与热结合的高压层压来层压导电材料202。
现在参照图16,从导电层202形成包括导电晶片连接垫208和引线框架引线210的半导体元器件区206。根据本发明的实施方式,导电晶片连接垫208和引线框架引线210通过使用如参照图3-5描述的光刻工艺形成。可选择地,导电晶片连接垫208和引线框架引线210可以通过使用激光切割技术或冲压工艺形成,随后去除导电层202的部分,以让导电晶片连接垫208和引线框架引线210彼此电绝缘。
图17是非金属支撑结构12的俯视图,导电晶片连接垫208和引线框架引线210在其上形成。更具体地说,图17显示包括导电晶片连接垫208和引线框架引线210的多个半导体元器件区206。半导体元器件200可以从每个半导体元器件区206制造。非金属支撑结构12、导电晶片连接垫208以及引线框架引线210共同形成引线框架212。图17所示的是半导体元器件区206的2乘2的外围阵列。半导体晶片58通过晶片连接材料(未显示)耦合到对应的导电晶片连接垫208。半导体晶片58和晶片连接材料已参照图5描述。引线键合66将键合垫68连接到对应的引线框架引线210。优选地,单个引线键合将引线框架引线连接到对应的键合垫。然而,本发明不限于此。例如,一个或更多键合垫可以连接到单个引线框架引线。根据图17所示的实施方式,导电晶片连接垫208(如图16所示)和键合垫68被通过引线键合66耦合到引线框架引线210。已参照图17展示和描述了十六条引线框架引线210、十六条引线键合66以及十六个键合垫68,然而,应该了解,本发明不受引线框架引线210、引线键合66和键合垫68的数目限制。虽然单个半导体晶片58被描述为连接到半导体元器件区206和引线框架212,但本发明并不限于此。可以配置引线框架以让多个半导体晶片连接到半导体晶片连接区域,或者可以将一个或更多半导体晶片和一个或更多无源电路元件连接到半导体晶片连接区域。可选择地,半导体晶片连接区域可以被用作无源电路连接区域。
图18是在模制材料70形成在引线框架212、半导体晶片58、引线键合66以及引线框架引线210的上面以形成引线框架组件218之后,沿17中的截面线18-18截取的引线框架212的截面图。图18显示通过晶片连接材料60耦合到导电晶片连接垫208的半导体晶片58,以及将键合垫68连接到对应引线框架引线210的引线键合66。引线框架212被布置在模具中(图中未示),并且模制材料被注入模具以形成半导体晶片58、引线键合66、导电晶片连接垫208以及引线框架引线210之上的密封剂70,来形成引线框架组件218。模制材料70保护半导体晶片58、引线键合66、导电晶片连接垫208以及引线框架引线210,使之不受机械和环境应力的影响。非金属支撑结构12被从导电晶片连接垫208、引线框架引线210以及模制材料70去除。
现在参照图19,非金属支撑结构12已从引线框架组件218去除,并且引线框架组件的余留部分被单一元件化,以形成多个半导体元器件200。
至此,应该了解到,已提供了一种包括引线框架的半导体元器件和一种制造该半导体元器件的方法。引线框架的大部分包括适合用于多种封装的非金属基础结构。使用非金属基础结构的优势在于,它比使用金属基础结构便宜,并且因为引线框架的大部分会被丢弃,因此只会浪费较少的金属。另外的优势是非金属基础结构可以被重利用。此外,热失配导致的应力问题被减到最小,因为引线框架金属量被减少了。
虽然在这里公开了具体的实施方式,但并非意图让本发明受限于所公开的实施方式。本领域的技术人员将会认识到可以作出修改和变更而不背离本发明的实质。本发明意图包含落在所附权利要求范围内的所有这样的修改和变更。
Claims (10)
1.一种制造半导体元器件的方法,包括:
提供具有非金属基础结构和第一主表面及第二主表面的支撑结构;
在所述第一主表面上形成电路元件连接结构;以及
在所述第一主表面上形成至少一个引线框架引线。
2.如权利要求1所述的方法,其中所述非金属基础结构包括纤维素。
3.如权利要求1所述的方法,进一步包括在至少所述第一主表面上形成薄膜,所述薄膜具有相对的面,其中一面是实质疏水的,与之相对的一面是实质亲水的。
4.如权利要求1所述的方法,进一步包括在至少所述第一主表面上形成树脂薄膜。
5.如权利要求1所述的方法,进一步包括将所述电路元件连接结构的一部分嵌入所述支撑结构的第一部分。
6.如权利要求1所述的方法,进一步包括:
在所述第一主表面上形成铜层;
从所述铜层形成电路元件连接结构和多个引线框架引线;
在所述电路元件连接结构和所述多个引线框架引线之上形成模制材料;
去除所述非金属基础结构;以及
去除所述铜层。
7.一种制造半导体元器件的方法,包括:
提供具有非金属基础结构和第一主表面及第二主表面的支撑结构;
在所述第一主表面上形成导电材料层;
将电路元件连接到所述导电材料层的一部分;以及
在所述电路元件上形成密封材料。
8.如权利要求7所述的方法,其中在所述第一主表面上形成导电材料的所述步骤包括:
在所述第一主表面上形成防水层;以及
在所述防水层上非电镀镀上所述导电材料层。
9.一种具有中间结构的半导体元器件,所述中间结构包括:
支撑结构,其具有非金属基础结构和第一主表面及第二主表面;
引线框架引线,其在所述非金属基础结构的第一面上;
电路元件,其在所述第一主表面上,所述电路元件被电耦合到所述引线框架引线;以及
密封材料,其在所述电路元件之上。
10.如权利要求9所述的半导体元器件,其中所述非金属基础部件包含选自包括纤维素、纸和塑料的一组材料中的材料。
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US20090261462A1 (en) * | 2008-04-16 | 2009-10-22 | Jocel Gomez | Semiconductor package with stacked die assembly |
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MY171813A (en) | 2009-11-13 | 2019-10-31 | Semiconductor Components Ind Llc | Electronic device including a packaging substrate having a trench |
KR102077742B1 (ko) * | 2013-02-27 | 2020-02-14 | 삼성전자주식회사 | 반도체 요소 전사 방법 |
KR101665794B1 (ko) * | 2014-12-22 | 2016-10-13 | 현대오트론 주식회사 | 다이 기반의 차량 제어기 전용 반도체 설계 방법 및 이에 의해 제조되는 차량 제어기 전용 반도체 |
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JP6889531B2 (ja) * | 2016-08-05 | 2021-06-18 | マクセルホールディングス株式会社 | 半導体装置用基板およびその製造方法、半導体装置の製造方法 |
US10957635B2 (en) * | 2019-03-20 | 2021-03-23 | Texas Instruments Incorporated | Multi-chip package with high thermal conductivity die attach |
US20230197623A1 (en) * | 2021-12-20 | 2023-06-22 | Advanced Micro Devices, Inc. | Electronic device including an integrated circuit die and a support structure |
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US5826328A (en) | 1996-03-25 | 1998-10-27 | International Business Machines | Method of making a thin radio frequency transponder |
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US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
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DE102006030581B3 (de) * | 2006-07-03 | 2008-02-21 | Infineon Technologies Ag | Verfahren zum Herstellen eines Bauelements |
-
2007
- 2007-10-23 MY MYPI20071826A patent/MY146344A/en unknown
-
2008
- 2008-03-17 US US12/049,909 patent/US7939380B2/en active Active
- 2008-08-20 CN CN2008102110496A patent/CN101419920B/zh not_active Expired - Fee Related
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