CN101416316B - 混合晶向沟道场效应晶体管 - Google Patents

混合晶向沟道场效应晶体管 Download PDF

Info

Publication number
CN101416316B
CN101416316B CN2006800142167A CN200680014216A CN101416316B CN 101416316 B CN101416316 B CN 101416316B CN 2006800142167 A CN2006800142167 A CN 2006800142167A CN 200680014216 A CN200680014216 A CN 200680014216A CN 101416316 B CN101416316 B CN 101416316B
Authority
CN
China
Prior art keywords
source
semiconductor
crystal orientation
drain region
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2006800142167A
Other languages
English (en)
Other versions
CN101416316A (zh
Inventor
约耳·P.·德索扎
德温得拉·K.·萨达纳
凯瑟琳·L.·萨恩格
宋均镛
杨敏
尹海洲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101416316A publication Critical patent/CN101416316A/zh
Application granted granted Critical
Publication of CN101416316B publication Critical patent/CN101416316B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本发明涉及混合晶向沟道场效应晶体管，在结合界面(360)上方的源/漏区具有的晶向，而结合界面(360)下方的源/漏区具有下部半导体(370)的晶向，使得源/漏区的每个部分的晶向与横向相邻的半导体材料的晶向相同。可选的源/漏延伸区(392)被整个地设置在上部半导体(350)中。可选地，结合界面(360)位于接近源/漏区(380)的底部，使得源/漏区(380)大部分处于上部半导体层(350)中。

Description

混合晶向沟道场效应晶体管
技术领域
本发明涉及互补金属氧化物半导体(CMOS)电路，其中n型场效应晶体管(nFET)被放置在具有对于电子迁移率最优的晶向的半导体中，而p型场效应晶体管(pFET)被放置在具有对于空穴迁移率最优的晶向的半导体中。更具体地，本发明涉及一种FET结构，其中完全在最优晶向的半导体中形成的FET的性能优势是通过以下结构实现的，在该结构中，只需要将该器件的沟道放置于具有最优晶向的半导体中。本发明还涉及将这些FET合并入混合晶向衬底上的CMOS电路中的方法。 
背景技术
现有半导体技术的互补金属氧化物半导体(CMOS)电路包括利用电子载流子工作的n型场效应晶体管(nFET)，和利用空穴载流子工作的p型场效应晶体管(pFET)。CMOS电路一般在具有单晶向、通常是(100)的Si晶片上制造。然而，因为电子在具有(100)表面晶向的Si中具有更高迁移率(相比于(110)晶向)而空穴在具有(110)表面晶向的Si中具有更高迁移率(相比于(100)晶向)，所以在混合晶向的衬底上制造CMOS电路以使得nFET可以被形成于具有(100)晶向的Si中而pFET可以被形成于具有(110)晶向的Si中是很有利的。 
一些现有技术的混合晶向衬底的例子如图1A到1G所示。所有图示的现有技术衬底包括共面、或者大致共面(substantiallycoplanar)的、不同晶向的单晶半导体的表面区，用10和20表示，并通过绝缘体填充隔离槽(insulator-filled isolation trench)30来分开。(在这里和接下来的附图中，用不同方向的交叉阴影线表示不同 的半导体晶向。)基础衬底(base substrate)40是与半导体区20具有相同晶向的单晶半导体。基础衬底50一般为半导体或绝缘体，晶向不限。单晶半导体区60、70和80的晶向与半导体区20的晶向相同。半导体区10和20包括用于图1A和1F的结构的体衬底的一部分；用于图1C、1D、1E和1G的结构的具有掩埋绝缘层90和/或局部掩模绝缘层100的绝缘体上硅(SOI)衬底的一部分；以及用于图1B结构的具有局部掩埋绝缘层110的混合体/SOI衬底的一部分。图1D的结构具有位于半导体区10与下方的半导体区70之间的绝缘层，而图1C和1G的结构具有位于半导体区10与下方的半导体区60和80之间的直接半导体-半导体结合(directsemiconductor-to-semiconductor bonded，DSB)界面。 
如图1A到1G所示的衬底的制造方法有很多种，但是所有方法一般都开始于被结合到(j’k’l’)晶向半导体处理晶片(handlewafer)或者处理晶片层上的(jkl)晶向半导体层。根据制造方法，结合可以为直接的(例如，生成半导体-半导体界面)或者间接的(例如，这样一种结合，其中至少在某些区域内氧化物或其它绝缘层保留在结合面上)。为了产生图1A到1E的衬底结构，用具有衬底的(j’k’l’)晶向的半导体替代该(jkl)晶向半导体层的选定区域(连同任意暴露的掩埋绝缘体区一起，如果需要的话)。这可以通过例如，沟槽/外延生长工艺(trench/epitaxial-growth process)(例如，如2004年12月23日公开的美国专利申请公开US2004/0256700A1中所述)来完成，其中(jkl)晶向半导体首先在选定区域中被蚀刻掉从而形成暴露下方的(j’k’l’)晶向半导体的开口然后被具有衬底晶向的外延生长半导体替代。替代地，还可以使用非晶化/模板再晶化(amorphization/templated recrystallization，ATR)工艺(例如，如2005年6月2日公开的美国专利申请公开US2005/0116290A1中所述)，其中(jkl)晶向半导体的选定区域首先被非晶化到低于DSB界面的深度然后使用下方的(j’k’l’)晶向半导体作为模板来外延地再晶化。可以执行其它处理步骤以引入或增强绝缘体埋层90、100和110， 例如，如美国专利申请公开US2005/0116290A1和(2006年2月2日公开的)US2006/0024931A1中所述。图1F到1G的结构一般会通过原位结合技术(in-place bonding technique)或者简单地将(jkl)晶向半导体层直接结合到(j’k’l’)晶向衬底层上的区域蚀刻掉来制造。 
目前，制造于这种混合晶向衬底中的CMOS电路中的所有nFET和pFET都有一个共同的特点：每个FET的沟道和源/漏区都被形成于具有单晶向的半导体中，该晶向被选择用来优化该FET载流子的迁移率。这种现有FET的实例如图2所示，其中形成于单晶向半导体210中的FET 200包括与绝缘体填充隔离槽30、源/漏延伸区230、半导体沟道区(在区域240中)、栅电介质250和导电的栅260邻接的源和漏区220。(为了清楚，后续附图中的源/漏区和源/漏延伸区可以用与它们的边界相关联的附图标记来标识，即使实际上是这些边界中的半导体材料组成了实际的源/漏和源/漏延伸区。)还可以包括其它通常的和/或优选的FET部件诸如阱注入区、大角度注入区、栅极上的侧壁间隔物、抬高的源/漏(raised source/drain)、栅接触、源/漏接触、产生沟道应力的替代源/漏区(replacementsource/drain region)和/或重叠层(overlayer)等，但并未在图2中显示。 
对于具有图1B、1D或1E结构的混合晶向衬底，其中单晶向半导体10和20在下方被同晶向(对于半导体20的情况)的体半导体(bulk semiconductor)或者下方的绝缘体层(underlying layerof insulator)(对于半导体20的情况)所包围，具有图2的几何结构的FET不存在问题。然而，对于具有图1A、1C、1F和1G结构的混合晶向衬底，其中(jkl)晶向区10在下方被(j’k’l’)晶向区60、70或80包围，这样的FET几何结构就不太兼容，因为该FET必须要“薄”(即，源/漏区必须比结合的(jkl)晶向半导体层更浅)，或者，等价地，被放置于比源/漏区更厚的(jkl)晶向DSB层中。这种限制会有很大的局限性：体半导体中的很多CMOS电路使用具有深源/漏的FET，而当DSB层薄时更容易形成混合晶向衬底。对于由ATR 技术制造的混合衬底而言尤其需要更薄的DSB层，因为再晶化半导体材料的缺陷率会随非晶化深度(amorphization depth)(该深度被约束为要大于DSB层的厚度)而增加。例如，N.Burbure和K.S.Jones(Mat.Res.Soc.Symp.Proc.810 C4.19.1，2004)指出，在ATR之后遗留在用氧化物填充槽(oxide-filled trench)图案化的硅衬底上的角缺陷(corner defect)的横向尺寸(lateral dimension)直接与非晶化注入的厚度成比例。 
因此需要一种FET结构，所述FET结构具有在最优晶向的半导体中制造的FET的优势和性能而不需要在最优晶向的半导体中制造整个FET(即其源/漏和沟道)。 
发明内容
因此本发明的目标是提供一种FET结构，其具有在最优晶向的半导体中被整体制造的现有FET的优势和性能而不需要在最优晶向的半导体中制造整个FET(即其源/漏和沟道)。 
本发明的目标是提供一种FET结构，其具有在位于混合晶向衬底中的最优晶向的半导体中被整体制造的现有FET的优势和性能，其中对于FET迁移率最优的晶向的半导体层尽可能薄。 
本发明的另一个目标是提供一种体和/或SOI混合晶向衬底中的CMOS电路，其中所述的CMOS电路包括至少满足一个上述目标的至少一个本发明的FET、和至少一种其它的现有FET。 
结合上述列出的和其它目标，提供一种FET结构，其中该FET的沟道被包含于具有第一单晶向的上部半导体层(uppersemiconductor layer)中，而该FET的源/漏区的至少一些部分被包含于具有不同晶向的下方的直接半导体结合(underlyingdirect-semiconductor-bonded)单晶向半导体中。更一般地，提供一种FET结构，其中包含源/漏区的半导体的至少一些部分的晶向会不同于包含沟道的半导体的至少一些部分的晶向。下方的单晶向半导体可以为体半导体或者绝缘体上半导体(semiconductor-on-insulator) 层。对于Si、Ge和SiGe合金半导体的情况，晶体取向一般会选自包括(110)、(111)和(100)的组。 
提供了本发明的基本FET结构的几种实施方案。例如，直接结合表面半导体层和下方不同晶向半导体(underlyingdifferently-oriented semiconductor)层可以包括相同或不同的半导体材料，例如Si和SiGe。给定晶向的半导体区还可以包括多于一种的半导体材料，诸如层状半导体。包括源、漏和沟道区的半导体可以为应变的、非应变的或者应变和非应变的复合体。如果是原来的源/漏区的一部分被不同的半导体材料所替代的情况，例如Si源/漏区被SiGe替代，那么源/漏区也可以包括与横向相邻的半导体区的材料不同的材料。上述与现有FET有关的其它通常的和/或有益的特征也可以被合并入本发明的FET结构中。 
本发明也提供体和/或SOI混合晶向衬底中的CMOS电路，其中所述的CMOS电路包括源/漏和沟道没有被完全包含于单晶半导体的单晶向中(与上述发明的FET结构一致)的至少一个FET，以及源/漏和沟道区被完全包含于单晶半导体的单晶向中(与上述现有的FET结构一致)的至少一其它FET。 
附图说明
这些及其它的特点、方面和优势通过以下本发明的详细描述会更加显而易见以及更容易理解，其中： 
图1A到1G为横截面示意图，显示了现有技术的平面混合晶向半导体衬底(planar hybrid-orientation semiconductorsubstrate)结构的例子； 
图2为横截面示意图，显示了现有几何结构的FET，其中FET的沟道和源/漏区被形成于具有单晶向的半导体中，该晶向优选地被选择用来优化该FET的载流子迁移率； 
图3A到3D为横截面示意图，显示了本发明的FET中源/漏区的上部具有与沟道相同的晶向，而源/漏区的下部具有与沟道不同 的晶向的情况； 
图4A到4E为横截面示意图，显示了本发明的FET中整个源/漏区具有与沟道不同的晶向的情况； 
图5A到5C为横截面示意图，显示了本发明的FET中源/漏区也可以包括与横向相邻的半导体区域的不同材料的情况； 
图6A到6D为横截面示意图，显示了在不同的混合晶向衬底上CMOS电路的一个nFET和一个pFET，其中FET中的一个是本发明的FET而另一个是现有FET； 
图7A到7C为横截面示意图，显示了非晶化/模板再晶化法，通过该方法使得包含两个不同晶向的单晶半导体区的FET的源/漏区可以被转化为只包含一个单晶半导体区的源/漏区；以及 
图8A到8D为横截面示意图，显示了沟槽/外延生长法，通过该方法使得包含两种不同晶向单晶半导体区的FET的源/漏区可以被替换为只包含一个单晶半导体区的源/漏区。 
具体实施方式
本发明提供了一种FET结构，其中包含源/漏区的半导体的至少一些部分的晶向不同于包含沟道的半导体的至少一些部分的晶向，这会被更加详细地描述。发明的FET结构的下方的单晶半导体可以为体半导体或者绝缘体上半导体层。图3到5的实施方案显示了下方的单晶半导体为体半导体的情况。 
图3A到3D显示本发明的FET源/漏区的上部具有与沟道相同的晶向，而源/漏区的下部具有与沟道不同的晶向的情况。图3A到3D的FET 300、310、320和330包含具有第一晶向的上方单晶半导体层350，它在结合界面360处与具有不同于第一晶向的第二晶向的下部单晶半导体层370相接合。与图2的FET 200相似，图3A到3D的每个FET中的元件包括栅导体(gate conductor)260、栅电介质230和绝缘体填充隔离槽30。图3A到3D的每个FET还包括上部半导体350(在区域375中)中的半导体沟道区、源/漏区380、382、 384或386，以及可选的源/漏延伸区392、394、396或398。 
在图3A到3D中，结合界面360上方的源/漏区具有上部半导体350的晶向而结合界面360下方的源/漏区具有下部半导体370的晶向，从而使得源/漏区的每一部分都具有跟与其横向相邻的半导体材料相同的晶向。FET 300、310、320和330的区别只在于结合界面360相对于源/漏区底部的位置。在FET 300、310和320中，可选的源/漏延伸区392、394和396完全处于上部半导体层350中。在FET300中，结合界面360位于接近源/漏区380的底部，使得源/漏区380大部分处于上部半导体层350中。在FET 310中，结合界面360所处的深度大约相当于源/漏厚度的一半，使得源/漏区382近似地在上部半导体350和下部半导体370之间平分。在FET 320中，结合界面360位于接近源/漏区384的上部，深度大约等于可选的源/漏延伸区396(如果有的话)的底部，使得源/漏区384大部分处于下方半导体层370中。在FET 330中，结合界面360离表面更近(相比其在FET320中的位置)。FET 330中的源/漏区386几乎完全位于下方半导体370中，而可选的源/漏延伸区398(如果有的话)近似地在上方半导体350和下方半导体370之间平分。 
图4A到4E显示了本发明的FET中整个源/漏区具有与沟道不同的晶向的情况。图4A到4E的FET 400、410、420、430和440包含具有第一晶向的上方单晶半导体层450，它在结合界面460处与具有不同于第一晶向的第二晶向的下方单晶半导体层470相接合。图4的FET的元件与图2中的FET 200的元件类似，包括栅导体260、栅电介质230和绝缘体填充隔离槽30。图4A到4E的每个FET中还包括上部单晶半导体450(在区域475中)中的半导体沟道区、源/漏区480、482、484、486或488，以及可选的源/漏延伸区490、492、494、496或498。虚线460’显示假如结合界面460在图4A到4D中横向延展到源/漏区480、482、484或486中、或者在图4E中横向延展到源/漏区488下面的半导体区499中时结合界面460的位置。使结合界面460从源/漏区中消失的工艺步骤会在稍后结合图7A到7C进 行讨论。 
在图4A到4E中，沟道区475和可选的源/漏延伸区490、492、494、496和498具有上部半导体450的晶向，而全部源/漏区具有下部半导体470的晶向。与图3A到3D的FET相反，虚线460’上方的源/漏区的晶向不同于横向相邻的半导体的晶向。图4A到4D的FET 400、410、420和430的区别只在于结合界面460相对于源/漏区底部的位置。在FET 400、410、420和440中，可选的源/漏延伸区490、492、494和498完全位于上部半导体层450中。在FET 400中，结合界面460位于接近源/漏区480的底部，使得源/漏区480大部分处于毗邻上部半导体450的下部半导体层470的上部区域中。在FET410中，结合界面460所处的深度大约相当于源/漏厚度的一半，使得源/漏区482近似地在上部半导体450和下部半导体470之间平分。在FET 420中，结合界面460位于接近源/漏区484的上部，深度大约等于可选的源/漏延伸区494(如果有的话)的底部，使得源/漏区484大部分处于下部半导体层470中。在FET 430中，结合界面460离表面更近(相比其在FET 420中的位置)。FET 430中的源/漏区486几乎完全位于下部半导体470中，而可选的源/漏延伸区496(如果有的话)近似地在上部半导体450和下部半导体470之间平分。 
图4E的FET也包括位于源/漏区498下方和虚线460’上方的半导体区499。形成区域498和499的工艺步骤会在稍后结合图7A到7C进行讨论。 
图5A到5C显示了本发明的FET中的源/漏区(和/或源/漏延伸区)的至少一些部分包括与横向相邻的半导体区域不同的半导体材料的情况，也就是如果原来的源/漏区的一部分被去除然后被替换为一种或多种不同半导体材料的情况。图5A到5C的FET 500、510和520包含具有第一晶向的上部单晶半导体层550，它在结合界面560处与具有不同于第一晶向的第二晶向的下部单晶半导体层570相接合。图5A到5C的FET的元件与附图2中FET 200的元件类似，包括栅导体260、栅电介质230和绝缘体填充隔离槽30。附图5A到5C 的每个FET中还包括上部单晶半导体550(在区域575中)中的半导体沟道区、源/漏区580、582或584，以及可选的源/漏延伸区590、592或594。在图5A中，在FET 500的源/漏区580中的半导体595的材料具有下部半导体570的晶向，并且不同于上部半导体层的材料。图5B的FET 510与附图5A的FET 500的相似之处在于源/漏区582中的半导体597的材料具有下部半导体570的晶向，并且不同于上部半导体层550的材料。FET 510与FET 500的不同之处在于FET 510中的半导体597没有像FET 500的半导体595那样在界面560下方延伸。在图5C中，在FET 520的源/漏区584中的半导体599的材料具有上部半导体550的晶向并且不同于上部半导体层的材料。形成区域595、597和599的工艺步骤会在稍后结合图8A到8D进行讨论。 
图5A到5C的FET几何结构可以被用于产生应变沟道(strained channel)，例如通过去除Si源/漏材料并将其替换为SiGe。该方法尤其优选地用于当上部半导体为(110)晶向的Si而源/漏区被替换为以具有(100)晶向的下方的Si半导体为模板的(100)晶向的SiGe的情况，因为(100)晶向的SiGe预计比(110)晶向的SiGe更容易生长。 
图3到5中显示的源/漏延伸区具有与沟道相同的晶向。虽然该晶向对于外延而言是优选的晶向(为了避免外延和沟道之间的晶界缺陷(grain boundary defect))，但是可能有些情况中会要求延伸区具有与源/漏区中的横向相邻的半导体相同的晶向(当该晶向不同于沟道晶向时)。具有该特征的实施方案也在本发明的范围内。 
直接结合表面半导体层、下方的不同晶向半导体和源/漏区中的任何其它半导体可以包括相同或不同的半导体材料，并且可以选自包括Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP以及其它III-V或II-VI族化合物半导体的组。上述半导体材料的层状化合物或者合金(例如，SiGe上的Si层)，其具有或者不具有一种或多种掺杂物，在这里也被预先考虑了。如果需要的话，包括源极、漏极、沟道和其它半导体区的半导体可以用As、B、C、P、Sb和/或其 它元素进行掺杂。包括源极、漏极和沟道的半导体可以是应变的、非应变的或者应变和非应变的复合体。对于Si、Ge和SiGe合金半导体的情况，晶体取向一般会选自包括(110)、(111)和(100)的组。 
上述与现有FET(阱注入区、大角度注入区、栅极上的侧壁间隔物、抬高的源/漏、栅接触、源/漏接触、产生沟道应力的替代源/漏区和/或重叠层等)以及源/漏和源/漏延伸区注入的更优化定位(more optimized positioning)有关的其它通常的和/或有益的特点也可以被合并入本发明的FET结构中。 
在所有情况中，本发明的FET结构都包括复合半导体区，该复合半导体区包含间隔开的掺杂的源和漏区以及位于所述源和漏区之间的沟道、位于所述沟道上的栅电介质以及位于所述栅电介质上的导电的栅，其中在所述栅的下方的所述复合半导体区包括具有第一晶向的上部单晶半导体和具有第二晶向的下部单晶半导体，所述上部和下部半导体在结合界面处直接接触；所述沟道的至少一些部分位于具有所述第一晶向的所述上部半导体中，以及所述源和漏区的至少一些部分位于具有所述下部半导体的晶向的半导体中。 
在本发明的另一方面，在混合晶向衬底中提供CMOS电路，其中所述的CMOS电路包括其源/漏和沟道没有被完全包含于单晶半导体的单晶向中(即本发明的FET)的至少一个FET，和其源/漏和沟道区被完全包含于单晶半导体的单晶向中(即现有的FET)的至少一个其它FET。如图6A到6D中所示，这种CMOS电路可以被放置于具有类体特性(bulk-like property)(例如，图1A和1F的衬底，如图6A和6B所示)、或者具有绝缘体上半导体特性(例如，图1C和1G的衬底，如图6C和6D所示)的混合晶向衬底上。图6A到6D的FET 600和610分别对应于本发明的FET和现有的FET；FET600和610中一个的为nFET而另一个为pFET。 
制造混合晶向衬底、本发明的FET结构以及包含它们的CMOS电路的工艺步骤是现有技术中通常已知的。仅有的需要用来制造本发明的FET和CMOS电路的额外步骤是选择产生在DSB层底部 下方延伸的注入区的源/漏注入条件。然而，值得详细描述使FET的源/漏区上部可以用不同于沟道的晶向和/或材料来完成的方法。 
图7A到7C显示了非晶化/模板再晶化法，通过该方法使得包含两个不同晶向单晶半导体区的FET的源/漏区可以被转化为只包含一个单晶半导体区的源/漏区。图7A显示了部分完成的FET结构640，包含具有第一晶向的上部单晶半导体层650，它在结合界面660处与具有不同于第一晶向的第二晶向的下部单晶半导体层670相接合。结构640的元件与图2中FET 200的元件类似，包括栅导体260、栅电介质230和绝缘体填充隔离槽30。区域680(用虚线标出)表示源和漏区的期望位置。图7B显示了使用栅导体260作为掩模进行了离子注入685并创建非晶区690的图7A的结构。注入可以只是非晶化(例如，注入到Si中的Si+或者Ge+)或者是非晶化和掺杂(例如，单独注入到Si中的B+、P+或As+，或者结合注入到Si中的Si+或Ge+)。非晶区690然后通过固相外延再晶化为下部半导体670的晶向，以形成半导体区695。像图4A的FET 400那样的结构可以在非晶化注入与掺杂注入具有相同深度时被形成，而像图4E的FET 440那样的结构可以在掺杂注入比非晶化注入更浅的条件下被形成。 
图8A到8D显示了沟槽/外延生长法，通过该方法使得包含两种不同晶向单晶半导体区的FET的源/漏区可以被替换为只包含一个单晶半导体区的源/漏区。图8A显示了在栅导体260的顶面上具有额外的栅钝化层710的图7A的结构。图8B显示了电介质侧壁间隔物(dielectric sidewall spacer)720已经形成于栅导体260的侧面之后的图8A的结构。图8C显示了在邻近期望的源/漏区680的半导体材料已经被蚀刻到低于结合界面660的深度以形成空腔730之后的图8B的结构。然后将空腔730用具有下方半导体670的晶向的外延生长半导体740来填充，其后栅钝化层710和间隔物720被去除以形成图8D的结构。图7A到7C和8A到8D的工艺步骤可以结合起来以制造诸如图5C的FET 520那样的结构。 
在本发明已经结合其优选实施方案被详细的说明和描述，但本领域技术人员可以理解的是可以在本发明的精神和范围内做出前述的和其它的形式上和细节上的改变。因此注意本发明并不只限于所描述和说明的具体形式和细节，而是在所附的权利要求的范围中。 

Claims (33)

1.一种场效应晶体管FET，包括：
复合半导体区，包括间隔开的掺杂的源和漏区和位于所述源和漏区之间的沟道；
位于所述沟道上的栅电介质，以及
位于所述栅电介质上的导电的栅，在所述栅的下方的所述复合半导体区包括具有第一晶向的上部单晶半导体和具有第二晶向的下部单晶半导体，所述第一晶向不同于所述第二晶向，所述上部和下部半导体在结合界面处直接接触并且所述沟道仅位于具有所述第一晶向的所述上部单晶半导体中，所述源和漏区的全部具有所述第二晶向。
2.根据权利要求1所述的场效应晶体管，其中，所述结合界面上方的源/漏区具有沟道的晶向而所述结合界面下方的源/漏区具有下部半导体的晶向。
3.根据权利要求1所述的场效应晶体管，其中，所述结合界面上方的至少一部分源/漏区的晶向不同于沟道的晶向。
4.根据权利要求1所述的场效应晶体管，还包括阱注入区、大角度注入区、所述栅上的侧壁间隔物、抬高的源/漏、栅接触、源/漏接触、产生沟道应力的替代源/漏区和/或重叠层、或者源/漏延伸区中的至少一种。
5.根据权利要求1所述的场效应晶体管，其中，所述下部半导体为体半导体晶片。
6.根据权利要求1所述的场效应晶体管，其中，所述下方半导体为绝缘体上半导体层。
7.根据权利要求1所述的场效应晶体管，其中，所述上部和下部半导体为相同的半导体材料。
8.根据权利要求1所述的场效应晶体管，其中，所述上部和下部半导体为不同的半导体材料。
9.根据权利要求1所述的场效应晶体管，其中，所述上部和所述下部半导体包括Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP、其它III-V或II-VI族化合物半导体或者上述半导体材料的层状组合物和合金。
10.根据权利要求1所述的场效应晶体管，其中，所述上部和所述下部半导体包括至少一种掺杂剂。
11.根据权利要求1所述的场效应晶体管，其中，所述上部和所述下部半导体包括应变区。
12.根据权利要求1所述的场效应晶体管，其中，包括源、漏和沟道区的上部和下部半导体是应变的、非应变的、或者应变和非应变区的复合体。
13.根据权利要求1所述的场效应晶体管，其中，所述上部和下部半导体包括Si、SiGe合金或者Ge。
14.根据权利要求13所述的场效应晶体管，其中，所述第一和第二晶向从包括(100)、(110)和(111)的组中选择。
15.根据权利要求1所述的场效应晶体管，其中，所述源和漏区的至少一些部分包括与横向相邻的半导体区不同的半导体材料。
16.根据权利要求15所述的场效应晶体管，其中，所述沟道包括Si而所述横向相邻的源/漏区包括SiGe半导体。
17.根据权利要求1所述的场效应晶体管，其中，所述沟道在所述结合界面之下延伸。
18.根据权利要求1所述的场效应晶体管，还包括源/漏延伸区，所述源/漏延伸区具有与所述沟道相同或不同的晶向。
19.一种CMOS电路，包括至少一个场效应晶体管FET，所述场效应晶体管包括具有间隔开的掺杂的源和漏区和位于该源和漏区之间的沟道的复合半导体区、位于所述沟道上的栅电介质以及位于所述栅电介质上的导电的栅，其中在所述栅的下方的所述复合半导体区包括具有第一晶向的上部单晶半导体和具有第二晶向的下部单晶半导体，所述第一晶向不同于所述第二晶向，所述上部和下部半导体在结合界面处直接接触并且所述沟道仅位于具有所述第一晶向的所述上部单晶半导体中，而所述源和漏区的全部具有所述第二晶向。
20.根据权利要求19所述的CMOS电路，其中，所述结合界面上方的源/漏区具有沟道的晶向而所述结合界面下方的源/漏区具有下部半导体的晶向。
21.根据权利要求19所述的CMOS电路，其中，所述结合界面上方的至少一部分源/漏区的晶向不同于沟道的晶向。
22.根据权利要求19所述的CMOS电路，还包括阱注入区、大角度注入区、所述栅上的侧壁间隔物、抬高的源/漏、栅接触、源/漏接触、产生沟道应力的替代源/漏区和/或重叠层、或者源/漏延伸区中的至少一种。
23.根据权利要求19所述的CMOS电路，其中，所述下部半导体为体半导体晶片或者绝缘体上半导体。
24.根据权利要求19所述的CMOS电路，其中，所述上部和下部半导体为相同或不同的半导体材料。
25.根据权利要求19所述的CMOS电路，其中，所述上部和所述下部半导体包括Si、SiC、SiGe、SiGeC、Ge合金、Ge、C、GaAs、InAs、InP、其它III-V或II-VI族化合物半导体或者上述半导体材料的层状组合物和合金。
26.根据权利要求19所述的CMOS电路，其中，所述上部和所述下部半导体包括至少一种掺杂剂。
27.根据权利要求19所述的CMOS电路，其中，所述上部和所述下部半导体包括应变区。
28.根据权利要求19所述的CMOS电路，其中，包括源、漏和沟道区的上部和下部半导体是应变的、非应变的、或者应变和非应变区的复合体。
29.根据权利要求19所述的CMOS电路，其中，所述上部和下部半导体包括Si、SiGe合金或者Ge。
30.根据权利要求29所述的CMOS电路，其中，所述第一和第二晶向从包括(100)、(110)和(111)的组中选择。
31.根据权利要求19所述的CMOS电路，其中，所述源和漏区的至少一些部分包括与横向相邻的半导体区不同的半导体材料。
32.根据权利要求31所述的CMOS电路，其中，所述沟道包括Si而所述横向相邻的源/漏区包括SiGe半导体。
33.根据权利要求19所述的CMOS电路，还包括另一种FET，所述另一种FET的源/漏和沟道区被完全包含于单晶半导体的单晶向中。
CN2006800142167A 2005-04-27 2006-04-21 混合晶向沟道场效应晶体管 Active CN101416316B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/116,053 US7465992B2 (en) 2005-04-27 2005-04-27 Field effect transistor with mixed-crystal-orientation channel and source/drain regions
US11/116,053 2005-04-27
PCT/US2006/015107 WO2006116098A2 (en) 2005-04-27 2006-04-21 Mixed -crystal-orientation channel field effect transistors

Publications (2)

Publication Number Publication Date
CN101416316A CN101416316A (zh) 2009-04-22
CN101416316B true CN101416316B (zh) 2011-06-29

Family

ID=37215304

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800142167A Active CN101416316B (zh) 2005-04-27 2006-04-21 混合晶向沟道场效应晶体管

Country Status (6)

Country Link
US (1) US7465992B2 (zh)
EP (1) EP1875508A4 (zh)
JP (1) JP4474479B2 (zh)
CN (1) CN101416316B (zh)
TW (1) TWI373135B (zh)
WO (1) WO2006116098A2 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531392B2 (en) * 2006-02-27 2009-05-12 International Business Machines Corporation Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same
US20070224785A1 (en) * 2006-03-21 2007-09-27 Liu Mark Y Strain-inducing film formation by liquid-phase epitaxial re-growth
US7642197B2 (en) * 2007-07-09 2010-01-05 Texas Instruments Incorporated Method to improve performance of secondary active components in an esige CMOS technology
US20090057816A1 (en) * 2007-08-29 2009-03-05 Angelo Pinto Method to reduce residual sti corner defects generated during spe in the fabrication of nano-scale cmos transistors using dsb substrate and hot technology
JP5178103B2 (ja) * 2007-09-12 2013-04-10 株式会社東芝 半導体装置およびその製造方法
US20090283829A1 (en) * 2008-05-13 2009-11-19 International Business Machines Corporation Finfet with a v-shaped channel
JP2011146691A (ja) * 2009-12-15 2011-07-28 Sumitomo Chemical Co Ltd 半導体基板、半導体デバイスおよび半導体基板の製造方法
US9577079B2 (en) * 2009-12-17 2017-02-21 Infineon Technologies Ag Tunnel field effect transistors
CN102543744B (zh) * 2010-12-29 2014-12-24 中芯国际集成电路制造(北京)有限公司 晶体管及其制作方法
US8878251B2 (en) 2012-10-17 2014-11-04 Seoul National University R&Db Foundation Silicon-compatible compound junctionless field effect transistor
US9263586B2 (en) 2014-06-06 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure
US9520496B2 (en) * 2014-12-30 2016-12-13 International Business Machines Corporation Charge carrier transport facilitated by strain
US9768254B2 (en) 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
KR102618493B1 (ko) 2018-08-03 2023-12-27 삼성전자주식회사 반도체 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020130378A1 (en) * 2001-03-15 2002-09-19 Leonard Forbes Technique to mitigate short channel effects with vertical gate transistor with different gate materials
US20040173812A1 (en) * 2003-03-07 2004-09-09 Amberwave Systems Corporation Shallow trench isolation process
US20040217352A1 (en) * 2003-04-29 2004-11-04 Micron Technology, Inc. Strained semiconductor by wafer bonding with misorientation
CN1581497A (zh) * 2003-08-05 2005-02-16 国际商业机器公司 采用晶片键合和simox工艺的不同晶体取向自对准soi
CN1591826A (zh) * 2003-08-25 2005-03-09 国际商业机器公司 集成半导体结构和应变绝缘硅的制造方法及应变绝缘硅

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04335538A (ja) * 1991-05-10 1992-11-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7034362B2 (en) * 2003-10-17 2006-04-25 International Business Machines Corporation Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020130378A1 (en) * 2001-03-15 2002-09-19 Leonard Forbes Technique to mitigate short channel effects with vertical gate transistor with different gate materials
US20040173812A1 (en) * 2003-03-07 2004-09-09 Amberwave Systems Corporation Shallow trench isolation process
US20040217352A1 (en) * 2003-04-29 2004-11-04 Micron Technology, Inc. Strained semiconductor by wafer bonding with misorientation
CN1581497A (zh) * 2003-08-05 2005-02-16 国际商业机器公司 采用晶片键合和simox工艺的不同晶体取向自对准soi
CN1591826A (zh) * 2003-08-25 2005-03-09 国际商业机器公司 集成半导体结构和应变绝缘硅的制造方法及应变绝缘硅

Also Published As

Publication number Publication date
WO2006116098A3 (en) 2008-10-30
US7465992B2 (en) 2008-12-16
CN101416316A (zh) 2009-04-22
US20060244068A1 (en) 2006-11-02
JP2008539593A (ja) 2008-11-13
EP1875508A2 (en) 2008-01-09
EP1875508A4 (en) 2009-08-05
TWI373135B (en) 2012-09-21
TW200707736A (en) 2007-02-16
WO2006116098A2 (en) 2006-11-02
JP4474479B2 (ja) 2010-06-02

Similar Documents

Publication Publication Date Title
CN101416316B (zh) 混合晶向沟道场效应晶体管
US7034362B2 (en) Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
CN100411180C (zh) 半导体结构及制造半导体结构的方法
CN100378917C (zh) 制造应变含硅混合衬底的方法以及含硅混合衬底
US7915100B2 (en) Hybrid orientation CMOS with partial insulation process
US7368354B2 (en) Planar substrate devices integrated with FinFETs and method of manufacture
CN101140933B (zh) 半导体器件以及制造半导体器件的方法
CN101454889B (zh) 使用体半导体晶片形成改善的soi衬底
JP2007258485A (ja) 半導体装置及びその製造方法
KR20070024581A (ko) 다수 반도체 층들을 갖는 반도체 디바이스
US7385257B2 (en) Hybrid orientation SOI substrates, and method for forming the same
US7479410B2 (en) Hybrid-orientation technology buried n-well design
US20180337198A1 (en) Systems and methods for a semiconductor structure having multiple semiconductor-device layers
TW201926711A (zh) 完全空乏型絕緣層上覆矽（ｆｄｓｏｉ）上的橫向雙擴散金屬氧化半導體（ｌｄｍｏｓ）元件致能高輸入電壓
US7820523B2 (en) Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor
EP1049156B1 (en) Manufacturing process of integrated SOI circuit structures
US20120286329A1 (en) SOI FET with embedded stressor block

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171121

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171121

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right