CN101359625A - Method for preparing polycrystal SiGe gate nano-scale CMOS integrated circuit based on multilayered auxiliary structure - Google Patents

Method for preparing polycrystal SiGe gate nano-scale CMOS integrated circuit based on multilayered auxiliary structure Download PDF

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CN101359625A
CN101359625A CNA2008101509297A CN200810150929A CN101359625A CN 101359625 A CN101359625 A CN 101359625A CN A2008101509297 A CNA2008101509297 A CN A2008101509297A CN 200810150929 A CN200810150929 A CN 200810150929A CN 101359625 A CN101359625 A CN 101359625A
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CN100585835C (en
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张鹤鸣
戴显英
舒斌
宣荣喜
胡辉勇
宋建军
王冠宇
徐小波
屈江涛
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Xidian University
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Abstract

The invention discloses a method for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid and is based on a multi-layer assistant structure. The method includes the following steps: fabricating an N/P well and growing a Poly-SiGe/SiO2/Poly-Si multi-layer structure on the N/P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching the SiN layer on the surface, except the SiN at the side of the window; etching the SiN on the surface of the substrate; based on the etching ratio of Poly-Si to SiN (11:1), etching the Poly-Si at the surface of SiN; based on the etching ratio of SiO2 to SiN(4:1) and the etching ratio of Poly-SiGe to SiN, etching the SiO2 and Poly-SiGe on the surface except on the side wall of the SiN so as to form an n/p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n/p MOSFET grid so as to form an n/p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The invention can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

Prepare the polycrystal SiGe gate nano-scale CMOS integrated circuit method based on multilayered auxiliary structure
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of existing micron order Si integrated circuit fabrication process that utilizes, make the method for nanoscale Si integrated circuit.
Background technology
Now, information technology has become the core technology of national economy, and it serves the national economy every field, and microelectric technique is the key of information technology, and integrated circuit is the key in the key especially.Integrated circuit is since 1958 come out, and development speed is surprising, becomes the foundation stone of the core of information science technology and the national economic development, national defense construction, and world politics, economy and culture have been produced tremendous influence.As with fastest developing speed on the human history, have the greatest impact, most widely used technology, integrated circuit has become the important symbol of weighing national science technical merit, overall national strength and a defense force.
Microelectric technique, especially Si integrated circuit technique develop so far, and whole world number is thrown the people with trillion dollars equipment and technology, have made Si base technology form very powerful industry ability.Simultaneously, long-term scientific research drops into and also makes the understanding of people to Si and technology thereof, reaches very deep, thorough stage, therefore in IC industry, the Si technology is a mainstream technology, and the Si integrated circuit (IC) products is a main product, accounts for more than 90% of IC industry.Although microelectronics has obtained very big progress in research aspect compound semiconductor and other new material and the application in some field, but from now on 10～20 years, the Si base CMOS integrated circuit technology that microelectric technique will constantly be dwindled with size is as mainstream technology, and is widely used in and the every field of the closely bound up national economy of producing, live.
Last century middle nineteen sixties, the height of U.S. fairchild company is stepped on. the mole doctor delivered after well-known " Moore's Law ", this theorem is pointed out: the transistor size on the integrated circuit (IC) chip, per approximately 18 months increase the by 1 times, performance also promotes 1 times.Simultaneously, the unit functional cost of integrated circuit reduces about 25% every year on average.Over more than 40 year, the world semiconductor industry constantly advances according to this law all the time.Represent in the global information summit that February in 2004, the CEO Ke Laigebeiruite of Intel on the 23rd held in Tokyo that Moore's Law will be still effective at following 15 to 20 years.The technology dynamics that the promotion Moore's Law moves on is: constantly dwindle the chip feature size.At present, external 90nm technology has entered the large-scale production stage, and 60nm technical office is in the introduction period, the 45nm technology is being done the R﹠D work in early stage, according to ITRS ITRS, the 45nm technology can enter large-scale production in 2010, and 2018 is 18nm.
Make the CMOS integrated circuit of so little characteristic size, the process equipment that just needs a new generation, because still there is not to solve preferably at present the technology of on existing equipment, making chip of future generation, therefore can only improve technology level by the renewal of process equipment.Through accumulation for many years, equipment and the technology input of the whole world in microelectronic industry surpasses trillion dollars at present, and the lifting iff obtain technology by the update of equipment will cause per 18 months superseded generation equipment.This will cause the huge resource and the waste of the energy, and therefore, this present situation has seriously restricted the development of semicon industry.
At present, poly-Si has become the grid material of main flow in the Si CMOS integrated circuit, still is p type poly-Si but no matter take n type poly-Si, and its adjusting range to device threshold voltage is all little.In order to adjust the threshold voltage of device more broadly, domestic and international most of manufacturer has taked after well region forms, and injects by once more well region being carried out ion, changes the method for well region doping content, the threshold voltage of trim.But this method still is limited to the device threshold voltage adjusting range, and has increased the difficulty that technology is made, and makes it to have become a technology bottleneck problem.
Summary of the invention
The object of the present invention is to provide a kind ofly to prepare the polycrystal SiGe gate nano-scale CMOS integrated circuit method, prepare the CMOS integrated circuit that conducting channel is 65～90nm with micro process with polycrystal SiGe gate to be implemented under the condition that does not change existing equipment and increase cost based on multilayered auxiliary structure.
For achieving the above object, preparation provided by the invention has the method for the nano-scale CMOS integrated circuit of polycrystal SiGe gate, carries out as follows:
The first step. thermal oxidation one deck SiO on the Si substrate 2Resilient coating, deposit layer of sin on this resilient coating is used for sheltering of well region injection;
Second step. difference photoetching N trap and P trap on the SiN layer, carry out the injection and the propelling of N trap and P trap simultaneously, form P trap and N trap respectively at the Si substrate;
The 3rd the step. etch away N trap and P trap top and between SiN layer and SiO 2Layer, and then at entire substrate superficial growth one deck SiO 2Resilient coating and SiN layer, photoetching on the SiN layer, oxidation form isolated area;
The 4th step. the thick SiO of thermal oxide growth 7～11nm on N trap and P trap 2Gate dielectric layer, n type doped P loy-SiGe that deposit one deck 120～150nm is thick on N trap and P trap respectively and p type doped P loy-SiGe again, as grid, the Ge component is 0.05～0.3, doping content＞10 20Cm -3
The 5th step. the deposit layer thickness of growing is the SiO of 40～60nm on Ploy-SiGe 2, as the protective layer of grid;
The 6th step. at SiO 2The thick Ploy-Si of deposit one deck 110～160nm again on the layer, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
The 7th step. in the zone of Ploy-Si, etch the window that coincident circuit requires;
The 8th step. the thick SiN dielectric layer of deposit one deck 90～130nm on whole Si substrate covers whole surface;
The 9th step. the lip-deep SiN of etched substrate, the SiN of reservation Ploy-Si sidewall; The etch rate that utilizes Ploy-Si and SiN is than (11: 1), the Ploy-Si on etching SiN surface; Utilize SiO 2With the etch rate of SiN than (4: 1), etch away the surface and go up SiO except that the SiN sidewall areas 2The etch rate that utilizes Ploy-SiGe and SiN again is than (11: 1), etch away the surface and go up Ploy-SiGe except that the SiN sidewall areas, the grid of formation n/pMOSFET, and on well region the thick SiO of deposit one deck 4～8nm 2, the protective layer of formation gate lateral wall;
The tenth step. carry out n type ion at the P well region respectively and inject, autoregistration generates source region and the drain region of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region and the drain region of pMOSFET;
The 11 step. photoetching lead-in wire on grid, source and the drain region of n/pMOSFET, constituting conducting channel is the CMOS integrated circuit of 65～90nm.
Describedly etching the window that coincident circuit requires in the zone of Ploy-Si, is to determine that according to the minimum line size of micro process processing and the size of alignment precision width is got 2～3.5 μ m usually.
Described grid length is determined according to the SiN thickness of the 8th step deposit, is got 65～90nm usually.
The present invention has following advantage:
1. the present invention is owing to utilized Ploy-Si and SiN, SiO in the plasma etching industrial 2With SiN, Ploy-SiGe etch rate ratio and self-registered technology, can on micron order Si integrated circuit technology platform, produce the CMOS integrated circuit of conducting channel 65～90nm with polycrystal SiGe gate with SiN;
2. because process proposed by the invention is process ripe in the existing micron order Si integrated circuit technology platform, therefore, the nano-scale CMOS integrated circuit implementation method with polycrystal SiGe gate proposed by the invention is compatible mutually with existing micron order Si integrated circuit technology;
3. because process proposed by the invention adopts the poly-SiGe material as gate medium, its work function changes with the variation of Ge component, by Ge component in the poly-SiGe grid of regulating CMOS, make the nMOSFET threshold voltage to adjust continuously, therefore, realize the adjustment of cmos device threshold voltage, reduced processing step, reduced technology difficulty;
4. all can in existing micron order Si integrated circuit technology platform, realize owing to process proposed by the invention, therefore can be under the situation that need not append any fund and equipment input, the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, and make the performance of the CMOS integrated circuit of its preparation improve for 3～5 generations;
5. because process proposed by the invention can realize the CMOS integrated circuit of conducting channel 65～90nm, therefore, along with reducing of conducting channel size, the integrated level of integrated circuit can significantly improve, thereby has reduced the manufacturing cost of lsi unit area;
6. because little with the conducting channel of device in the CMOS integrated circuit of process preparation of the present invention, therefore, the operating frequency of integrated circuit significantly improves, and has realized the great-leap-forward development of domestic integrated circuit level of processing.
Description of drawings
Fig. 1 is a process chart of the present invention;
Fig. 2 is the process schematic diagram that has the CMOS integrated circuit of polycrystal SiGe gate with the inventive method preparation.
Embodiment
Following with reference to accompanying drawing 1 and accompanying drawing 2, the technological process that the present invention's preparation is had the nano-scale CMOS integrated circuit of polycrystal SiGe gate describes in further detail.
Embodiment 1: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 75nm on the Si substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type Si substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 25nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 120nm of plasma-reinforced chemical vapour deposition PECVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2Layer carries out the N trap simultaneously and advances, and forms N trap 5 on substrate 1;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 3.5 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 30nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 110nm with the method deposit of PECVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 0.8 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 9nm 2Gate dielectric layer 7;
(4b) at SiO 2The method of using high vacuum chemical vapour deposition UHVCVD on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 135nm, as grid, the Ge component is 0.2, doping content＞10 20Cm -3
(4c) the thick SiO of method deposit growth 50nm of application PECVD on Ploy-SiGe 2Layer 9 is as the protective layer of grid;
(4d) at SiO 2Use the thick Ploy-Si layer 10 of method deposit 140nm of PECVD on the layer again, this one deck assists to generate sidewall mainly as the auxiliary layer in the manufacture process;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 3 μ m usually.
Step 5, deposit SiN medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiN dielectric layer 11 of method deposit one deck 110nm of PECVD, cover whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) method of utilizing dry etching etches away the SiN of substrate surface, keeps the SiN of Ploy-Si sidewall;
(6b) utilize the etch rate of Ploy-Si and SiN than (11: 1), with SiO 2The Ploy-Si on surface all etches away;
(6c) utilize SiO 2With the etch rate of SiN than (4: 1), etch away the SiO except that the SiN sidewall areas on the substrate surface 2Expose bottom Ploy-SiGe;
(6d) utilize the etch rate of Ploy-SiGe and SiN than (11: 1), and protect with the SiN sidewall, etch away SiN sidewall protection zone Ploy-SiGe in addition again, Ploy-SiGe below the reservation sidewall, form the grid s of nMOSFET and the grid sa of pMOSFET, the length of this grid is determined according to the SiN thickness of step 5 deposit, is got 75nm usually;
(6e) utilize wet etching to fall the SiN sidewall;
(6f) method thick SiO of deposit one deck 6nm on well region of usefulness PECVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 75nm.
Embodiment 2: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 65nm on the SOI substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type SOI substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 15nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 100nm of normal pressure chemical vapor deposition APCVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2, carry out the N trap simultaneously and advance, on substrate 1, form N trap 5;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 2.5 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 20nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 100nm with the method deposit of APCVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 0.5 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 7nm 2Gate dielectric layer 7;
(4b) at SiO 2The method of using UHVCVD on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 120nm, as grid, the Ge component is 0.3, doping content＞10 20Cm -3
(4c) the thick SiO of method deposit growth 40nm of application APCVD on Ploy-SiGe 2Layer 9 is as the protective layer of grid;
(4d) at SiO 2Use the thick Ploy-Si layer 10 of method deposit 110nm of APCVD on the layer again, this one deck assists to generate sidewall mainly as the auxiliary layer in the manufacture process;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 2 μ m usually.
Step 5, deposit SiN medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiN dielectric layer 11 of method deposit one deck 90nm of APCVD, cover whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) method of utilizing dry etching etches away the SiN of substrate surface, keeps the SiN of Ploy-Si sidewall;
(6b) utilize the etch rate of Ploy-Si and SiN than (11: 1), with SiO 2The Ploy-Si on surface all etches away;
(6c) utilize SiO 2With the etch rate of SiN than (4: 1), etch away the SiO except that the SiN sidewall areas on the substrate surface 2Expose bottom Ploy-SiGe;
(6d) utilize the etch rate of Ploy-SiGe and SiN than (11: 1), and protect with the SiN sidewall, etch away SiN sidewall protection zone Ploy-SiGe in addition again, Ploy-SiGe below the reservation sidewall, form the grid s of nMOSFET and the grid sa of pMOSFET, the length of this grid is determined according to the SiN thickness of step 5 deposit, is got 65nm usually;
(6e) utilize wet etching to fall the SiN sidewall;
(6f) method thick SiO of deposit one deck 4nm on well region of usefulness APCVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 65nm.
Embodiment 3: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 90nm on the Si substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type Si substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 35nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 130nm of low-pressure chemical vapor phase deposition LPCVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2, carry out the N trap simultaneously and advance, on substrate 1, form N trap 5;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 5 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 40nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 120nm with the method deposit of LPCVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 1 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 11nm 2 Gate dielectric layer 7;
(4b) at SiO 2The method of using UHVCVD on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 150nm, as grid, the Ge component is 0.05, doping content＞10 20Cm -3
(4c) the thick SiO of method deposit growth 60nm of application LPCVD on Ploy-SiGe 2Layer 9 is as the protective layer of grid;
(4d) at SiO 2Use the thick Ploy-Si layer 10 of method deposit 160nm of LPCVD on the layer again, this one deck assists to generate sidewall mainly as the auxiliary layer in the manufacture process;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 3.5 μ m usually.
Step 5, deposit SiN medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiN dielectric layer 11 of method deposit one deck 130nm of LPCVD, cover whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) method of utilizing dry etching etches away the SiN of substrate surface, keeps the SiN of Ploy-Si sidewall;
(6b) utilize the etch rate of Ploy-Si and SiN than (11: 1), with SiO 2The Ploy-Si on surface all etches away;
(6c) utilize SiO 2With the etch rate of SiN than (4: 1), etch away the SiO except that the SiN sidewall areas on the substrate surface 2Expose bottom Ploy-SiGe;
(6d) utilize the etch rate of Ploy-SiGe and SiN than (11: 1), and protect with the SiN sidewall, etch away SiN sidewall protection zone Ploy-SiGe in addition again, Ploy-SiGe below the reservation sidewall, form the grid s of nMOSFET and the grid sa of pMOSFET, the length of this grid is determined according to the SiN thickness of step 5 deposit, is got 90nm usually;
(6e) utilize wet etching to fall the SiN sidewall;
(6f) method thick SiO of deposit one deck 8nm on well region of usefulness LPCVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 90nm.
Above embodiment does not constitute any limitation of the invention.

Claims (4)

1. one kind prepares the polycrystal SiGe gate nano-scale CMOS integrated circuit method based on multilayered auxiliary structure, carries out as follows:
Step 1. go up thermal oxidation one deck SiO at Si substrate (1) 2Resilient coating (2), deposit layer of sin (3) on this resilient coating is used for sheltering of well region injection;
Step 2. difference photoetching N trap and P trap on the SiN layer, carry out N trap and P trap simultaneously and advance, form P trap (4) and N trap (5) respectively at Si substrate (1);
Step 3. etch away P trap (4) and N trap (5) top and between SiN layer and SiO 2Layer, and then at entire substrate superficial growth one deck SiO 2Resilient coating and SiN layer, photoetching field isolated area on the SiN layer, oxidation forms isolated area (6);
Step 4. thermal oxide growth thickness is the SiO of 7～11nm on N trap and P trap 2Gate dielectric layer (7), more respectively on N trap and P trap deposit one layer thickness be n type doped P loy-SiGe layer (8a) and the p type doped P loy-SiGe layer (8) of 120～150nm, as grid, the Ge component is 0.05～0.3, doping content＞10 20Cm -3
Step 5. the deposit layer thickness of growing is the SiO of 40～60nm on Ploy-SiGe 2(9), as the protective layer of grid;
Step 6. at SiO 2The Ploy-Si (10) that deposit one deck 110～160nm is thick again on the layer, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
Step 7. in the zone of Ploy-Si, etch the window (10a) that coincident circuit requires;
Step 8. the SiN dielectric layer (11) that deposit one deck 90～130nm is thick on the Si substrate covers whole surface;
Step 9. the lip-deep SiN of etched substrate, the SiN of reservation Ploy-Si sidewall; The etch rate that utilizes Ploy-Si and SiN is than (11: 1), the Ploy-Si on etching SiN surface; Utilize SiO 2With the etch rate of SiN than (4: 1), etch away the surface and go up SiO except that the SiN sidewall areas 2The etch rate that utilizes Ploy-SiGe and SiN again is than (11: 1), etch away the surface and go up Ploy-SiGe except that the SiN sidewall areas, the grid (s) of formation nMOSFET and the grid (sa) of pMOSFET, and on well region the thick SiO of deposit one deck 4～8nm 2, the protective layer (12) of formation gate lateral wall;
Step 10. carry out n type ion at the P well region and inject, autoregistration generates source region (13) and drain region (14) of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region (15) and drain region (16) of pMOSFET;
Step 11. photoetching lead-in wire on grid, source and the drain region of n/pMOSFET, constituting conducting channel is the CMOS integrated circuit of 65～90nm.
2. method according to claim 1, wherein, step 7 is described to etch the window that coincident circuit requires in the zone of Ploy-Si, be to determine that according to the minimum line size of micro process processing and the size of alignment precision width is got 2～3.5 μ m usually.
3. method according to claim 1, wherein, the described formation grid of step 9, its length is determined according to the SiN thickness of step 8 deposit, is got 65～90nm usually.
4. one kind prepares the polycrystal SiGe gate nano-scale CMOS integrated circuit method based on multilayered auxiliary structure, comprises the steps:
The 1st step. go up thermal oxidation one deck SiO at Si substrate (1) 2Resilient coating (2) with the method deposit layer of sin (3) of PECVD, is used for sheltering of well region injection on this resilient coating;
The 2nd step. difference photoetching N trap and P trap on the SiN layer, carry out N trap and P trap simultaneously and advance, form P trap (4) and N trap (5) respectively at Si substrate (1);
The 3rd the step. etch away P trap (4) and N trap (5) top and between SiN layer and SiO 2Layer, and then at entire substrate superficial growth one deck SiO 2Resilient coating and SiN layer, photoetching field isolated area on the SiN layer, oxidation forms isolated area (6);
The 4th step. the thick SiO of thermal oxide growth 9nm on N trap and P trap 2Gate dielectric layer (7), again with the method for UHVCVD respectively on N trap and P trap growth one layer thickness be n type doped P loy-SiGe layer (8a) and the p type doped P loy-SiGe layer (8) of 135nm, as grid, the Ge component is 0.2, doping content＞10 20Cm -3
The 5th step. the method deposit of using PECVD on the Ploy-SiGe layer thickness of growing is the SiO of 50nm 2(9), as the protective layer of grid;
The 6th step. at SiO 2Use the thick Ploy-Si (10) of method deposit one deck 140nm of PECVD on the layer again, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
The 7th step. in the zone of Ploy-Si, etch the window (10a) that coincident circuit requires;
The 8th step. on whole Si substrate, use the thick SiN dielectric layer (11) of method deposit one deck 110nm of PECVD, cover whole surface;
The 9th step. the lip-deep SiN of etched substrate, the SiN of reservation Ploy-Si sidewall; The etch rate that utilizes Ploy-Si and SiN is than (11: 1), the Ploy-Si on etching SiN surface; Utilize SiO 2With the etch rate of SiN than (4: 1), etch away the surface and go up SiO except that the SiN sidewall areas 2The etch rate that utilizes Ploy-SiGe and SiN again is than (11: 1), etch away the upward Ploy-SiGe except that the SiN sidewall areas of surface, form the grid (s) of nMOSFET and the grid (sa) of pMOSFET, use method thick SiO of deposit one deck 6nm on well region of PECVD at last 2, the protective layer (12) of formation gate lateral wall;
The 10th step. carry out n type ion at the P well region and inject, autoregistration generates source region (13) and drain region (14) of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region (15) and drain region (16) of pMOSFET;
The 11st step. photoetching lead-in wire on grid, source and the drain region of n/pMOSFET, constituting conducting channel is the CMOS integrated circuit of 75nm.
CN200810150929A 2008-09-12 2008-09-12 Prepare the polycrystal SiGe gate nano-scale CMOS integrated circuit method based on multilayered auxiliary structure Expired - Fee Related CN100585835C (en)

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CN102723330A (en) * 2012-07-16 2012-10-10 西安电子科技大学 Strain Si BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor) integrated device and preparation method thereof
CN105489497A (en) * 2015-11-24 2016-04-13 中国电子科技集团公司第二十研究所 Method for fabricating PMOS control circuit of polycrystalline SiGe gate by utilizing auxiliary structure

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US4430791A (en) * 1981-12-30 1984-02-14 International Business Machines Corporation Sub-micrometer channel length field effect transistor process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102723330A (en) * 2012-07-16 2012-10-10 西安电子科技大学 Strain Si BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor) integrated device and preparation method thereof
CN102723330B (en) * 2012-07-16 2015-12-09 西安电子科技大学 A kind of strain Si BiCMOS integrated device and preparation method
CN105489497A (en) * 2015-11-24 2016-04-13 中国电子科技集团公司第二十研究所 Method for fabricating PMOS control circuit of polycrystalline SiGe gate by utilizing auxiliary structure

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