CN101359629B - Polycrystal SiGe gate nano CMOS integrated circuit preparation based on SiO2 masking technique - Google Patents

Polycrystal SiGe gate nano CMOS integrated circuit preparation based on SiO2 masking technique Download PDF

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CN101359629B
CN101359629B CN2008101509333A CN200810150933A CN101359629B CN 101359629 B CN101359629 B CN 101359629B CN 2008101509333 A CN2008101509333 A CN 2008101509333A CN 200810150933 A CN200810150933 A CN 200810150933A CN 101359629 B CN101359629 B CN 101359629B
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layer
trap
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sige
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CN101359629A (en
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胡辉勇
张鹤鸣
宣荣喜
戴显英
舒斌
宋建军
赵丽霞
屈江涛
徐小波
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Xidian University
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Abstract

The invention discloses a method based on SiO2 masking technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N/P well and growing a Poly- SiGe/SiO2/Poly-Si multi-layer structure on the N/P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching the SiO2 layer on the surface, except the SiO2 at the side face of the window; based on the etching ratio of Poly-Si to SiO2 (50:1), etching the Poly-Si at the upper layer; based on the etching ratio of Poly-SiGeto SiO2 (50:1), etching the SiO2 and the Poly-SiGe, except the SiO2 and Poly-SiGe in the protective area at the side wall of the SiO2, preserving the SiO2 and Poly-SiGe below the side wall, forming an/p MOSFET grid and depositing a layer of SiO2; injecting ions, self-aligning, and forming the source area and the drain area of the n/p MOSFET grid so as to form an n/p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 65-90nm. The method can fabricate a CMOS integrated circuit which is improved in performanceby 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

Based on SiO 2The polycrystal SiGe gate nano CMOS integrated circuit preparation of macking technique
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of existing micron order Si integrated circuit fabrication process that utilizes, make the method for nanoscale Si integrated circuit.
Background technology
Electronic information technology is the core technology of national economy, and it serves the national economy every field, and microelectric technique is the key of electronic information technology, and integrated circuit is the key in the key especially.Integrated circuit is since 1958 come out, and development speed is surprising, becomes the foundation stone of the core of information science technology and the national economic development, national defense construction, and world politics, economy and culture have been produced tremendous influence.As with fastest developing speed on the human history, have the greatest impact, most widely used technology, integrated circuit has become the important symbol of weighing national science technical merit, overall national strength and a defense force.
The Si integrated circuit technique develops so far, and whole world number is thrown the people with trillion dollars equipment and technology, has made Si base technology form very powerful industry ability.Simultaneously, long-term scientific research drops into and also makes the understanding of people to Si and technology thereof, reaches very deep, thorough stage, therefore in IC industry, the Si technology is a mainstream technology, and the Si integrated circuit (IC) products is a main product, accounts for more than 90% of IC industry.Although microelectronics has obtained very big progress in research aspect compound semiconductor and other new material and the application in some field, but from now on 10～20 years, the Si base CMOS integrated circuit technology that microelectric technique will constantly be dwindled with size is as mainstream technology, and is widely used in and the every field of the closely bound up national economy of producing, live.
In generation nineteen sixty, the height of U.S. fairchild company is stepped on. well-known " Moore's Law " after the mole doctor has delivered, and this theorem is pointed out: the transistor size on the integrated circuit (IC) chip, increased by 1 times in per approximately 18 months, performance also promotes 1 times.Simultaneously, the unit functional cost of integrated circuit reduces about 25% every year on average.Over more than 40 year, the world semiconductor industry constantly advances according to this law all the time.Represent in the global information summit that February in 2004, the CEO Ke Laigebeiruite of Intel on the 23rd held in Tokyo that Moore's Law will be still effective at following 15 to 20 years.The technology dynamics that the promotion Moore's Law moves on is: constantly dwindle the chip feature size.At present, external 90nm technology has entered the large-scale production stage, and 60nm technical office is in the introduction period, the 45nm technology is being done the R﹠D work in early stage, according to ITRS ITRS, the 45nm technology can enter large-scale production in 2010, and 2018 is 18nm.
Make the CMOS integrated circuit of so little characteristic size, the process equipment that just needs a new generation, because still there is not to solve preferably at present the technology of on existing equipment, making chip of future generation, therefore can only improve technology level by the renewal of process equipment.Through accumulation for many years, equipment and the technology input of the whole world in microelectronic industry surpasses trillion dollars at present, and the lifting iff obtain technology by the update of equipment will cause per 18 months superseded generation equipment.This will cause the huge resource and the waste of the energy, and therefore, this present situation has seriously restricted the development of semicon industry.
Nowadays, poly-Si has become the grid material of main flow in the MOS device, still is p type poly-Si but no matter take n type poly-Si, and its adjusting range to device threshold voltage is all little.In order to adjust the threshold voltage of device more broadly, domestic and international most of manufacturer has taked after well region forms, and injects by once more well region being carried out ion, changes the method for well region doping content, the threshold voltage of trim.But this method still is limited to the device threshold voltage adjusting range, and has increased the difficulty that technology is made, and makes it to have become a technology bottleneck problem.
Summary of the invention
The object of the present invention is to provide a kind of based on SiO 2The polycrystal SiGe gate nano CMOS integrated circuit preparation of macking technique to be implemented under the condition that does not change existing equipment and increase cost, is prepared the CMOS integrated circuit that conducting channel is 65～90nm with micro process.
For achieving the above object, preparation provided by the invention has the method for the nano-scale CMOS integrated circuit of polycrystal SiGe gate, carries out as follows:
The first step. thermal oxidation one deck SiO on the Si substrate 2Resilient coating, deposit layer of sin on this resilient coating is used for sheltering of well region injection;
Second step. difference photoetching N trap and P trap on the SiN layer, carry out the injection and the propelling of N trap and P trap simultaneously, form P trap and N trap respectively at the Si substrate;
The 3rd the step. etch away N trap and P trap top and between SiN layer and SiO 2Layer, and then at entire substrate superficial growth one deck SiO 2Resilient coating and SiN layer, photoetching on the SiN layer, oxidation form isolated area;
The 4th step. the thick SiO of thermal oxide growth 8～12nm on N trap and P trap 2Gate dielectric layer, n type doped P loy-SiGe that deposit one deck 120～150nm is thick on N trap and P trap respectively and p type doped P loy-SiGe again, as grid, the Ge component is 0.05～0.3, doping content＞10 20Cm -3
The 5th step. the deposit layer thickness of growing is the SiO of 60～80nm on Ploy-SiGe 2, as the protective layer of grid;
The 6th step. at SiO 2The thick Ploy-Si of deposit one deck 100～160nm again on the layer, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
The 7th step. in the zone of Ploy-Si, etch the window that coincident circuit requires;
The 8th step. the thick SiO of deposit one deck 90～140nm on whole Si substrate 2Dielectric layer covers whole surface;
The 9th step. the lip-deep SiO of etched substrate 2, the SiO of reservation Ploy-Si sidewall 2Utilize Ploy-Si and SiO 2Etch rate than (50: 1), etch away SiO 2The Ploy-Si on surface removes SiO on the etched substrate surface 2SiO beyond the sidewall areas 2Expose bottom Ploy-SiGe; Utilize Ploy-SiGe and SiO 2Etch rate than (50: 1), etching SiO 2Ploy-SiGe beyond the sidewall protection zone forms the grid of n/pMOSFET, and on well region the thick SiO of deposit one deck 3～5nm 2, the protective layer of formation gate lateral wall;
The tenth step. carry out n type ion at the P well region respectively and inject, autoregistration generates source region and the drain region of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region and the drain region of pMOSFET;
The 11 step. photoetching lead-in wire on grid, source and the drain region of n/pMOSFET, constituting conducting channel is the CMOS integrated circuit of 65～90nm.
Describedly etching the window that coincident circuit requires in the zone of Ploy-Si, is to determine that according to the minimum line size of micro process processing and the size of alignment precision width is got 2～3 μ m usually.
Described grid length is according to the SiO of the 8th step deposit 2Thickness is determined, is got 65～90nm usually.
The present invention has following advantage:
1. the present invention is owing to utilized Ploy-Si and SiO in the plasma etching industrial 2, Ploy-SiGe and SiO 2Etch rate than and self-registered technology, can on micron order Si integrated circuit technology platform, produce the CMOS integrated circuit of conducting channel 65～90nm with polycrystal SiGe gate;
2. because process proposed by the invention is process ripe in the existing micron order Si integrated circuit technology platform, therefore, the nano-scale CMOS integrated circuit implementation method with polycrystal SiGe gate proposed by the invention is compatible mutually with existing micron order Si integrated circuit technology;
3. because process proposed by the invention adopts the poly-SiGe material as gate medium, its work function changes with the variation of Ge component, by Ge component in the poly-SiGe grid of regulating CMOS, make the nMOSFET threshold voltage to adjust continuously, therefore, realize the adjustment of cmos device threshold voltage, reduced processing step, reduced technology difficulty;
4. all can in existing micron order Si integrated circuit technology platform, realize owing to process proposed by the invention, therefore can be under the situation that need not append any fund and equipment input, the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, and make the performance of the CMOS integrated circuit of its preparation improve for 3～5 generations;
5. because process proposed by the invention can realize the CMOS integrated circuit of conducting channel 65～90nm, therefore, along with reducing of conducting channel size, the integrated level of integrated circuit can significantly improve, thereby has reduced the manufacturing cost of lsi unit area;
6. because little with the conducting channel of device in the CMOS integrated circuit of process preparation of the present invention, therefore, the operating frequency of integrated circuit significantly improves, and has realized the great-leap-forward development of domestic integrated circuit level of processing.
Description of drawings
Fig. 1 is a process chart of the present invention;
Fig. 2 is the process schematic diagram that has the CMOS integrated circuit of polycrystal SiGe gate with the inventive method preparation.
Embodiment
Following with reference to accompanying drawing 1 and accompanying drawing 2, the technological process that the present invention's preparation is had the nano-scale CMOS integrated circuit of polycrystal SiGe gate describes in further detail.
Embodiment 1: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 75nm on the Si substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type Si substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 40nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 140nm of plasma-reinforced chemical vapour deposition PECVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2Layer carries out the N trap simultaneously and advances, and forms N trap 5 on substrate 1;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 4 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 50nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 140nm with the method deposit of PECVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 0.8 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 10nm 2 Gate dielectric layer 7;
(4b) at SiO 2The method of using ultraviolet light chemistry vapor deposition UVCVD on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 140nm, as grid, the Ge component is 0.15, doping content＞10 20Cm -3
(4c) the thick SiO of method deposit growth 70nm of application PECVD on Ploy-SiGe 2Layer 9 is as the protective layer of grid;
(4d) at SiO 2Use the thick Ploy-Si layer 10 of method deposit 130nm of PECVD on the layer again, this one deck assists to generate sidewall mainly as the auxiliary layer in the manufacture process;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 2.5 μ m usually.
Step 5, deposit SiO 2Medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiO of method deposit one deck 110nm of PECVD 2Dielectric layer 11 covers whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) utilize the SiO of the method for dry etching with substrate surface 2Etch away, keep the SiO of Ploy-Si sidewall 2
(6b) utilize Ploy-Si and SiO 2Etch rate than (50: 1), with SiO 2The Ploy-Si on surface all etches away;
(6c) etch away on the substrate surface except that SiO 2SiO beyond the sidewall areas 2Expose bottom Ploy-SiGe;
(6d) utilize Ploy-SiGe and SiO 2Etch rate than (50: 1), and with SiO 2Sidewall is protected, and etches away SiO again 2Ploy-SiGe below the Ploy-SiGe beyond the sidewall protection zone, reservation sidewall forms the grid s of nMOSFET and the grid sa of pMOSFET, and the length of this grid is according to the SiO of step 5 deposit 2Thickness is determined, is got 75nm usually;
(6e) method thick SiO of deposit one deck 4nm on well region of usefulness PECVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 75nm.
Embodiment 2: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 65nm on the SOI substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type SOI substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 30nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 120nm of normal pressure chemical vapor deposition APCVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2, carry out the N trap simultaneously and advance, on substrate 1, form N trap 5;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 3 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 50nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 120nm with the method deposit of APCVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 0.5 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 8nm 2Gate dielectric layer 7;
(4b) at SiO 2The method of using UVCVD on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 120nm, as grid, the Ge component is 0.05, doping content＞10 20Cm -3
(4c) the thick SiO of method deposit growth 60nm of application APCVD on Ploy-SiGe 2Layer 9 is as the protective layer of grid;
(4d) at SiO 2Use the thick Ploy-Si layer 10 of method deposit 100nm of APCVD on the layer again, this one deck assists to generate sidewall mainly as the auxiliary layer in the manufacture process;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 2 μ m usually.
Step 5, deposit SiO 2Medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiO of method deposit one deck 90nm of APCVD 2Dielectric layer 11 covers whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) utilize the SiO of the method for dry etching with substrate surface 2Etch away, keep the SiO of Ploy-Si sidewall 2
(6b) with Ploy-Si and SiO 2Etch rate than (50: 1), with SiO 2The Ploy-Si on surface all etches away;
(6c) etch away on the substrate surface except that SiO 2SiO beyond the sidewall areas 2Expose bottom Ploy-SiGe;
(6d) utilize Ploy-SiGe and SiO 2Etch rate than (50: 1), and with SiO 2Sidewall is protected, and etches away SiO again 2Ploy-SiGe below the Ploy-SiGe beyond the sidewall protection zone, reservation sidewall forms the grid s of nMOSFET and the grid sa of pMOSFET, and the length of this grid is according to the SiO of step 5 deposit 2Thickness is determined, is got 65nm usually;
(6e) method thick SiO of deposit one deck 3nm on well region of usefulness APCVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 65nm.
Embodiment 3: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 90nm on the Si substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type Si substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 50nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 160nm of low-pressure chemical vapor phase deposition LPCVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2, carry out the N trap simultaneously and advance, on substrate 1, form N trap 5;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 5 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 60nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 160nm with the method deposit of LPCVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 1 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 12nm 2 Gate dielectric layer 7;
(4b) at SiO 2The method of using UVCVD on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 150nm, as grid, the Ge component is 0.3, doping content＞10 20Cm -3
(4c) the thick SiO of method deposit growth 80nm of application LPCVD on Ploy-SiGe 2Layer 9 is as the protective layer of grid;
(4d) at SiO 2Use the thick Ploy-Si layer 10 of method deposit 160nm of LPCVD on the layer again, this one deck assists to generate sidewall mainly as the auxiliary layer in the manufacture process;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 3 μ m usually.
Step 5, deposit SiO 2Medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiO of method deposit one deck 140nm of LPCVD 2Dielectric layer 11 covers whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) utilize the SiO of the method for dry etching with substrate surface 2Etch away, keep the SiO of Ploy-Si sidewall 2
(6b) utilize Ploy-Si and SiO 2Etch rate than (50: 1), with SiO 2The Ploy-Si on surface all etches away;
(6c) etch away on the substrate surface except that SiO 2SiO beyond the sidewall areas 2Expose bottom Ploy-SiGe;
(6d) utilize Ploy-SiGe and SiO 2Etch rate than (50: 1), and with the SiO of sidewall 2Protect, etch away SiO again 2Ploy-SiGe below the Ploy-SiGe beyond the sidewall protection zone, reservation sidewall forms the grid s of nMOSFET and the grid sa of pMOSFET, and the length of this grid is according to the SiO of step 5 deposit 2Thickness is determined, is got 90nm usually;
(6e) method thick SiO of deposit one deck 5nm on well region of usefulness LPCVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 90nm.
Above embodiment does not constitute any limitation of the invention.

Claims (4)

1. one kind based on SiO 2The polycrystal SiGe gate nano CMOS integrated circuit preparation of macking technique, carry out as follows:
Step 1. go up thermal oxidation one deck SiO at Si substrate (1) 2Resilient coating (2), deposit layer of sin (3) on this resilient coating is used for sheltering of well region injection;
Step 2. difference photoetching N trap and P trap on the SiN layer, carry out N trap and P trap simultaneously and advance, form P trap (4) and N trap (5) respectively at Si substrate (1);
Step 3. etch away P trap (4) and N trap (5) top and between SiN layer and SiO 2Layer, and then at entire substrate superficial growth one deck SiO 2Resilient coating and SiN layer, photoetching field isolated area on the SiN layer, oxidation forms isolated area (6);
Step 4. thermal oxide growth thickness is the SiO of 8～12nm on N trap and P trap 2Gate dielectric layer (7), n type doped P loy-SiGe layer (8a) that deposit one deck 120～150nm is thick on N trap and P trap respectively and p type doped P loy-SiGe layer (8) again, as grid, the Ge component is 0.05～0.3, doping content＞10 20Cm -3
Step 5. the deposit layer thickness of growing is the SiO of 60～80nm on Ploy-SiGe 2(9), as the protective layer of grid;
Step 6. at SiO 2The Ploy-Si (10) that deposit one deck 100～160nm is thick again on the layer, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
Step 7. in the zone of Ploy-Si, etch the window (10a) that coincident circuit requires;
Step 8. the thick SiO of deposit one deck 90～140nm on whole Si substrate 2Dielectric layer (11) covers whole surface;
Step 9. the lip-deep SiO of etched substrate 2, the SiO of reservation Ploy-Si sidewall 2Utilize Ploy-Si and SiO 250: 1 etch rate ratio, etching SiO 2The Ploy-Si on surface removes SiO on the etched substrate surface 2SiO beyond the sidewall areas 2Expose bottom Ploy-SiGe; Utilize Ploy-SiGe and SiO 250: 1 etch rate ratio etches away SiO 2Ploy-SiGe beyond the sidewall protection zone forms the grid (sa) of nMOSFET grid (s) and pMOSFET, and on well region the thick SiO of deposit one deck 3～5nm 2, the protective layer (12) of formation gate lateral wall;
Step 10. carry out n type ion at the P well region and inject, autoregistration generates source region (13) and drain region (14) of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region (15) and drain region (16) of pMOSFET;
Step 11. photoetching lead-in wire on grid, source and the drain region of n/pMOSFET, constituting conducting channel is the CMOS integrated circuit of 65～90nm.
2. method according to claim 1, wherein, step 7 is described to etch the window that coincident circuit requires in the zone of Ploy-Si, is to determine that according to the minimum line size of micro process processing and the size of alignment precision width is got 2～3 μ m.
3. method according to claim 1, wherein, the described formation grid of step 9, its length is according to the SiO of step 8 deposit 2Thickness is determined, is got 65～90nm.
4. one kind based on SiO 2The polycrystal SiGe gate nano CMOS integrated circuit preparation of macking technique comprises the steps:
Step 1. goes up thermal oxidation one deck SiO at Si substrate (1) 2Resilient coating (2) with the method deposit layer of sin (3) of PECVD, is used for sheltering of well region injection on this resilient coating;
Step 2. is difference photoetching N trap and P trap on the SiN layer, carries out N trap and P trap simultaneously and advances, and forms P trap (4) and N trap (5) respectively at Si substrate (1);
Step 3. etch away P trap (4) and N trap (5) top and between SiN layer and SiO 2Layer, and then at entire substrate superficial growth one deck SiO 2Resilient coating and SiN layer, photoetching field isolated area on the SiN layer, oxidation forms isolated area (6);
Step 4. is the thick SiO of thermal oxide growth 10nm on N trap and P trap 2Gate dielectric layer (7), again with the method for UVCVD respectively on N trap and P trap growth one layer thickness be n type doped P loy-SiGe layer (8a) and the p type doped P loy-SiGe layer (8) of 140nm, as grid, the Ge component is 0.15, doping content＞10 20Cm -3
Step 5. is used PECVD on Ploy-SiGe the method deposit layer thickness of growing is the SiO of 70nm 2(9), as the protective layer of grid;
Step 6. is at SiO 2Use the thick Ploy-Si (10) of method deposit one deck 130nm of PECVD on the layer again, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
Step 7. etches the window (10a) that coincident circuit requires in the zone of Ploy-Si;
Step 8. is used the thick SiO of method deposit one deck 110nm of PECVD on whole Si substrate 2Dielectric layer (11) covers whole surface;
The lip-deep SiO of step 9. etched substrate 2, the SiO of reservation Ploy-Si sidewall 2Utilize Ploy-Si and SiO 250: 1 etch rate ratio, etching SiO 2The Ploy-Si on surface removes SiO on the etched substrate surface 2SiO beyond the sidewall areas 2Expose bottom Ploy-SiGe; Utilize Ploy-SiGe and SiO 250: 1 etch rate ratio etches away SiO 2Ploy-SiGe beyond the sidewall protection zone forms the grid (s) of nMOSFET and the grid (sa) of pMOSFET, uses method thick SiO of deposit one deck 4nm on well region of PECVD at last 2, the protective layer (12) of formation gate lateral wall;
Step 10. is carried out the injection of n type ion at the P well region, and autoregistration generates source region (13) and drain region (14) of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region (15) and drain region (16) of pMOSFET;
Step 11. is the photoetching lead-in wire on grid, source and the drain region of n/pMOSFET, and constituting conducting channel is the CMOS integrated circuit of 75nm.
CN2008101509333A 2008-09-12 2008-09-12 Polycrystal SiGe gate nano CMOS integrated circuit preparation based on SiO2 masking technique Expired - Fee Related CN101359629B (en)

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CN1366711A (en) * 2000-02-17 2002-08-28 皇家菲利浦电子有限公司 Semiconductor device with integrated CMOS circuit with MOS transistors having silicon-germanium (Sil-Gex) gate electrodes, and method for manufacturing same
CN101027779A (en) * 2004-09-17 2007-08-29 应用材料公司 Poly-silicon-germanium gate stack and method for forming the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1366711A (en) * 2000-02-17 2002-08-28 皇家菲利浦电子有限公司 Semiconductor device with integrated CMOS circuit with MOS transistors having silicon-germanium (Sil-Gex) gate electrodes, and method for manufacturing same
CN101027779A (en) * 2004-09-17 2007-08-29 应用材料公司 Poly-silicon-germanium gate stack and method for forming the same

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