CN102810568B - Stress silicon (Si) vertical-channel P-channel metal-oxide semiconductor (PMOS) device and preparation method - Google Patents

Abstract

The invention discloses a stress silicon (Si) vertical-channel P-channel metal-oxide semiconductor (PMOS) integration device prepared by a micrometer level process and a preparation method. The method is characterized in that a PMOS device is formed through an epitaxial material preparation step, an isolator preparation step, a drain connecting region preparation step and a PMOS forming step; and finally a PMOS integration circuit with the length of a conducting channel of 22 to 45nm is formed through a step for forming the PMOS integration circuit. By utilizing the characteristic that the hole mobility of the stress Si is higher than that of relaxation Si, on the platform of a micrometer-level Si integration circuit processing technique, the stress Si vertical-channel PMOS integration device and the circuit with excellent performance are manufactured under low temperature.

Description

A kind of strain Si vertical-channel PMOS integrated device and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of strain Si vertical-channel PMOS integrated device and preparation method.

Background technology

New technology revolution, also known as modern technologies revolution, also has people it to be called the third technical revolution after steam engine, electric power.The information technology being main contents with microelectric technique, electronic computer, laser, optical fiber communication, satellite communication and remote sensing technology becomes the frontier technology of new technology revolution.New technology revolution results from mid-term 1940's, first it rise, progressively to other countries and regional radiation, until have swept the globe in west developed capitalist countries, it gets up along with the shaping and development of contemporary science and technology, extend to the every field of science and technology.

Information technology is the core technology of scientific and technological revolution, and microelectric technique is the basis of information technology.The historical facts of development in science and technology show, the integrated circuit occurred for 1958 is one of invention of 20th century most impact.The microelectronics be born based on this invention has become the basis of existing modern technologies, accelerates more educated, the IT application process that change human society, have also been changed the mode of thinking of the mankind simultaneously.It not only provides the instrument of strong nature remodeling for the mankind, but also has opened up a wide development space.

Point out " Moore's Law " that semiconductor industry development has an immense impact on: the transistor size in integrated circuit (IC) chip, within about every 18 months, increase by 1 times, performance also promotes 1 times.Over more than 40 year, world semiconductor industry constantly advances according to this law all the time.

Along with the reduction of device size, especially progressively enter after nanoscale, the development of microelectric technique more and more approaches the limit of material, technology, device, is faced with huge challenge.After device feature size narrows down to 65 nanometers, from device angles, the impact of the problem such as impact, technological parameter fluctuation on performances such as device leakage current, subthreshold behavior, ON state/off-state currents of the short channel effect in nanoscale devices, high-field effect, quantum effect, parasitic parameter is more and more outstanding, and the contradiction of circuit speed and power consumption also will be more serious.Along with integrated level and operating frequency increase, power dissipation density increases, and causes chip overheating, can cause circuit malfunction.On the other hand, after entering nanoscale, interconnection resistance and interconnection capacitance are not only more obvious on the impact of circuit speed, and can have an impact to signal integrity, become the key factor affecting the final performance of circuit gradually.

The reduction of characteristic size, needs the process equipment of a new generation, because still do not have can solve the technology manufacturing chip of future generation on existing equipment preferably at present, therefore can only improve technology level by the renewal of process equipment.Through accumulation for many years, the equipment of the current whole world in microelectronic industry and Technical investment exceed trillion dollars, if just obtained the lifting of technology by the update of equipment, by every 18 months superseded generation equipment, this will cause huge resource and the waste of the energy, cause production cost to rise, therefore, this present situation seriously constrains the development of semicon industry.

Summary of the invention

The object of the present invention is to provide a kind of preparation method preparing strain Si vertical-channel PMOS device and integrated circuit with existing micro process, to realize, under the condition not changing existing equipment and increase cost, preparing strain Si vertical-channel PMOS device and integrated circuit that conducting channel is 22 ~ 45nm.

The object of the present invention is to provide a kind of strain Si vertical-channel PMOS device, described device conducts raceway groove is hollow, and channel direction is vertical with substrate surface.

Another object of the present invention is to the preparation method providing a kind of strain Si vertical-channel PMOS integrated device, the vertical PMOS device of the strain Si in described integrated device has the conducting channel of hollow; Described preparation method comprises the steps:

The first step, to choose doping content be 10 ¹⁵~ 10 ¹⁶cm ^-3n-type Si substrate slice;

Second step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, growth seven layer materials continuously on substrate: the P type Si epitaxial loayer of ground floor to be thickness be 200 ~ 400nm, doping content is 10 ¹⁵~ 10 ¹⁶cm ^-3; The second layer to be thickness the be P type relaxed sige layer of 1 ~ 1.5 μm, doping content is 5 ~ 10 × 10 ¹⁸cm ^-3, Ge content gradually variational, the Ge component at P type relaxed sige layer and P type Si epitaxial layer interface place is 0%, P type relaxed sige layer top Ge component is 15 ~ 25%; The SiGe layer of Ge component fixed by the P type of third layer to be thickness be 200 ~ 300nm, and Ge component is 15 ~ 25%, consistent with the Ge component at graded sige layer top, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as drain region; The P type strained si layer/of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, as the first lightly-doped source drain region (LDD) layer; Layer 5 to be thickness the be N-type strained si layer/of 22 ~ 45nm is as channel region, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, as the second lightly-doped source drain region (LDD) layer; The SiGe layer of the fixing Ge component of P type doping of layer 7 to be thickness be 300 ~ 400nm, Ge component is 15 ~ 25%, and its doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as source region;

3rd step, photoetching deep trench isolation district, utilize dry etch process, etches in isolated area the deep trouth that the degree of depth is 2 ~ 3 μm;

4th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one SiO ₂layer, all covered by deep trouth inner surface, then depositing polysilicon (Poly-Si) fills up in deep trouth, forms deep trench isolation;

5th step, photoetching shallow trench isolation region, utilize dry etch process, above deep trouth, etch the shallow slot that the degree of depth is 0.4 ~ 0.5 μm with source and drain isolated area; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

6th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away sections SiN and SiO ₂formed and leak bonding pad window; Utilize dry etch process, etch the leakage groove that the degree of depth is 0.45 ~ 0.55 μm; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, grow a SiO at substrate surface ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the SiO of drain region channel bottom ₂layer; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit doping content is in the groove 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3polysilicon, this groove is filled up, removes the polysilicon of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

7th step, etch away SiN and SiO of excess surface ₂barrier layer; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away SiN and SiO ₂form grid window; Utilize dry etch process, etch the gate groove that the degree of depth is 0.45 ~ 0.55 μm; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 5 × 10 in substrate surface deposit doping content ¹⁹~ 5 × 10 ²⁰cm ^-3n-type polycrystalline silicon, and gate groove to be filled up, removes surface portion polysilicon, form grid;

The SiO that 8th step, removal substrate surface are unnecessary ₂, SiN and SiO ₂barrier layer, forms source region, finally forms PMOS device;

9th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, grow a SiO at substrate surface ₂layer, and on grid, source and drain region lithography fair lead;

Tenth step, metallization, photoetching goes between, and forms drain electrode, source electrode and gate metal lead-in wire, forms the PMOS integrated circuit that conducting channel length is 22 ~ 45nm.

Another object of the present invention is to the preparation method providing a kind of strain Si vertical-channel PMOS integrated circuit, the vertical PMOS device of the strain Si in described integrated circuit has the conducting channel of hollow; Described preparation method comprises the steps:

Step 1, epitaxial material preparation process:

(1a) choosing doping content is 5 × 10 ¹⁶cm ^-3the N-type Si substrate slice of left and right;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type Si epitaxial loayer of 300nm in Grown a layer thickness, doping content is 5 × 10 ¹⁶cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si epitaxial loayer grows the P type SiGe resilient coating that a layer thickness is 1.25 μm, Ge content gradually variational, Ge component is distributed as from the bottom to top from 0% to 25%, and doping content is 10 ¹⁹cm ^-3;

(1d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, SiGe epitaxial loayer grows a layer thickness be the P type SiGe layer of 250nm as drain region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 25%;

(1e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, SiGe epitaxial loayer grows the P type strained si layer/that a layer thickness is 3nm, and doping content is 5 × 10 ¹⁸cm ^-3, as the first lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows a layer thickness be the N-type strained si layer/of 22nm as channel region, doping content is 5 × 10 ¹⁷cm ^-3;

(1g) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows the P type strained si layer/that a layer thickness is 3nm, and doping content is 5 × 10 ¹⁸cm ^-3, as the second lightly-doped source drain region (LDD) layer;

(1h) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows a layer thickness be the P type SiGe layer of 350nm as source region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 25%;

Step 2, isolation preparation process:

(2a) photoetching deep trench isolation district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 μm;

(2b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill polysilicon, form deep trench isolation;

(2d) photoetching shallow trench isolation region, utilizes dry etch process, above deep trouth, etch the shallow slot that the degree of depth is 0.45 μm with source and drain isolated area;

(2e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 3, leak bonding pad preparation process:

(3a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) SiN and SiO is etched away ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.5 μm;

(3d) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth SiO ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit concentration is 5 × 10 ²⁰cm ^-3polysilicon, fill up groove, remove the polysilicon of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

Step 4, PMOS forming step:

(4a) SiN and SiO of excess surface is etched away ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(4c) SiN and SiO is etched away ₂form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.5 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3polysilicon, and gate groove to be filled up, removes surface portion polysilicon, form grid;

(4g) SiO that substrate surface is unnecessary is removed ₂with SiN barrier layer, form source region, finally form PMOS device;

Step 5, forms PMOS integrated circuit step:

(5a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth SiO ₂layer;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, forms the PMOS integrated circuit that conducting channel length is 22nm.

tool of the present invention has the following advantages:

1. the strain Si vertical-channel PMOS device channel direction that prepared by the present invention is the vertical direction of strained si layer/, then channel length is strained si layer/thickness, this thickness can pass through Si Material growth technology controlling and process, thus avoids small size photoetching, decreases the input of lithographic equipment;

2. fix component because sige material first grows the regrowth of one deck graded component in the Si vertical-channel PMOS device that prepared by the present invention, effectively can reduce dislocation, the defect concentration therefore in Si material is low, the strain Si PMOS device stable performance of preparation;

3. the present invention utilizes the anisotropy of material strain, tensile-strained si layer vertical direction lattice compresses, and causes the division of valence-band level, reduces effective mass and the scattering probability in hole, improve mobility, thus improve current driving ability and the frequency characteristic of PMOS device;

4. the Si vertical-channel PMOS device raceway groove that prepared by the present invention is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

5., in the Si vertical-channel PMOS device that prepared by the present invention, in order to effectively suppress short-channel effect, introducing lightly-doped source drain region (LDD) technique, improve device performance;

6., in the Si vertical-channel PMOS device structure that prepared by the present invention, have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of device, enhance the electric property of device;

7. the present invention prepares the maximum temperature related in strain Si vertical-channel PMOS device process is 800 DEG C, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

8. due to process proposed by the invention and existing micron order Si integrated circuit processing technology compatibility, therefore, can when any fund and equipment investment need not be added, prepare PMOS device and integrated circuit that conducting channel is length 22-45nm, the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, realizes the great-leap-forward development of domestic integrated circuit working ability.

Accompanying drawing explanation

Fig. 1 is the realization flow figure of the preparation method of strain Si vertical-channel PMOS integrated device provided by the invention and circuit;

Fig. 2 is the process schematic preparing strain Si vertical-channel PMOS integrated device and circuit by method provided by the invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of strain Si vertical-channel PMOS device, this device conducts raceway groove is hollow, and channel direction is vertical with substrate surface.

As a prioritization scheme of the embodiment of the present invention, the channel region of this device is strain Si material, and is compressive strain at channel direction.

As a prioritization scheme of the embodiment of the present invention, this device also comprises: on substrate, stack gradually a P type Si epitaxial loayer of growth, the SiGe layer of SiGe layer, the 4th P type strained si layer/, the 5th N-type strained si layer/, the 6th P type strained si layer/and the 7th fixing Ge component that Ge component fixed by the 2nd P type relaxed sige layer, the 3rd P type.

As a prioritization scheme of the embodiment of the present invention, one P type Si epitaxy layer thickness is 200 ~ 400nm, described 2nd P type relaxed sige layer thickness is 1 ~ 1.5 μm, the SiGe layer thickness that Ge component fixed by described 3rd P type is 200 ~ 300nm, described 4th P type strained si layer/thickness is 3 ~ 5nm, described 5th N-type strained si layer/thickness is 22 ~ 45nm, described 6th P type strained si layer/, and the SiGe layer thickness of the described 7th fixing Ge component is 300 ~ 400nm.

Referring to accompanying drawing 1 and accompanying drawing 2, the preparation method of strain Si vertical-channel PMOS integrated device of the present invention and circuit is described in further detail.

Embodiment 1: prepare the strain Si vertical-channel PMOS integrated device circuit that conducting channel is 45nm, concrete steps are as follows:

Step 1, prepared by epitaxial material, as shown in Figure 2 (a) shows.

(1a) choosing doping content is 5 × 10 ¹⁵cm ^-3the N-type Si substrate slice 1 of left and right;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type Si epitaxial loayer 2 of 400nm in Grown a layer thickness, doping content is 5 × 10 ¹⁵cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si epitaxial loayer grows P type SiGe resilient coating 3, the Ge content gradually variational that a layer thickness is 1.5 μm, and be distributed as from the bottom to top from 0% to 15%, doping content is 5 × 10 ¹⁸cm ^-3;

(1d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, SiGe epitaxial loayer grows a layer thickness be the P type SiGe layer 4 of 300nm as drain region, doping content is 5 × 10 ¹⁹cm ^-3, Ge component is 15%;

(1e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, SiGe epitaxial loayer grows the P type strained si layer/5a that a layer thickness is 5nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the first lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si strained layer grows a layer thickness be the N-type strained si layer/5 of 45nm as channel region, doping content is 5 × 10 ¹⁶cm ^-3.

(1g) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si strained layer grows the P type strained si layer/5b that a layer thickness is 5nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the second lightly-doped source drain region (LDD) layer;

(1h) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si strained layer grows a layer thickness be the P type SiGe layer 6 of 400nm as source region, doping content is 5 × 10 ¹⁹cm ^-3, Ge component is 15%.

Step 2, isolation preparation, as Suo Shi Fig. 2 (b) (left side is profile, and the right is vertical view).

(2a) photoetching deep trench isolation district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 3 μm;

(2b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer 7, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill Poly-Si8, form deep trench isolation 9;

(2d) photoetching shallow trench isolation region, utilizes dry etch process, above deep trouth, etch the shallow slot that the degree of depth is 0.5 μm with source and drain isolated area;

(2e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation 10.

Step 3, leaks bonding pad preparation, as shown in Figure 2 (c) (left side is profile, and the right is vertical view).

(3a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) SiN, SiO is etched away ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.55 μm;

(3d) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface growth SiO ₂layer 11, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit concentration is 10 ²⁰cm ^-3poly-Si12, fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad.

Step 4, PMOS is formed, as shown in Figure 2 (d) shows (left side is profile, and the right is vertical view).

(4a) SiN, SiO of excess surface is etched away ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(4c) SiN, SiO is etched away ₂form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.55 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer 13, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 10 in substrate surface deposit doping content ²⁰cm ^-3poly-Si14, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

(4g) SiO that substrate surface is unnecessary is removed ₂, SiN barrier layer, form source region 15, final form PMOS device 16.

Step 5, forms PMOS integrated circuit, as Suo Shi Fig. 2 (e) (left side is profile, and the right is vertical view).

(5a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface growth SiO ₂layer 17;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire 18, source metal lead-in wire 19 and gate metal lead-in wire 20, forms the PMOS integrated circuit that conducting channel length is 45nm.

Embodiment 2: prepare strain Si vertical-channel PMOS integrated device and circuit that conducting channel is 30nm, concrete steps are as follows:

Step 1, prepared by epitaxial material, as shown in Figure 2 (a) shows.

(1a) choosing doping content is 5 × 10 ¹⁵cm ^-3the N-type Si substrate slice 1 of left and right;

(1b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type Si epitaxial loayer 2 of 200nm in Grown a layer thickness, doping content is 5 × 10 ¹⁵cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si epitaxial loayer grows P type SiGe resilient coating 3, the Ge content gradually variational that a layer thickness is 1 μm, and be distributed as from the bottom to top from 0 to 20%, doping content is 7 × 10 ¹⁸cm ^-3;

(1d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, on the sige layer grow a layer thickness be the P type SiGe layer 4 of 200nm as drain region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 20%;

(1e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, SiGe epitaxial loayer grows the P type strained si layer/5a that a layer thickness is 4nm, and doping content is 10 ¹⁸cm ^-3, as the first lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si strained layer grows a layer thickness be the N-type strained si layer/5 of 30nm as channel region, doping content is 5 × 10 ¹⁷cm ^-3;

(1g) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si strained layer grows the P type strained si layer/5b that a layer thickness is 4nm, and doping content is 5 × 10 ¹⁸cm ^-3, as the second lightly-doped source drain region (LDD) layer;

(1h) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si strained layer grows a layer thickness be the P type SiGe layer 6 of 300nm as source region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 20%.

Step 2, isolation preparation, as Suo Shi Fig. 2 (b) (left side is profile, and the right is vertical view).

(2a) photoetching deep trench isolation district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2 μm;

(2b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer 7, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill Poly-Si8, form deep trench isolation 9;

(2d) photoetching shallow trench isolation region, utilizes dry etch process, above deep trouth, etch the shallow slot that the degree of depth is 0.4 μm with source and drain isolated area;

(2e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation 10.

Step 3, leaks bonding pad preparation, as shown in Figure 2 (c) (left side is profile, and the right is vertical view).

(3a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) SiN, SiO is etched away ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.45 μm;

(3d) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface growth SiO ₂layer 11, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit concentration is 5 × 10 ¹⁹cm ^-3poly-Si12, fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad.

Step 4, PMOS is formed, as shown in Figure 2 (d) shows (left side is profile, and the right is vertical view).

(4a) SiN, SiO of excess surface is etched away ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(4c) SiN, SiO is etched away ₂form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.45 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface deposition thickness ₂layer 13, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 5 × 10 in substrate surface deposit doping content ¹⁹cm ^-3poly-Si14, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

(4g) SiO that substrate surface is unnecessary is removed ₂, SiN barrier layer, form source region 15, final form PMOS device 16.

Step 5, forms PMOS integrated circuit, as Suo Shi Fig. 2 (e) (left side is profile, and the right is vertical view).

(5a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface growth SiO ₂layer 17;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire 18, source metal lead-in wire 19 and gate metal lead-in wire 20, forms the PMOS integrated circuit that conducting channel length is 30nm.

Embodiment 3: prepare strain Si vertical-channel PMOS integrated device and circuit that conducting channel is 22nm, concrete steps are as follows:

Step 1, prepared by epitaxial material, as shown in Figure 2 (a) shows.

(1a) choosing doping content is 5 × 10 ¹⁶cm ^-3the N-type Si substrate slice 1 of left and right;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type Si epitaxial loayer 2 of 300nm in Grown a layer thickness, doping content is 5 × 10 ¹⁶cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si epitaxial loayer grows P type SiGe resilient coating 3, the Ge content gradually variational that a layer thickness is 1.25 μm, and be distributed as from the bottom to top from 0% to 25%, doping content is 5 × 10 ¹⁹cm ^-3;

(1d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, SiGe epitaxial loayer grows a layer thickness be the P type SiGe layer 4 of 250nm as drain region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 25%;

(1e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, SiGe epitaxial loayer grows the P type strained si layer/5a that a layer thickness is 3nm, and doping content is 5 × 10 ¹⁸cm ^-3, as the first lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows a layer thickness be the N-type strained si layer/5 of 22nm as channel region, doping content is 5 × 10 ¹⁷cm ^-3;

(1g) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows the P type strained si layer/5b that a layer thickness is 3nm, and doping content is 5 × 10 ¹⁸cm ^-3, as the second lightly-doped source drain region (LDD) layer;

(1h) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows a layer thickness be the P type SiGe layer 6 of 350nm as source region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 25%.

Step 2, isolation preparation, as Suo Shi Fig. 2 (b) (left side is profile, and the right is vertical view).

(2a) photoetching deep trench isolation district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 μm;

(2b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer 7, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill Poly-Si8, form deep trench isolation 9;

(2d) photoetching shallow trench isolation region, utilizes dry etch process, above deep trouth, etch the shallow slot that the degree of depth is 0.45 μm with source and drain isolated area;

(2e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation 10.

Step 3, leaks bonding pad preparation, as shown in Figure 2 (c) (left side is profile, and the right is vertical view).

(3a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) SiN, SiO is etched away ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.5 μm;

(3d) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth SiO ₂layer 11, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit concentration is 5 × 10 ²⁰cm ^-3poly-Si12, fill up groove, remove the Poly-Si of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad.

Step 4, PMOS is formed, as shown in Figure 2 (d) shows (left side is profile, and the right is vertical view).

(4a) SiN, SiO of excess surface is etched away ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(4c) SiN, SiO is etched away ₂form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.5 μm;

(4e) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer 13, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3poly-Si14, and gate groove to be filled up, removes surface portion Poly-Si, form grid;

(4g) SiO that substrate surface is unnecessary is removed ₂, SiN barrier layer, form source region 15, final form PMOS device 16.

Step 5, forms PMOS integrated circuit, as Suo Shi Fig. 2 (e) (left side is profile, and the right is vertical view).

(5a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth SiO ₂layer 17;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire 18, source metal lead-in wire 19 and gate metal lead-in wire 20, forms the PMOS integrated circuit that conducting channel length is 22nm.

The strain Si vertical-channel PMOS integrated device that the embodiment of the present invention provides and preparation method's tool have the following advantages:

1. the strain Si vertical-channel PMOS device channel direction that prepared by the present invention is the vertical direction of strained si layer/, then channel length is strained si layer/thickness, this thickness can pass through Si Material growth technology controlling and process, thus avoids small size photoetching, decreases the input of lithographic equipment;

2. fix component because sige material first grows the regrowth of one deck graded component in the Si vertical-channel PMOS device that prepared by the present invention, effectively can reduce dislocation, the defect concentration therefore in Si material is low, the strain Si PMOS device stable performance of preparation;

3. the present invention utilizes the anisotropy of material strain, tensile-strained si layer vertical direction lattice compresses, and causes the division of valence-band level, reduces effective mass and the scattering probability in hole, improve mobility, thus improve current driving ability and the frequency characteristic of PMOS device;

4. the Si vertical-channel PMOS device raceway groove that prepared by the present invention is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

5., in the Si vertical-channel PMOS device that prepared by the present invention, in order to effectively suppress short-channel effect, introducing lightly-doped source drain region (LDD) technique, improve device performance;

6., in the Si vertical-channel PMOS device structure that prepared by the present invention, have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of device, enhance the electric property of device;

7. the present invention prepares the maximum temperature related in strain Si vertical-channel PMOS device process is 800 DEG C, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

8. due to process proposed by the invention and existing micron order Si integrated circuit processing technology compatibility, therefore, can when any fund and equipment investment need not be added, prepare PMOS device and integrated circuit that conducting channel is 22-45nm, the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, realizes the great-leap-forward development of domestic integrated circuit working ability.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (5)

1. a preparation method for strain Si vertical-channel PMOS integrated device, is characterized in that, the vertical PMOS device of the strain Si in described integrated device has the conducting channel of hollow; Described preparation method comprises the steps:

The first step, to choose doping content be 10 ¹⁵~ 10 ¹⁶cm ^-3n-type Si substrate slice;

Second step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, growth seven layer materials continuously on substrate: the P type Si epitaxial loayer of ground floor to be thickness be 200 ~ 400nm, doping content is 10 ¹⁵~ 10 ¹⁶cm ^-3; The second layer to be thickness the be P type relaxed sige layer of 1 ~ 1.5 μm, doping content is 5 ~ 10 × 10 ¹⁸cm ^-3, Ge content gradually variational, the Ge component at P type relaxed sige layer and P type Si epitaxial layer interface place is 0%, P type relaxed sige layer top Ge component is 15 ~ 25%; The SiGe layer of Ge component fixed by the P type of third layer to be thickness be 200 ~ 300nm, and Ge component is 15 ~ 25%, consistent with the Ge component at graded sige layer top, and doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as drain region; The P type strained si layer/of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, as the first lightly-doped source drain region (LDD) layer; Layer 5 to be thickness the be N-type strained si layer/of 22 ~ 45nm is as channel region, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 5 × 10 ¹⁷~ 5 × 10 ¹⁸cm ^-3, as the second lightly-doped source drain region (LDD) layer; The SiGe layer of the fixing Ge component of P type doping of layer 7 to be thickness be 300 ~ 400nm, Ge component is 15 ~ 25%, and its doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3, as source region;

3rd step, photoetching deep trench isolation district, utilize dry etch process, etches in isolated area the deep trouth that the degree of depth is 2 ~ 3 μm;

4th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one SiO ₂layer, all covered by deep trouth inner surface, then depositing polysilicon (Poly-Si) fills up in deep trouth, forms deep trench isolation;

5th step, photoetching shallow trench isolation region, utilize dry etch process, above deep trouth, etch the shallow slot that the degree of depth is 0.4 ~ 0.5 μm with source and drain isolated area; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

6th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away sections SiN and SiO ₂formed and leak bonding pad window; Utilize dry etch process, etch the leakage groove that the degree of depth is 0.45 ~ 0.55 μm; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, grow a SiO at substrate surface ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the SiO of drain region channel bottom ₂layer; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit doping content is in the groove 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3polysilicon, this groove is filled up, removes the polysilicon of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

7th step, etch away SiN and SiO of excess surface ₂barrier layer; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, etch away SiN and SiO ₂form grid window; Utilize dry etch process, etch the gate groove that the degree of depth is 0.45 ~ 0.55 μm; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 5 × 10 in substrate surface deposit doping content ¹⁹~ 5 × 10 ²⁰cm ^-3n-type polycrystalline silicon, and gate groove to be filled up, removes surface portion polysilicon, form grid;

The SiO that 8th step, removal substrate surface are unnecessary ₂, SiN and SiO ₂barrier layer, forms source region, finally forms PMOS device;

9th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, grow a SiO at substrate surface ₂layer, and on grid, source and drain region lithography fair lead;

Tenth step, metallization, photoetching goes between, and forms drain electrode, source electrode and gate metal lead-in wire, forms the PMOS integrated circuit that conducting channel length is 22 ~ 45nm.

2. method according to claim 1, is characterized in that, channel length is determined according to the P type strained si layer/thickness of second step deposit.

3. method according to claim 1, is characterized in that, maximum temperature involved in this preparation method determines according to chemical vapor deposition (CVD) technological temperature in second, four, five, six, seven and nine steps.

4. method according to claim 1, is characterized in that, the maximum temperature in this preparation method is less than or equal to 800 DEG C.

5. a preparation method for strain Si vertical-channel PMOS integrated circuit, is characterized in that, the vertical PMOS device of the strain Si in described integrated circuit has the conducting channel of hollow; Described preparation method comprises the steps:

Step 1, epitaxial material preparation process:

(1a) choosing doping content is 5 × 10 ¹⁶cm ^-3n-type Si substrate slice;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type Si epitaxial loayer of 300nm in Grown a layer thickness, doping content is 5 × 10 ¹⁶cm ^-3;

(1c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si epitaxial loayer grows the P type SiGe resilient coating that a layer thickness is 1.25 μm, Ge content gradually variational, Ge component is distributed as from the bottom to top from 0 to 25%, and doping content is 10 ¹⁹cm ^-3;

(1d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, SiGe epitaxial loayer grows a layer thickness be the P type SiGe layer of 250nm as drain region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 25%;

(1e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, SiGe epitaxial loayer grows the P type strained si layer/that a layer thickness is 3nm, and doping content is 5 × 10 ^18cm ^-3, as the first lightly-doped source drain region (LDD) layer;

(1f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows a layer thickness be the N-type strained si layer/of 22nm as channel region, doping content is 5 × 10 ¹⁷cm ^-3;

(1g) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows the P type strained si layer/that a layer thickness is 3nm, and doping content is 5 × 10 ¹⁸cm ^-3, as the second lightly-doped source drain region (LDD) layer;

(1h) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si strained layer grows a layer thickness be the P type SiGe layer of 350nm as source region, doping content is 5 × 10 ²⁰cm ^-3, Ge component is 25%;

Step 2, isolation preparation process:

(2a) photoetching deep trench isolation district, utilizes dry etch process, etches in isolated area the deep trouth that the degree of depth is 2.5 μm;

(2b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer, all covers deep trouth inner surface;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill polysilicon, form deep trench isolation;

(2d) photoetching shallow trench isolation region, utilizes dry etch process, above deep trouth, etch the shallow slot that the degree of depth is 0.45 μm with source and drain isolated area;

(2e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 3, leak bonding pad preparation process:

(3a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(3b) SiN and SiO is etched away ₂formed and leak bonding pad window;

(3c) utilize dry etch process, etch the leakage groove that the degree of depth is 0.5 μm;

(3d) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth SiO ₂layer, is formed and leaks trenched side-wall isolation, utilize dry etch process, remove the SiO of drain region channel bottom ₂layer;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit concentration is 5 × 10 ²⁰cm ^-3polysilicon, fill up groove, remove the polysilicon of excess surface by chemico-mechanical polishing (CMP) method, formed and leak bonding pad;

Step 4, PMOS forming step:

(4a) SiN and SiO of excess surface is etched away ₂barrier layer;

(4b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin;

(4c) SiN and SiO is etched away ₂form grid window;

(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.5 μm;

(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as gate dielectric layer;

(4f) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3polysilicon, and gate groove to be filled up, removes surface portion polysilicon, form grid;

(4g) SiO that substrate surface is unnecessary is removed ₂with SiN barrier layer, form source region, finally form PMOS device;

Step 5, forms PMOS integrated circuit step:

(5a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface growth SiO ₂layer;

(5b) lithography fair lead on grid, source and drain region;

(5c) metallize;

(5d) photoetching lead-in wire, forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, forms the PMOS integrated circuit that conducting channel length is 22nm.