CN101359631B - Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by micro process - Google Patents

Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by micro process Download PDF

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CN101359631B
CN101359631B CN2008101509352A CN200810150935A CN101359631B CN 101359631 B CN101359631 B CN 101359631B CN 2008101509352 A CN2008101509352 A CN 2008101509352A CN 200810150935 A CN200810150935 A CN 200810150935A CN 101359631 B CN101359631 B CN 101359631B
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trap
sio
sin
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CN101359631A (en
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胡辉勇
张鹤鸣
舒斌
宣荣喜
戴显英
宋建军
赵丽霞
屈江涛
徐小波
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Xidian University
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Abstract

The invention discloses a method based on micron-scale technique for fabricating a nano-scale CMOS integrated circuit which has a polycrystal SiGe grid. The process includes the following steps: fabricating an N/P well and growing a Poly- SiGe/SiN/Poly-Si multi-layer structure on the N/P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching away the SiO2layer on the surface of the substrate, except the SiO2 at the side wall of Poly-Si; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the surface of SiN; based on the ratio of SiN to SiO2(2:1), etching the SiN, except the SiN in the protective area on the side wall of SiO2; based on the etching ratio of Poly-SiGe to SiO2(50:1), etching the Poly-SiGe, except the Poly-SiGein the protective area on the side wall of SiO2 so as to form an n/p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n/p MOSFET grid so as to form ann/p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 45-90nm. The method can fabricate a CMOS integrated circuitwhich has a polycrystal SiGe grid on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

Prepare the polycrystal SiGe gate nano-scale CMOS integrated circuit method with micro process
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of existing micron order Si integrated circuit fabrication process that utilizes, make the method for nanoscale Si integrated circuit.
Background technology
Electronic information technology is the core technology of national economy, and it serves the national economy every field, and microelectric technique is the key of electronic information technology, and integrated circuit is the key in the key especially.Integrated circuit is since 1958 come out, and development speed is surprising, becomes the foundation stone of the core of information science technology and the national economic development, national defense construction, and world politics, economy and culture have been produced tremendous influence.As with fastest developing speed on the human history, have the greatest impact, most widely used technology, integrated circuit has become the important symbol of weighing national science technical merit, overall national strength and a defense force.Adopt how many direct signs of its system's advance especially for integrated circuit in the machine system.
Microelectric technique, especially Si integrated circuit technique develop so far, and whole world number is thrown the people with trillion dollars equipment and technology, have made Si base technology form very powerful industry ability.Simultaneously, long-term scientific research drops into and also makes the understanding of people to Si and technology thereof, reaches very deep, thorough stage, therefore in IC industry, the Si technology is a mainstream technology, and the Si integrated circuit (IC) products is a main product, accounts for more than 90% of IC industry.Although microelectronics has obtained very big progress in research aspect compound semiconductor and other new material and the application in some field, but from now on 10～20 years, the Si base CMOS integrated circuit technology that microelectric technique will constantly be dwindled with size is as mainstream technology, and is widely used in and the every field of the closely bound up national economy of producing, live.
Last century the mid-1960s, the height of U.S. fairchild company is stepped on. the mole doctor delivered after well-known " Moore's Law ", this theorem is pointed out: the transistor size on the integrated circuit (IC) chip, per approximately 18 months increase the by 1 times, performance also promotes 1 times.Simultaneously, the unit functional cost of integrated circuit reduces about 25% every year on average.Over more than 40 year, the world semiconductor industry constantly advances according to this law all the time.Represent in the global information summit that February in 2004, the CEO Ke Laigebeiruite of Intel on the 23rd held in Tokyo that Moore's Law will be still effective at following 15 to 20 years.The technology dynamics that the promotion Moore's Law moves on is: constantly dwindle the chip feature size.At present, external 90nm technology has entered the large-scale production stage, and 60nm technical office is in the introduction period, the 45nm technology is being done the R﹠D work in early stage, according to ITRS ITRS, the 45nm technology can enter large-scale production in 2010, and 2018 is 18nm.
Make the CMOS integrated circuit of so little characteristic size, the process equipment that just needs a new generation, because still there is not to solve preferably at present the technology of on existing equipment, making chip of future generation, therefore can only improve technology level by the renewal of process equipment.Through accumulation for many years, at present the whole world in microelectronic industry equipment and the technology input above trillion dollars, iff the lifting that obtains technology by the update of equipment, with per 18 months superseded generation equipment, this will cause the huge resource and the waste of the energy, cause production cost to rise, therefore, this present situation has seriously restricted the development of semicon industry.
At present, poly-Si grid substituted metal grid become the grid material of main flow, still are p type poly-Si but no matter take n type poly-Si, and its adjusting range to device threshold voltage is all little.In order to adjust the threshold voltage of device more broadly, domestic and international most of manufacturer takes after well region forms, and injects by once more well region being carried out ion, changes the method for well region doping content, the threshold voltage of trim.But this method is limited to the device threshold voltage adjusting range, and has increased the difficulty that technology is made, and makes it to have become a technology bottleneck problem.
Summary of the invention
The object of the present invention is to provide and a kind ofly prepare the polycrystal SiGe gate nano-scale CMOS integrated circuit method with micro process, to be implemented under the condition that does not change existing equipment and increase cost, preparing conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 45～90nm.
For achieving the above object, preparation provided by the invention has the method for the nano-scale CMOS integrated circuit of polycrystal SiGe gate, carries out as follows:
The first step. thermal oxidation one deck SiO on the Si substrate 2Resilient coating, deposit layer of sin on this resilient coating is used for sheltering of well region injection;
Second step. difference photoetching N trap and P trap on the SiN layer, carry out the injection and the propelling of N trap and P trap simultaneously, form N trap and P trap respectively at the Si substrate;
The 3rd the step. etch away N trap and P trap top and between SiN layer and SiO 2Layer, and then at entire substrate superficial growth one deck SiO 2Resilient coating and SiN layer, photoetching on the SiN layer, oxidation form isolated area;
The 4th step. the thick SiO of thermal oxide growth 4～5nm on N trap and P trap 2Gate dielectric layer, n type doped P loy-SiGe that deposit one deck 120～150nm is thick on N trap and P trap respectively and p type doped P loy-SiGe again, as grid, the Ge component is 0.05～0.3, doping content＞10 20Cm -3
The 5th step. the deposit layer thickness of growing is the SiN of 30～60nm on Ploy-Si, as the protective layer of grid;
The 6th step. the thick Ploy-Si of deposit one deck 100～150nm again on the SiN layer, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
The 7th step. in the zone of Ploy-Si, etch the window that coincident circuit requires;
The 8th step. the thick SiO of deposit one deck 70～120nm on whole Si substrate 2Dielectric layer covers whole surface;
The 9th step. the lip-deep SiO of etched substrate 2, the SiO of reservation Ploy-Si sidewall 2The etch rate that utilizes Ploy-Si and SiN is than (11: 1), the Ploy-Si on etching SiN surface; Utilize SiN and SiO 2Etch rate is than (2: 1), etching SiO 2SiN beyond the sidewall protection zone; Utilize Ploy-SiGe and SiO again 2Etch rate than (50: 1), etching SiO 2Ploy-SiGe beyond the sidewall protection zone forms the grid of n/pMOSFET, and on well region the thick SiO of deposit one deck 3～5nm 2, the protective layer of formation gate lateral wall;
The tenth step. carry out n type ion at the P well region respectively and inject, autoregistration generates source region and the drain region of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region and the drain region of pMOSFET;
The 11 step. photoetching lead-in wire on grid, source and the drain region of n/pMOSFET, constituting conducting channel is the CMOS integrated circuit of 45～90nm.
Describedly etching the window that coincident circuit requires in the zone of Ploy-Si, is to determine that according to the minimum line size of micro process processing and the size of alignment precision width is got 1.8～3 μ m usually.
Described grid length is according to the SiO of the 8th step deposit 2Thickness is determined, is got 45～90nm usually.
The present invention has following advantage:
1. the present invention is owing to utilized Ploy-Si and SiN, SiN and SiO in the plasma etching industrial 2, Ploy-SiGe and SiO 2Etch rate than and self-registered technology, can on micron order Si integrated circuit technology platform, produce the CMOS integrated circuit of conducting channel 45～90nm with polycrystal SiGe gate;
2. because process proposed by the invention is process ripe in the existing micron order Si integrated circuit technology platform, therefore, the nano-scale CMOS integrated circuit implementation method with polycrystal SiGe gate proposed by the invention is compatible mutually with existing micron order Si integrated circuit technology;
3. because process proposed by the invention adopts the poly-SiGe material as gate medium, its work function changes with the variation of Ge component, by Ge component in the poly-SiGe grid of regulating CMOS, make the nMOSFET threshold voltage to adjust continuously, therefore, realize the adjustment of cmos device threshold voltage, reduced processing step, reduced technology difficulty;
4. all can in existing micron order Si integrated circuit technology platform, realize owing to process proposed by the invention, therefore can be under the situation that need not append any fund and equipment input, the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, and make the performance of the CMOS integrated circuit of its preparation improve for 3～5 generations;
5. because process proposed by the invention can realize the CMOS integrated circuit of conducting channel 45～90nm, therefore, along with reducing of conducting channel size, the integrated level of integrated circuit can significantly improve, thereby has reduced the manufacturing cost of lsi unit area;
6. because little with the conducting channel of device in the CMOS integrated circuit of process preparation of the present invention, therefore, the operating frequency of integrated circuit significantly improves, and has realized the great-leap-forward development of domestic integrated circuit level of processing.
Description of drawings
Fig. 1 is a process chart of the present invention;
Fig. 2 is the process schematic diagram that has the CMOS integrated circuit of polycrystal SiGe gate with the inventive method preparation.
Embodiment
Following with reference to accompanying drawing 1 and accompanying drawing 2, the technological process that the present invention's preparation is had the nano-scale CMOS integrated circuit of polycrystal SiGe gate describes in further detail.
Embodiment 1: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 45nm on the Si substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type Si substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 20nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 110nm of low pressure chemical vapor deposition LPCVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2Layer carries out the N trap simultaneously and advances, and forms N trap 5 on substrate 1;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 2 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 15nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 80nm with the method deposit of normal pressure chemical vapor deposition APCVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 0.5 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 4nm 2Gate dielectric layer 7;
(4b) at SiO 2The method of using molecular beam epitaxy MBE on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 120nm, as grid, the Ge component is 0.3, doping content＞10 20Cm -3
(4c) the thick SiN layer 9 of method deposit growth 30nm of application LPCVD on Ploy-SiGe is as the protective layer of grid;
(4d) use the thick Ploy-Si layer 10 of method deposit 100nm of LPCVD again on the SiN layer, this one deck is mainly as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 1.8 μ m usually.
Step 5, deposit SiO 2Medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiO of method deposit one deck 70nm of LPCVD 2Dielectric layer 11 covers whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) utilize the SiO of the method for dry etching with substrate surface 2Etch away, keep the SiO of Ploy-Si sidewall 2
(6b) etch rate that utilizes Ploy-Si and SiN is than (11: 1), and the Ploy-Si on SiN surface is all etched away;
(6c) utilize SiN and SiO 2Etch rate than (2: 1), and with SiO 2Sidewall is protected, and etches away SiO 2SiN below the SiN beyond the sidewall protection zone, reservation sidewall;
(6d) utilize Ploy-SiGe and SiO 2Etch rate than (50: 1), and with SiO 2Sidewall is protected, and etches away SiO again 2Ploy-SiGe below the Ploy-SiGe beyond the sidewall protection zone, reservation sidewall forms the grid s of nMOSFET and the grid sa of pMOSFET, and the length of this grid is according to the SiO of step 5 deposit 2Thickness is determined, is got 45nm usually;
(6e) utilize wet etching to fall SiO 2Sidewall;
(6f) method thick SiO of deposit one deck 3nm on well region of usefulness LPCVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 45nm.
Embodiment 2: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 65nm on the SOI substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type SOI substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 30nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 120nm of APCVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2, carry out the N trap simultaneously and advance, on substrate 1, form N trap 5;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 2.5 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 20nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 90nm with the method deposit of APCVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the place that the isolated area partial thermal oxidation forms 0.8 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 4nm 2Gate dielectric layer 7;
(4b) at SiO 2The method of using MBE on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 130nm, as grid, the Ge component is 0.1, doping content＞10 20Cm -3
(4c) the thick SiN layer 9 of method deposit growth 45nm of application APCVD on Ploy-SiGe is as the protective layer of grid;
(4d) use the thick Ploy-Si layer 10 of method deposit 130nm of APCVD again on the SiN layer, this one deck is mainly as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 2.5 μ m usually.
Step 5, deposit SiO 2Medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiO of method deposit one deck 90nm of APCVD 2Dielectric layer 11 covers whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) utilize the SiO of the method for dry etching with substrate surface 2Etch away, keep the SiO of Ploy-Si sidewall 2
(6b) etch rate that utilizes Ploy-Si and SiN is than (11: 1), and the Ploy-Si on SiN surface is all etched away;
(6c) utilize SiN and SiO 2Etch rate than (2: 1), and with SiO 2Sidewall is protected, and etches away SiO 2SiN below the SiN beyond the sidewall protection zone, reservation sidewall;
(6d) utilize Ploy-SiGe and SiO 2Etch rate than (50: 1), and with SiO 2Sidewall is protected, and etches away SiO again 2Ploy-SiGe below the Ploy-SiGe beyond the sidewall protection zone, reservation sidewall forms the grid s of nMOSFET and the grid sa of pMOSFET, and the length of this grid is according to the SiO of step 5 deposit 2Thickness is determined, is got 65nm usually;
(6e) utilize wet etching to fall SiO 2Sidewall;
(6f) method thick SiO of deposit one deck 4nm on well region of usefulness APCVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 65nm.
Embodiment 3: the preparation conducting channel is the CMOS integrated circuit with polycrystal SiGe gate of 90nm on the Si substrate, and concrete steps are as follows:
Step 1, the deposit masking layer is shown in Fig. 2 (a).
(1a) choose the crystal orientation for＜100 〉, doping content is 10 15Cm -3About p type Si substrate slice 1;
(1b) the thick SiO of thermal oxidation one deck 40nm on substrate 2 Resilient coating 2;
(1c) at SiO 2With the thick SiN layer 3 of method deposit 140nm of plasma-reinforced chemical vapor deposition PECVD, be used for sheltering of well region injection on the resilient coating.
Step 2 forms well region, shown in Fig. 2 (b).
(2a) on SiN layer 3, distinguish photoetching P well area 4 and N well area 5 according to alternate order;
(2b) inject boron and form p type zone, generate SiO in the oxidation of P well region surface heat at the P well area 2, carry out the P trap simultaneously and advance, on substrate 1, form P trap 4;
(2c) inject phosphorus and form n type zone, generate SiO in the oxidation of N well region surface heat at the N well area 2, carry out the N trap simultaneously and advance, on substrate 1, form N trap 5;
(2d) in temperature be 800 ℃ N 2Under the atmosphere, it is dark simultaneously N trap and P trap to be continued to be advanced to 3 μ m.
Step 3 forms isolated area, shown in Fig. 2 (c).
(3a) wet etching falls the top of P trap 4 and N trap 5 and between the two SiN layer and SiO 2Layer;
(3b) at the thick SiO of entire substrate surface heat oxidation one deck 30nm 2Resilient coating;
(3c) at SiO 2Be about the thick SiN layer of 100nm with the method deposit of PECVD growth one deck on the resilient coating, and on this SiN layer photoetching field isolated area;
(3d) isolate 6, N trap and P trap are isolated in the field that the isolated area partial thermal oxidation forms 1 μ m;
(3e) wet etching falls the SiN and the SiO on P trap 4 and N trap 5 surfaces 2Layer.
Step 4, deposit poly-Si and etching window are shown in Fig. 2 (d).
(4a) at P trap 4 and the thick SiO of N trap 5 Film by Thermal Oxidation 5nm 2Gate dielectric layer 7;
(4b) at SiO 2The method of using MBE on the gate dielectric layer 7 respectively on N trap and P trap growth thickness be n type doped P loy-SiGe layer 8a and the p type doped P loy-SiGe layer 8 of 150nm, as grid, the Ge component is 0.05, doping content＞10 20Cm -3
(4c) the thick SiN layer 9 of method deposit growth 60nm of application PECVD on Ploy-SiGe is as the protective layer of grid;
(4d) use the thick Ploy-Si layer 10 of method deposit 150nm of PECVD again on the SiN layer, this one deck is mainly as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
(4e) according to the circuit needs, in the zone of Ploy-Si, etch the window 10a that coincident circuit requires, the size of this window determines that according to the minimum line size of micro process processing and the size of alignment precision width is got 3 μ m usually.
Step 5, deposit SiO 2Medium is shown in Fig. 2 (e).
On whole Si sheet, use the thick SiO of method deposit one deck 120nm of PECVD 2Dielectric layer 11 covers whole surface.
Step 6 forms grid, and at gate lateral wall deposit protective layer, shown in Fig. 2 (f).
(6a) utilize the SiO of the method for dry etching with substrate surface 2Etch away, keep the SiO of Ploy-Si sidewall 2
(6b) etch rate that utilizes Ploy-Si and SiN is than (11: 1), and the Ploy-Si on SiN surface is all etched away;
(6c) utilize SiN and SiO 2Etch rate than (2: 1), and with SiO 2Sidewall is protected, and etches away SiO 2SiN below the SiN beyond the sidewall protection zone, reservation sidewall;
(6d) utilize Ploy-SiGe and SiO 2Etch rate than (50: 1), and with SiO 2Sidewall is protected, and etches away SiO again 2Ploy-SiGe below the Ploy-SiGe beyond the sidewall protection zone, reservation sidewall forms the grid s of nMOSFET and the grid sa of pMOSFET, and the length of this grid is according to the SiO of step 5 deposit 2Thickness is determined, is got 90nm usually;
(6e) utilize wet etching to fall SiO 2Sidewall;
(6f) method thick SiO of deposit one deck 5nm on well region of usefulness PECVD 2, as the protective layer 12 of gate side.
Step 7 forms the n/pMOSFET device architecture, shown in Fig. 2 (g).
(7a) carry out n type ion at the P well region and inject, autoregistration generates source region 13 and the drain region 14 of nMOSFET, forms nMOSFET device 17;
(7b) carry out p type ion at the N well region and inject, autoregistration generates source region 15 and the drain region 16 of pMOSFET, forms pMOSFET device 18.
Step 8 constitutes the CMOS integrated circuit.
Photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 90nm.
Above embodiment does not constitute any limitation of the invention.

Claims (4)

1. one kind prepares the polycrystal SiGe gate nano-scale CMOS integrated circuit method with micro process, carries out as follows:
The first step. go up thermal oxidation the one SiO at Si substrate (1) 2Layer (2), as resilient coating, deposit the one SiN layer (3) on this resilient coating is used for sheltering of well region injection;
Second step. difference photoetching N trap and P trap on a SiN layer, carry out N trap and P trap simultaneously and advance, form P trap (4) and N trap (5) respectively at Si substrate (1);
The 3rd the step. etch away P trap (4) and N trap (5) top and between a SiN layer and a SiO 2Layer, and then at entire substrate superficial growth the 2nd SiO 2Layer, as resilient coating and the 2nd SiN layer, photoetching field isolated area on the 2nd SiN layer, oxidation forms isolated area (6), and wet etching falls the 2nd SiN layer and the 2nd SiO on P trap and N trap surface 2Layer;
The 4th step. thermal oxide growth thickness is the Three S's iO of 4～5nm on N trap and P trap 2The layer (7), as gate dielectric layer, more respectively on N trap and P trap deposit one layer thickness be n type doped P loy-SiGe layer (8a) and the p type doped P loy-SiGe layer (8) of 120～150nm, as grid, the Ge component is 0.05～0.3, doping content＞10 20Cm -3
The 5th step. the deposit layer thickness of growing is the Three S's iN layer (9) of 30～60nm on Ploy-SiGe, as the protective layer of grid;
The 6th step. the Ploy-Si (10) that deposit one deck 100～150nm is thick again on Three S's iN layer, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
The 7th step. in the zone of Ploy-Si, etch the window (10a) that coincident circuit requires;
The 8th step. the 4th thick SiO of deposit one deck 70～120nm on whole Si substrate 2Layer (11) as dielectric layer, covers whole surface;
The 9th step. lip-deep the 4th SiO of etched substrate 2Layer, the 4th SiO of reservation Ploy-Si sidewall 2Layer; Utilize 11: 1 etch rate of Ploy-Si and SiN ratio, the Ploy-Si of etching Three S's iN laminar surface; Utilize SiN and SiO 22: 1 etch rate ratio, etching the 4th SiO 2Three S's iN layer beyond the layer sidewall protection zone; Utilize Ploy-SiGe and SiO again 250: 1 etch rate ratio, etching the 4th SiO 2Ploy-SiGe beyond the layer sidewall protection zone forms the grid (s) of nMOSFET and the grid (sa) of pMOSFET, and on well region the 5th thick SiO of deposit one deck 3～5nm 2Layer (12), the protective layer of formation gate lateral wall;
The tenth step. carry out n type ion at the P well region and inject, autoregistration generates source region (13) and drain region (14) of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region (15) and drain region (16) of pMOSFET;
The 11 step. photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 45～90nm.
2. method according to claim 1, wherein, the 7th goes on foot the described window that coincident circuit requires that etches in the zone of Ploy-Si, is to determine that according to the minimum line size of micro process processing and the size of alignment precision width is got 1.8～3 μ m.
3. method according to claim 1, wherein, described formation grid of the 9th step, its length is according to the SiO of the 8th step deposit 2Thickness is determined, is got 45～90nm.
4. one kind prepares the polycrystal SiGe gate nano-scale CMOS integrated circuit method with micro process, comprises the steps:
The 1st step. go up thermal oxidation the one SiO at Si substrate (1) 2Layer (2) as resilient coating, with method deposit the one SiN layer (3) of LPCVD, is used for sheltering of well region injection on this resilient coating;
The 2nd step. difference photoetching N trap and P trap on a SiN layer, carry out N trap and P trap simultaneously and advance, form P trap (4) and N trap (5) respectively at Si substrate (1);
The 3rd the step. etch away P trap (4) and N trap (5) top and between a SiN layer and a SiO 2Layer, and then at entire substrate superficial growth the 2nd SiO 2Layer, as resilient coating and the 2nd SiN layer, photoetching field isolated area on the 2nd SiN layer, oxidation forms isolated area (6), and wet etching falls the 2nd SiN layer and the 2nd SiO on P trap and N trap surface 2Layer;
The 4th step. thermal oxide growth thickness is the Three S's iO of 4nm on N trap and P trap 2Layer (7) as gate dielectric layer, is n type doped P loy-SiGe layer (8a) and the p type doped P loy-SiGe layer (8) of 120nm with the method for the MBE layer thickness of growing on N trap and P trap respectively again, and as grid, the Ge component is 0.3, doping content＞10 20Cm - 3
The 5th step. the method deposit of using LPCVD on the Ploy-SiGe layer thickness of growing is the Three S's iN layer (9) of 30nm, as the protective layer of grid;
The 6th step. on Three S's iN layer, use the thick Ploy-Si (10) of method deposit one deck 100nm of LPCVD again, as the auxiliary layer in the manufacture process, the auxiliary sidewall that generates;
The 7th step. in the zone of Ploy-Si, etch the window (10a) that coincident circuit requires;
The 8th step. on whole Si substrate, use the 4th thick SiO of method deposit one deck 70nm of LPCVD 2Layer (11) as dielectric layer, covers whole surface;
The 9th step. lip-deep the 4th SiO of etched substrate 2Layer, the 4th SiO of reservation Ploy-Si sidewall 2Layer; Utilize 11: 1 etch rate of Ploy-Si and SiN ratio, the Ploy-Si of etching Three S's iN laminar surface; Utilize SiN and SiO 22: 1 etch rate ratio, etching the 4th SiO 2Three S's iN layer beyond the layer sidewall protection zone; Utilize Ploy-SiGe and SiO again 250: 1 etch rate ratio, etching the 4th SiO 2Ploy-SiGe beyond the layer sidewall protection zone forms the grid (s) of nMOSFET and the grid (sa) of pMOSFET, uses method the 5th thick SiO of deposit one deck 3nm on well region of LPCVD at last 2Layer (12), the protective layer of formation gate lateral wall;
The 10th step. carry out n type ion at the P well region and inject, autoregistration generates source region (13) and drain region (14) of nMOSFET, carries out p type ion at the N well region and injects, and autoregistration generates source region (15) and drain region (16) of pMOSFET;
The 11st step. photoetching lead-in wire on grid, source and the drain region of nMOSFET and pMOSFET, constituting conducting channel is the CMOS integrated circuit of 45nm.
CN2008101509352A 2008-09-12 2008-09-12 Method for preparing polycrystal SiGe gate nano CMOS integrated circuit by micro process Expired - Fee Related CN101359631B (en)

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CN1366711A (en) * 2000-02-17 2002-08-28 皇家菲利浦电子有限公司 Semiconductor device with integrated CMOS circuit with MOS transistors having silicon-germanium (Sil-Gex) gate electrodes, and method for manufacturing same
CN101027779A (en) * 2004-09-17 2007-08-29 应用材料公司 Poly-silicon-germanium gate stack and method for forming the same

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