CN105336694B - A kind of germanium base CMOS preparation method - Google Patents

A kind of germanium base CMOS preparation method Download PDF

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CN105336694B
CN105336694B CN201510657587.8A CN201510657587A CN105336694B CN 105336694 B CN105336694 B CN 105336694B CN 201510657587 A CN201510657587 A CN 201510657587A CN 105336694 B CN105336694 B CN 105336694B
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deposit
preparation
sio
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germanium base
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CN105336694A (en
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黎明
林猛
黄如
安霞
张冰馨
赵阳
郝培霖
张兴
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

The invention discloses a kind of germanium base CMOS preparation method, belong to field of semiconductor devices.This method handles NMOSFETs and PMOSFETs in CMOS using different passivating methods, i.e. is used in PMOSFETs and be advantageous to the GeOx (wherein 0 that hole mobility improves<X≤2) passivation layer, and the nitrogen passivation improved in NMOSFETs using electron mobility is advantageous to, while realize the raising of two kinds of carrier mobilities.The technique of the present invention is completed and conventional germanium process compatible, it is easy to accomplish.

Description

A kind of germanium base CMOS preparation method
Technical field
The invention belongs to field of semiconductor devices, and in particular to a kind of germanium base CMOS preparation flow.
Background technology
As silicon based metal-Oxide-Semiconductor Field effect transistor (MOSFET) physical dimension narrows down to nanoscale, The dual limit that tradition is faced with physics and technology by reducing the method for device size improving performance and integrated level tests.In order to It is to introduce mobility channel material further to improve one of device performance, effective ways.Due to there is higher electronics simultaneously With hole mobility (under room temperature (300K), the electron mobility of germanium raceway groove is 2.4 times of silicon, and hole mobility is 4 times of silicon), Germanium material and germanium base device turn into a kind of and selected.
But germanium base CMOS performances can not also meet the requirement of high property at present, main cause is to be difficult to realize simultaneously in CMOS High electronics and hole mobility, especially electron mobility.For germanium base MOS device, generally use hafnium is situated between as grid Matter, but hafnium is deposited directly in germanium substrate, germanium substrate can quilts in high K deposition process and in follow-up thermal process Oxidation, form the GeO of heat endurance differencex(x<2), cause device performance degeneration, therefore need, to substrate surface Passivation Treatment, to suppress Deposit the performance degradation in gate medium and subsequent thermal process.From improve mobility from the perspective of, NMOSFETs with PMOSFETs needs different passivating methods.The passivating method reported for work at present has nitrogen passivation, GeO2Passivation layer, Si passivation layers are dilute Native oxide passivation layer etc..But one kind in passivating method more than simple use can not be realized while improve germanium base CMOS Electronics and hole mobility in device.Have been reported and claim nitrogen passivation to be advantageous to improve electron mobility, and GeO2Passivation layer is favourable In the raising of hole mobility.
The content of the invention
The present invention proposes a kind of preparation flow suitable for germanium base CMOS, and NMOSFETs and PMOSFETs are respectively adopted Nitrogen passivation and nitrogen passivation, while realize the raising of electronics and hole mobility in germanium based CMOS devices.
The concrete technical scheme of the present invention is as follows：
A kind of germanium base CMOS preparation method, comprises the following steps：
1) on germanium base substrate trap preparation, i.e. N traps and p-well：
1-1) germanium base substrate is cleaned, the deposit injection masking layer on germanium base substrate；
1-2) impurity needed for injection and activation；
1-3) remove injection masking layer；
2) isolation structure is formed：
2-1) place isolation channel is formed；
2-2) field oxide deposits；
3) PMOS device structure is formed：
3-1) PMOS device active area perforate, improve substrate surface for roughness with the method for sacrificing oxidation；
3-2) GeOx (wherein 0<X≤2) passivation layer formed；
3-3) deposit gate medium；
3-4) deposit gate electrode；
4) protective layer SiO is deposited2；
5) SiO of nmos device overlying regions is removed2And grid metal；
6) nmos device structure is formed：
6-1) nmos device active area perforate, improve substrate surface for roughness with the method for sacrificing oxidation；
6-2) nitrogen passivation is formed；
6-3) deposit gate electrode；
6-4) deposit grid metal；
6-5) the grid metal in photoetching protection nmos device region, removes remaining region gate electrode, and the protective layer of lower section SiO2；
7) patterned gate electrode is formed：
8) source, leakage and contact are formed：
8-1) form sidewall structure；
8-2) source, leakage injection and activation；
8-3) separation layer deposit, perforate, deposit contacting metal.
Step 1-1) in, germanium base substrate can be body Ge substrates, epitaxial Germanium (Germanium-on-silicon) lining on silicon Bottom or GeOI (Germanium on Insulator) substrate etc..Situation, doping concentration are adulterated for the germanium base substrate<1× 15cm-3；, germanium base substrate surface is cleaned, removes surface contamination and natural oxidizing layer, then deposit injection masking layer.Injection It can be SiO to shelter layer material2、Al2O3Or Y2O3Deng its thickness is 5~20nm.Masking layer material deposition methods have ALD, PVD, MBE, PLD, MOCVD, PECVD or ICPCVD etc..
Step 1-2) in, the preparation for p-well, it is usually injected into boron ion；Preparation for N traps, is usually injected into phosphonium ion； Depending on the depth and concentration of implantation dosage and energy trap as needed.For boron, implantation dosage is 5 × 1010~1 × 1014cm-2, Implantation Energy is 30keV~120keV；For phosphorus, implantation dosage is 5 × 1010~1 × 1014cm-2, Implantation Energy 50keV ~180keV.When injecting required impurity, using the method injected twice：High-energy injection, makes impurity be injected into substrate In deeper region；Low energy injection, makes impurity be injected into the region close to substrate surface.General use has a constant inclination The injection of rake angle, usually 7 ° injections.Activation for impurity in trap, in N2Atmosphere carries out 500 DEG C of 60s annealing.
Step 1-3) in, remove the masking layer of injection with the HF of dilution, wherein HF is diluted, HF:H2O=1:30.
Step 2-1) in, place isolation channel, which is formed, includes lithographic definition isolation channel figure, and it is deep that etching forms 300~500nm Groove.
Step 2-2) in, 400~500nm of deposit field oxide, such as SiO2, Al2O3, Y2O3Deng the method for deposit There are PVD, PLD, PECVD or ICPCVD etc., but be not limited to above-mentioned deposition process.
Step 3-1) in, lithographic definition PMOS device active area, remove the field oxide of active region.With sacrifice oxygen The method of change improves substrate surface for roughness, and specific method is as follows：Substrate is first immersed in the H that concentration is 30%2O2Middle 30s, use Deionized water rushes 1min, then substrate is immersed in into 1min in the HCl that concentration is 36%, and 1min is rushed with deionized water；So repeat 3 ~4 cycles.
Step 3-2) in, GeOx (wherein 0<X≤2) passivation layer formation, can use thermal oxide, oxygen plasma oxygen Change, the method for ozone oxidation, the method that deposit can also be used.Ultimately form GeO2Thickness be 0.5~2nm.
Step 3-3) in, the gate dielectric material of deposit has：Al2O3、Y2O3、HfO2、ZrO2、La2O3Deng, but be not limited to Give an account of material.The method of deposit has ALD, MBE, PLD, MOCVD etc., but is not limited to above-mentioned deposition process.Deposit gate medium Thickness be 1.5~5nm.
Step 3-4) in, gate electrode can use polysilicon gate, metal gate or FUSI grid etc..The method of deposit have ALD, PVD, PLD, MOCVD, PECVD or LPCVD etc., but it is not limited to above-mentioned deposition process.
In step 4), protective layer SiO2Thickness be 10~20nm, the method for deposit has PVD, PLD, PECVD or ICPCVD Deng.
In step 5), graphic definition nmos device region, the SiO in the region is removed2And grid metal.
Step 6-1) in, lithographic definition nmos device active area, remove the field oxide of active region.With sacrifice oxygen The method of change improves substrate surface for roughness, and specific method is as follows：Substrate is first immersed in the H that concentration is 30%2O2Middle 30s, use Deionized water rushes 1min, then substrate is immersed in into 1min in the HCl that concentration is 36%, and 1min is rushed with deionized water；So repeat 3 ~4 cycles.
Step 6-2) in, nitrogen passivation is formed, and can use NH3The method of thermal annealing or nitrogen plasma treatment.
Step 6-3) in, the gate dielectric material of deposit has：Al2O3、Y2O3、HfO2、ZrO2、La2O3Deng, but be not limited to Give an account of material.The method of deposit has ALD, MBE, PLD, MOCVD etc., but is not limited to above-mentioned deposition process.Deposit gate medium Thickness be 1.5~5nm.
Step 6-4) in, gate electrode can use polysilicon gate, metal gate or FUSI grid etc..The method of deposit have ALD, PVD, PLD, MOCVD, PECVD or LPCVD etc., but it is not limited to above-mentioned deposition process.
Step 6-5) in, the gate electrode in photoetching protection nmos device region, etching removes the gate electrode in other regions, then Protective layer SiO is removed with the HF of dilution2。
In step 7), lithographic definition gate electrode figure, and etch.
Step 8-1) in grid both sides formation side wall.Side wall can be by depositing SiO2Or SiNxAnd etch and form side wall, First SiO can also be used2SiN againxBilateral wall.
Step 8-2) source, leakage injection dosage, for PMOSFETs, the dosage of B injection is 5E14~5E15cm-2, note It is 10~20keV to enter energy；For NMOSFETs, the dosage of P injection is 5E14~5E15cm-2, Implantation Energy be 20~ 50keV.For source, the activation of leakage impurity, in N2Atmosphere carries out 500 DEG C of 60s annealing.
Advantage of the present invention is as follows：
Using in the NMOSFETs and PMOSFETs, PMOSFETs in different passivating method processing CMOS using being advantageous to The GeOx (wherein 0 that hole mobility improves<X≤2) passivation layer, and in NMOSFETs using be advantageous to electron mobility improve Nitrogen passivation, while realize the raising of two kinds of carrier mobilities.In addition, technique completes the germanium process compatible with routine, it is easy to real It is existing.
Brief description of the drawings
Fig. 1 is the flow chart of the method for the invention.
Fig. 2 show embodiment to germanium base CMOS preparation method schematic diagrames；
In figure：1-germanium substrate；2—Al2O3；3-p-well；4-N traps；5-prepare the germanium substrate of trap；6-prepare isolation channel Germanium substrate；The SiO of 7-place isolation2；8-GeOx (wherein 0<x≤2)；9—Al2O3；10—TiNx；11—SiO2；12— GeOxNy；13—Al2O3；14—TiNx；15—SiO2；16-side wall SiO2；17-B doped regions；18-P doped regions；19-every From medium SiO2。
Embodiment
Below in conjunction with accompanying drawing, method of the present invention is described further by specific embodiment.
1) germanium substrate is cleaned, and removes surface oxide layer, as shown in Fig. 2 (a)；
2) one layer of injection masking layer is deposited in the germanium substrate through over cleaning, the material of deposit can be SiO2, Al2O3, Y2O3Deng material, the method for deposit has ALD, PVD, MBE, PLD, MOCVD, PECVD, ICPCVD etc., and deposition thickness is 5~20nm； The present embodiment preferably uses ALD deposition 10nm Al2O3, as shown in Fig. 2 (b)；
3) impurity needed for injection, p-well is prepared, injects boron (B) ion；N traps are prepared, inject phosphorus (P) ion；Implantation dosage With energy depending on the depth and concentration of trap as needed.For p-well, lithographic definition p-well region, injection boron (B), implantation dosage For 5 × 1010~1 × 1014cm-2, Implantation Energy is generally 30keV~120keV；For N traps, lithographic definition N well region, injection Phosphorus (P), implantation dosage are 5 × 1010~1 × 1014cm-2, Implantation Energy is generally 50keV~180keV；It can typically use twice The method of injection, a high-energy injection, impurity is injected into the higher depth in substrate, a low energy injection, note impurity Enter to the region close to substrate surface.For p-well, the present embodiment preferably first uses 70keV energy injection 4 × 1011cm-2Boron Ion, then the energy injection 1 × 10 with 33keV11cm-2Boron ion, as shown in Fig. 2 (c)；It is preferred for N traps, the present embodiment First use 90keV energy injection 4 × 1012cm-2Phosphonium ion, then the energy injection 1 × 10 with 50keV12cm-2Phosphonium ion, such as Shown in Fig. 2 (d).
4) anneal, make impurity activation, can be in N2Atmosphere carries out 500 DEG C of 60s annealing.
5) remove the masking layer of substrate surface, the HF of dilution can be used.The present embodiment is with dilute HF (HF:H2O=1:30) float 30~55s, as shown in Fig. 2 (e).
6) by lithographic definition isolation channel, etching forms the deep grooves of 300~500nm, the present embodiment for etching 300nm every From groove, as shown in Fig. 2 (f).
7) 400~500nm field oxide, such as SiO are deposited2, Al2O3, Y2O3Deng, deposit method have PVD, PLD, PECVD or ICPCVD etc., the present embodiment are the SiO that 400nm is deposited using PECVD method2, as shown in Fig. 2 (g).
8) lithographic definition active area, can be by the method for dry etching+wet etching or wet etching, the present embodiment ~350nm SiO is etched away with the method for dry etching2, then the SiO of method corrosion~50nm with wet etching2, formed such as Shown in Fig. 2 (h).
9) sacrificing the method for oxidation improves substrate surface for roughness, and method is as follows：Substrate is first immersed in concentration as 30% H2O2Middle 30s, 1min is rushed with deionized water, then substrate is immersed in 1min in the HCl that concentration is 36%, rushed with deionized water 1min；So repeat 3~4 cycles.
10) GeOx (wherein 0 is formed<X≤2) passivation layer, the method for formation has：Thermal oxide, oxygen plasma oxidation, ozone Oxidation or deposit.The method that the present embodiment uses thermal oxide, in 400 DEG C of O2Ambient anneal 3min, form GeOx (wherein 0< X≤2), as shown in Fig. 2 (i).
11) gate medium of deposit, material have：Al2O3、Y2O3、HfO2、ZrO2、GeO2、La2O3Deng, but be not limited to above-mentioned Dielectric material.The method of deposit has ALD, PVD, MBE, PLD, MOCVD, PECVD or ICPCVD etc., but is not limited to above-mentioned deposit Method.The thickness of deposit medium is 1.5~5nm, and the present embodiment is that ALD method deposits 3nm Al2O3.Deposit can be in N2、 O2Etc. being annealed in atmosphere, but above-mentioned annealing atmosphere is not limited to, as shown in Fig. 2 (j).
12) gate electrode is deposited, gate electrode can use polysilicon gate, metal gate or FUSI grid, and the present embodiment uses 50nm TiNxAs grid metal, as shown in Fig. 2 (k).
13) protective layer SiO is deposited2Thickness be 10~20nm, the method for deposit has PVD, PLD, PECVD or ICPCVD Deng.The present embodiment deposits 10nm SiO using ALD method2, as shown in Fig. 2 (l).
14) lithographic definition nmos device region, the SiO in the region is removed2And grid metal, as shown in Fig. 2 (m).
15) lithographic definition nmos device active area, can by the method for dry etching+wet etching or wet etching, The present embodiment is that~350nm SiO is etched away with the method for dry etching2, then with method corrosion~50nm's of wet etching SiO2, formed as shown in Fig. 2 (n).
16) sacrificing the method for oxidation improves substrate surface for roughness, and method is as follows：Substrate is first immersed in concentration as 30% H2O2Middle 30s, 1min is rushed with deionized water, then substrate is immersed in 1min in the HCl that concentration is 36%, rushed with deionized water 1min；So repeat 3~4 cycles.
17) nitrogen plasma treatment, NH can be used3The method of thermal annealing or nitrogen plasma treatment.The present embodiment nitrogen The method of corona treatment, the ICP radio frequency sources carried using ALD are produced nitrogen plasma, power 300W, handle 2min, Form one layer of GeOxNy(wherein 0<x<3/2,0<y<4/3) passivation layer, as shown in Fig. 2 (o).
18) gate medium of deposit, material have：Al2O3、Y2O3、HfO2、ZrO2、GeO2、La2O3Deng, but be not limited to above-mentioned Dielectric material.The method of deposit has ALD, PVD, MBE, PLD, MOCVD, PECVD or ICPCVD etc., but is not limited to above-mentioned deposit Method.The thickness of deposit medium is 1.5~5nm, and the present embodiment is that ALD method deposits 3nm Al2O3.Deposit can be in N2、 O2Etc. being annealed in atmosphere, but above-mentioned annealing atmosphere is not limited to, as shown in Fig. 2 (p).
19) gate electrode is deposited, gate electrode can use polysilicon gate, metal gate or FUSI grid, and the present embodiment uses 50nm TiNxAs grid metal, as shown in Fig. 2 (q).
20) grid metal in photoetching protection nmos device region, etching remove the grid metal in other regions, then with dilution HF removes protective layer SiO2, as shown in Fig. 2 (r).
21) photoetching, etching form patterned gate electrode, as shown in Fig. 2 (s).
22) side wall is formed.Side wall can be by depositing SiO2Or SiNxAnd etch and form side wall, can also use first SiO2SiN againxBilateral wall.The method of deposit has ALD, PVD, MBE, PLD, MOCVD, PECVD or ICPCVD etc., but does not limit to In above-mentioned deposition process.The present embodiment deposits 30nm SiN using PECVD methodx, as shown in Fig. 2 (t).Etch to be formed again Side wall, as shown in Fig. 2 (u)；
23) PMOSFET source and drain is injected, and the dosage for injecting B is 1E15~5E15cm-2, Implantation Energy is 5~40keV, this reality Apply to inject 1E15cm-2B, Implantation Energy 15keV, as shown in Fig. 2 (v)；NMOSFET source and drain is injected, and the dosage for injecting P is 1E15~5E15cm-2, Implantation Energy is 5~40keV, is originally embodied as injecting 1E15cm-2P, Implantation Energy 15keV, such as scheme Shown in 2 (w).
24) separation layer SiO is deposited2, as shown in Fig. 2 (x).Perforate is carried out afterwards, deposits contacting metal.
The present invention is described in detail above by specific embodiment.It is it will be understood by those of skill in the art that described above Only the particular embodiment of the present invention, in the scope for not departing from essence of the invention, other materials can be used to realize the present invention Preparation process, can also use same method be obtained in other Semiconductor substrates in embodiment outside germanium substrate equally Effect, preparation method are not limited to the content disclosed in embodiment, all equivalent changes done according to the claims in the present invention with Modification, it should all belong to the covering scope of the present invention.

Claims (10)

1. a kind of germanium base CMOS preparation method, comprises the following steps：
1) on germanium base substrate trap preparation, i.e. N traps and p-well：
1-1) germanium base substrate is cleaned, the deposit injection masking layer on germanium base substrate；
1-2) impurity needed for injection and activation；
1-3) remove injection masking layer；
2) isolation structure is formed：
2-1) place isolation channel is formed；
2-2) field oxide deposits；
3) PMOS device structure is formed：
3-1) PMOS device active area perforate, improve substrate surface for roughness with the method for sacrificing oxidation；
3-2) GeOx passivation layers are formed, wherein 0<x≤2；
3-3) deposit gate medium；
3-4) deposit gate electrode；
4) protective layer SiO is deposited2；
5) SiO of nmos device overlying regions is removed2And grid metal；
6) nmos device structure is formed：
6-1) nmos device active area perforate, improve substrate surface for roughness with the method for sacrificing oxidation；
6-2) nitrogen passivation is formed；
6-3) deposit gate electrode；
6-4) deposit grid metal；
6-5) the grid metal in photoetching protection nmos device region, removes remaining region gate electrode, and the protective layer SiO of lower section2；
7) patterned gate electrode is formed：
8) source, leakage and contact are formed：
8-1) form sidewall structure；
8-2) source, leakage injection and activation；
8-3) separation layer deposit, perforate, deposit contacting metal.
2. preparation method as claimed in claim 1, it is characterised in that step 1-1) in, germanium base substrate is body Ge substrates, silicon Upper extension germanium substrate or GeOI substrates, situation, doping concentration are adulterated for the germanium base substrate<1×15cm-3；To germanium base substrate Surface is cleaned, and removes surface contamination and natural oxidizing layer, then deposits injection masking layer, and injection masking layer material is SiO2、 Al2O3Or Y2O3, its thickness is 5~20nm, masking layer material deposition methods have ALD, PVD, MBE, PLD, MOCVD, PECVD or ICPCVD。
3. preparation method as claimed in claim 1, it is characterised in that step 1-2) in, the preparation for p-well, generally note Enter boron ion；Preparation for N traps, is usually injected into phosphonium ion；The depth and concentration of implantation dosage and energy trap as needed Depending on, the implantation dosage of boron ion is 5 × 1010~1 × 1014cm-2, Implantation Energy is 30keV~120keV；The note of phosphonium ion Enter dosage for 5 × 1010~1 × 1014cm-2, Implantation Energy is 50keV~180keV.
4. preparation method as claimed in claim 1, it is characterised in that step 3-2) in, the formation of GeOx passivation layers, use Thermal oxide, oxygen plasma oxidation, the method for ozone oxidation or deposit, the thickness for forming GeOx is 0.5~2nm.
5. preparation method as claimed in claim 1, it is characterised in that step 6-1) in, improved with the method for sacrificing oxidation Substrate surface for roughness, specific method are as follows：Substrate is first immersed in the H that concentration is 30%2O2Middle 30s, is rushed with deionized water 1min, then substrate is immersed in 1min in the HCl that concentration is 36%, rush 1min with deionized water；So repeat 3~4 cycles.
6. preparation method as claimed in claim 1, it is characterised in that step 6-2) in, using NH3Thermal annealing or nitrogen etc. from The method of daughter processing realizes that nitrogen passivation is formed.
7. preparation method as claimed in claim 1, it is characterised in that the gate dielectric material of above-mentioned deposit is Al2O3、Y2O3、 HfO2、ZrO2Or La2O3, the method for deposit has ALD, MBE, PLD or MOCVD, and the thickness for depositing gate medium is 1.5~5nm.
8. preparation method as claimed in claim 1, it is characterised in that above-mentioned gate electrode using polysilicon gate, metal gate or Person's FUSI grid, the method for deposit have ALD, PVD, PLD, MOCVD, PECVD or LPCVD.
9. preparation method as claimed in claim 1, it is characterised in that step 8-1) in, by depositing SiO2Or SiNxAnd Etching forms side wall, or uses first SiO2SiN againxBilateral wall.
10. preparation method as claimed in claim 1, it is characterised in that step 8-2) source, leakage injection dosage, for The dosage of PMOSFETs, B injection is 5E14~5E15cm-2, Implantation Energy is 10~20keV；For NMOSFETs, P note The dosage entered is 5E14~5E15cm-2, Implantation Energy is 20~50keV, for source, the activation of leakage impurity, in N2Atmosphere is carried out 500 DEG C of 60s annealing.
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