CN101350332B - 具有边缘支撑环的超薄晶片及其制造方法 - Google Patents
具有边缘支撑环的超薄晶片及其制造方法 Download PDFInfo
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- CN101350332B CN101350332B CN2008101295052A CN200810129505A CN101350332B CN 101350332 B CN101350332 B CN 101350332B CN 2008101295052 A CN2008101295052 A CN 2008101295052A CN 200810129505 A CN200810129505 A CN 200810129505A CN 101350332 B CN101350332 B CN 101350332B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- 235000012431 wafers Nutrition 0.000 title claims description 126
- 238000000034 method Methods 0.000 title abstract description 40
- 238000003801 milling Methods 0.000 claims description 70
- 238000013459 approach Methods 0.000 claims description 28
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- 238000003825 pressing Methods 0.000 claims description 6
- 229910001651 emery Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
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- 238000012545 processing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
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- 238000001311 chemical methods and process Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02035—Shaping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/880,455 US8048775B2 (en) | 2007-07-20 | 2007-07-20 | Process of forming ultra thin wafers having an edge support ring |
US11/880,455 | 2007-07-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101350332A CN101350332A (zh) | 2009-01-21 |
CN101350332B true CN101350332B (zh) | 2012-03-28 |
Family
ID=40264159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008101295052A Active CN101350332B (zh) | 2007-07-20 | 2008-06-23 | 具有边缘支撑环的超薄晶片及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8048775B2 (zh) |
CN (1) | CN101350332B (zh) |
TW (1) | TWI413208B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105390383A (zh) * | 2014-08-26 | 2016-03-09 | 株式会社迪思科 | 晶片的加工方法 |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060145312A1 (en) * | 2005-01-05 | 2006-07-06 | Kai Liu | Dual flat non-leaded semiconductor package |
US7884454B2 (en) * | 2005-01-05 | 2011-02-08 | Alpha & Omega Semiconductor, Ltd | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package |
US7898092B2 (en) * | 2007-11-21 | 2011-03-01 | Alpha & Omega Semiconductor, | Stacked-die package for battery power management |
JP2009096698A (ja) * | 2007-10-19 | 2009-05-07 | Toshiba Corp | ウェーハ及びその製造方法 |
US8164199B2 (en) * | 2009-07-31 | 2012-04-24 | Alpha and Omega Semiconductor Incorporation | Multi-die package |
US9257375B2 (en) | 2009-07-31 | 2016-02-09 | Alpha and Omega Semiconductor Inc. | Multi-die semiconductor package |
JP5441587B2 (ja) * | 2009-09-25 | 2014-03-12 | 株式会社ディスコ | ウエーハの加工方法 |
FR2953064B1 (fr) * | 2009-11-20 | 2011-12-16 | St Microelectronics Tours Sas | Procede d'encapsulation de composants electroniques sur tranche |
US8987878B2 (en) | 2010-10-29 | 2015-03-24 | Alpha And Omega Semiconductor Incorporated | Substrateless power device packages |
CN102157426B (zh) * | 2011-01-28 | 2015-10-07 | 上海华虹宏力半导体制造有限公司 | 晶片支撑装置及晶片处理工艺 |
JP2012169487A (ja) * | 2011-02-15 | 2012-09-06 | Disco Abrasive Syst Ltd | 研削装置 |
US8987898B2 (en) * | 2011-06-06 | 2015-03-24 | International Rectifier Corporation | Semiconductor wafer with reduced thickness variation and method for fabricating same |
CN102226986B (zh) * | 2011-06-27 | 2013-01-16 | 天津环鑫科技发展有限公司 | 一种用于超薄半导体器件的制造方法 |
JP5796412B2 (ja) * | 2011-08-26 | 2015-10-21 | 三菱電機株式会社 | 半導体素子の製造方法 |
US8716067B2 (en) | 2012-02-20 | 2014-05-06 | Ixys Corporation | Power device manufacture on the recessed side of a thinned wafer |
CN103390539B (zh) * | 2012-05-11 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | 薄硅片的制备方法 |
CN103123913A (zh) * | 2012-07-03 | 2013-05-29 | 上海华力微电子有限公司 | 一种打薄晶圆降低分裂闪存单元失败率的工艺方法 |
US9368340B2 (en) | 2014-06-02 | 2016-06-14 | Lam Research Corporation | Metallization of the wafer edge for optimized electroplating performance on resistive substrates |
US9966293B2 (en) | 2014-09-19 | 2018-05-08 | Infineon Technologies Ag | Wafer arrangement and method for processing a wafer |
CN106158580B (zh) * | 2015-03-25 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | 晶圆减薄方法 |
TWI588880B (zh) * | 2016-06-28 | 2017-06-21 | 昇陽國際半導體股份有限公司 | 晶圓薄化製程 |
JP6791579B2 (ja) * | 2016-09-09 | 2020-11-25 | 株式会社ディスコ | ウェーハ及びウェーハの加工方法 |
JP6460074B2 (ja) * | 2016-10-07 | 2019-01-30 | トヨタ自動車株式会社 | 半導体ウエハと半導体素子の製造方法 |
US20200321236A1 (en) * | 2019-04-02 | 2020-10-08 | Semiconductor Components Industries, Llc | Edge ring removal methods |
US20210013176A1 (en) * | 2019-07-09 | 2021-01-14 | Semiconductor Components Industries, Llc | Pre-stacking mechanical strength enhancement of power device structures |
USD917825S1 (en) * | 2019-07-16 | 2021-04-27 | Entegris, Inc. | Wafer support ring |
JP7391476B2 (ja) * | 2020-03-17 | 2023-12-05 | 株式会社ディスコ | 研削方法 |
CN111863596B (zh) * | 2020-07-21 | 2023-05-26 | 绍兴同芯成集成电路有限公司 | 一种晶圆的铜柱与厚膜镀铜结构的制造工艺 |
US11626371B2 (en) | 2020-12-28 | 2023-04-11 | Infineon Technologies Ag | Semiconductor structure with one or more support structures |
US11837632B2 (en) * | 2021-03-24 | 2023-12-05 | Globalwafers Co., Ltd. | Wafer |
JP2022166513A (ja) * | 2021-04-21 | 2022-11-02 | 富士電機株式会社 | 半導体装置の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04263425A (ja) * | 1991-02-18 | 1992-09-18 | Toshiba Corp | 半導体基板の研削装置及び研削方法 |
US6162702A (en) | 1999-06-17 | 2000-12-19 | Intersil Corporation | Self-supported ultra thin silicon wafer process |
JP4878738B2 (ja) * | 2004-04-30 | 2012-02-15 | 株式会社ディスコ | 半導体デバイスの加工方法 |
US7507638B2 (en) * | 2004-06-30 | 2009-03-24 | Freescale Semiconductor, Inc. | Ultra-thin die and method of fabricating same |
US7066792B2 (en) * | 2004-08-06 | 2006-06-27 | Micron Technology, Inc. | Shaped polishing pads for beveling microfeature workpiece edges, and associate system and methods |
US7314767B2 (en) * | 2005-05-27 | 2008-01-01 | Credence Systems Corporation | Method for local wafer thinning and reinforcement |
JP4731241B2 (ja) * | 2005-08-02 | 2011-07-20 | 株式会社ディスコ | ウエーハの分割方法 |
-
2007
- 2007-07-20 US US11/880,455 patent/US8048775B2/en active Active
-
2008
- 2008-06-23 CN CN2008101295052A patent/CN101350332B/zh active Active
- 2008-06-24 TW TW097123615A patent/TWI413208B/zh active
-
2011
- 2011-05-24 US US13/115,097 patent/US8507362B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105390383A (zh) * | 2014-08-26 | 2016-03-09 | 株式会社迪思科 | 晶片的加工方法 |
CN105390383B (zh) * | 2014-08-26 | 2020-03-17 | 株式会社迪思科 | 晶片的加工方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101350332A (zh) | 2009-01-21 |
TWI413208B (zh) | 2013-10-21 |
US8507362B2 (en) | 2013-08-13 |
US8048775B2 (en) | 2011-11-01 |
US20110223742A1 (en) | 2011-09-15 |
US20090020854A1 (en) | 2009-01-22 |
TW200905789A (en) | 2009-02-01 |
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C06 | Publication | ||
PB01 | Publication | ||
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SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170619 Address after: Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407 Patentee after: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Address before: Bermuda Hamilton No. 22 Vitoria street Canon hospital Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. |
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TR01 | Transfer of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Ultra thin wafers having an edge support ring and manufacture method thereof Effective date of registration: 20191210 Granted publication date: 20120328 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20120328 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
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PC01 | Cancellation of the registration of the contract for pledge of patent right |