CN101344862A

CN101344862A - Anti-interference equipment of embedded system

Info

Publication number: CN101344862A
Application number: CNA200810146460XA
Authority: CN
Inventors: 黄久松
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2008-09-01
Filing date: 2008-09-01
Publication date: 2009-01-14
Anticipated expiration: 2028-09-01
Also published as: CN101344862B

Abstract

The embodiment of the invention discloses an anti-jamming device, comprising: a watchdog timer, which is used for presetting a threshold value, and when the count reaches the threshold value, outputting an overflow signal to a control unit; the control unit, which comprises a configuration control circuit and a reset control circuit, wherein, the configuration control circuit is used for the configuration of the watchdog timer by the CPU and the reset control circuit is used for sending a reset signal to the CPU when the watchdog timer overflows; and an electrification reset unit, which is used for generating the reset signal, in case of power supply abnormality, and providing the reset signal to the control unit. In the invention, the SOC internal watchdog circuit is independent from the CPU clock and combined with a POR circuit to improve the reliability, can supersede the special watchdog chip in the system, thus reducing the system implementation cost; in addition, the device of the invention maintains the configurable property of internal watchdogs, thus improving the flexibility and the reliability of system configuration.

Description

Anti-interference equipment in a kind of embedded system

Technical field

The present invention relates to communication technical field, relate in particular to the anti-interference equipment in a kind of embedded system.

Background technology

It is anti-interference generally to adopt watchdog circuit to carry out in the embedded system, and watchdog circuit comprises counter and control circuit.During the embedded system operate as normal, the CPU of embedded system (Central ProcessingUnit, CPU (central processing unit)) at regular intervals the counter of watchdog circuit is carried out zero clearing, be called and feed dog, under normal circumstances, embedded system is fed the time interval the overflowing the time less than counter of dog, watchdog chip can not reset to embedded system, embedded system can operate as normal, behind system exception, the CPU of embedded system can not normally carry out dog feeding operation, what surpass setting feeds dog after the time, and counter overflows, and forces embedded system to reset, restart and normally operation, thereby guarantee that embedded system is from software, return to normal operation in the hard error.

At present, adopt SOC (System On Chip, system level chip) to add watchdog chip in the Embedded system usually and realize, as shown in Figure 1.CPU feeds dog by I/O (I/O) pin, the output RESET that resets of watchdog chip directly gives SOC chip or cpu chip as reset signal, also can between watchdog chip and SOC chip or cpu chip, add steering logic, increase the dirigibility of system.During system exception, CPU fails to feed dog in official hour, and watchdog chip is then exported reset signal, and total system resets.

For increasing the watchdog chip scheme outside the SOC chip, level of integrated system is lower, has both increased the cost of system, increases the area overhead of veneer again.In addition, the outer watchdog chip is fed the dog time and is fixed, and the priority that CPU must feed the dog task improves, and feeds dog with higher frequency, just can avoid other tasks to occupy CPU for a long time and stops to feed dog, causes that system is improper to be resetted, thereby CPU efficient reduces.

Along with the continuous development of integrated circuit technique, integrated level constantly rises, integrated internal digital house dog in the now more SOC chip, as shown in Figure 2.Mode of operation and the outer watchdog chip of inner integrated digital house dog are basic identical, owing to realize that in chip resource is unrestricted, watchdog circuit can be accomplished flexible configuration.

Though combine the high and advantage flexibly of integrated level at the integrated watchdog circuit of SOC chip internal, combine too closely with CPU, the reliability of this circuit is lowered.Mainly show as: inner integrated digital house dog is digital house dog, can't supervision system power unusual, therefore normal resetting system; When some is unusual, also may cause system not to be reset, when losing as the chip major clock, house dog can't be worked, and system can not be reset; When CPU configuration house dog, when program exception takes place, there is the risk of closing WDT (Watch Dog Timer, WatchDog Timer) function in CPU.

Therefore, the built-in watchdog circuit of the higher SOC of a kind of reliability need be provided.

Summary of the invention

The embodiment of the invention provides the anti-interference equipment in a kind of embedded system, being independent of the used clock of CPU, and improves its reliability in conjunction with por circuit, reduces the realization cost of system.

The embodiment of the invention provides the anti-interference equipment in a kind of embedded system, comprising: WatchDog Timer, control module, and electrification reset unit, wherein:

Described WatchDog Timer is used for default threshold value, and when counting reached described threshold value, the output spill over was given control module;

Described control module comprises configuration control circuit and reset control circuit, and wherein said configuration control circuit is used to realize the configuration of CPU to described WatchDog Timer; When described reset control circuit is used for described WatchDog Timer and overflows, send reset signal to described CPU;

Described electrification reset unit is used for producing reset signal when abnormity of power supply, offers described control module.

Compared with prior art, the present invention has the following advantages:

In the embodiments of the invention, the built-in watchdog circuit of SOC is independent of all clocks of CPU and in conjunction with por circuit, improves its reliability and enables special-purpose watchdog chip in the alternative system, and the reduction system realizes cost; The configurable characteristics that keep built-in house dog simultaneously, the dirigibility and the reliability of increase system configuration.

Description of drawings

Fig. 1 is that available technology adopting SOC chip exterior increases the synoptic diagram that watchdog chip is realized watchdog circuit;

Fig. 2 is the synoptic diagram that available technology adopting SOC chip internal integrated digital house dog is realized watchdog circuit;

Fig. 3 is the synoptic diagram of watchdog circuit in the embodiment of the invention;

Fig. 4 is the synoptic diagram of WatchDog Timer in the embodiment of the invention;

Fig. 5 is the configuration control circuit synoptic diagram that comprises in the control module in the embodiment of the invention:

Fig. 6 is the reset control circuit synoptic diagram that comprises in the control module in the embodiment of the invention.

Embodiment

The embodiment of the invention provides a kind of anti-interference equipment, as shown in Figure 3, comprising: electrification reset unit 10, WatchDog Timer 20, clock generating unit 30, control module 40.

Electrification reset unit (POR) 10 is used for when abnormity of power supply, during such as chip power or supply voltage reduction, produces a reset signal, and this reset signal is offered control module 40;

WatchDog Timer (WDT) 20 is used for default threshold value, when counting reaches threshold value, exports a spill over and gives control module 40;

Clock generating unit 30, be used to the built-in device of this anti-interference equipment that a clock signal that is independent of CPU is provided, thereby when the clock signal of CPU occurs when unusual, the watchdog circuit of the embodiment of the invention can not be affected, in embodiments of the present invention, described clock generating unit 30 can adopt the RC oscillator;

Control module (CTRL) 40 is used to control the config update of watchdog circuit and the output that resets.

Wherein, in embodiments of the present invention, described clock generating unit 30 and electrification reset unit 10 are mimic channel, and WatchDog Timer 20 and control module 40 are digital circuit.

Further, as shown in Figure 4, WatchDog Timer 20 comprises:

Counter 200 is used to realize zero clearing, and the clear terminal of counter 200 links to each other with outside feeding-dog signal, and when CPU fed dog, counter 200 resetted, and when CPU fed dog and finishes, counter 200 beginnings were from adding counting until feeding dog once more or to the thresholding of setting;

Thresholding obtains subelement 210, is used for obtaining from control module 40 the counting threshold value of counter 200;

Overflow indication subelement 220, be used for that thresholding obtains the threshold value that subelement 210 obtains and when not taking place to feed the dog incident, prompting counter 200 overflows, and the generation spill over is given control module 40 when counter 200 count down to.

Further, control module 40 comprises:

Configuration control circuit and reset control circuit.Wherein, the configuration control circuit is used to realize the configuration of CPU to described WatchDog Timer 20, as shown in Figure 5, described configuration control circuit comprises original configuration register 400, configuration save register 410 and configuration enabled device 420, wherein original configuration register 400 and configuration keep the figure place of register 410 to be determined by the figure place of configuration signal, and promptly original configuration register 400 is identical with the figure place of figure place that disposes maintenance register 410 and configuration signal.

Original configuration register 400 communicates to connect with CPU, is used to receive and preserve the original configuration information of the watchdog circuit that CPU sends.

Configuration keeps register 410, communicates to connect with original configuration register 400, and isolated with CPU, the configuration information when being used to preserve the watchdog circuit real work.

Wherein, have only when configuration enabled device 420 is opened, the configuration information in the original configuration register 400 just can be updated to configuration and keep in the register 410; When configuration enabled device 420 was closed, CPU only can change the original configuration information in the original configuration register 400, thereby had avoided the configuration parameter of CPU unexpected change house dog when work.

Wherein, when reset control circuit is used for described WatchDog Timer 20 and overflows, send reset signal, as shown in Figure 6, comprising to described CPU:

Reseting signal generating device 430 is used for when the high level spill over negate of WatchDog Timer 20, with the significant level reset signal of electrify restoration circuit output with, produce a low level reset signal.The low level reset signal of above-mentioned generation and the high level inhibit signal of external terminal mutually or export a low level reset signal, this low level reset signal also can be used as the reset signal output of total system as the reset signal of SOC chip.When being used for described WatchDog Timer and overflowing, send reset signal to described CPU

As seen, the configuration signal of watchdog circuit comprises configuration informations such as the threshold value, working method of counter 200 in the WatchDog Timer 20, and does not comprise that house dog is forbidden or enable information, and promptly watchdog circuit can not be closed by CPU.In addition, the outside inhibit signal of watchdog circuit is used to forbid WatchDog Timer 20 and clock generating unit 30 simultaneously.When the inner house dog of SOC was forbidden by external terminal, its reset signal no longer outputed to system.

The clock generation circuit that the internal clocking generation unit can also be changed into other in the embodiment of the invention separates with the clock of realizing watchdog circuit and other circuit of SOC, just no longer gives unnecessary details herein.

In the embodiments of the invention, provide a kind of anti-interference equipment, in this anti-interference equipment, comprise the electrification reset unit, when abnormity of power supply, produce a reset signal, with the influence of the power supply of avoiding the SOC chip this anti-interference equipment.Further, also comprise clock generating unit in this anti-interference equipment, make the clock in this anti-interference equipment be independent of the used clock of CPU, this anti-interference equipment is independent of other circuit of SOC, this clock generating unit occurs when unusual in the clock signal of CPU, clocking is given this anti-interference equipment, with the influence to this anti-interference equipment of the clock signal of avoiding CPU.

Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential general hardware platform, can certainly pass through hardware, but the former is better embodiment under a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium, comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.

More than disclosed only be several specific embodiment of the present invention, still, the present invention is not limited thereto, any those skilled in the art can think variation all should fall into protection scope of the present invention.

Claims

1, the anti-interference equipment in a kind of embedded system is characterized in that, comprise WatchDog Timer, control module, reach the electrification reset unit, wherein:

2, the anti-interference equipment in the embedded system as claimed in claim 1 is characterized in that, described WatchDog Timer has and comprises:

Counter, the clear terminal of described counter links to each other with outside feeding-dog signal, when CPU feeds dog, counter reset; When CPU fed dog and finishes, counter began from adding counting until feeding dog once more or to the thresholding of setting;

Thresholding obtains subelement, is used to obtain the counting threshold value of being set by control module;

Overflow the indication subelement, be used for when rolling counters forward arrives described counting threshold value and do not take place to feed the dog incident, counter overflows and produces spill over gives described control module.

3, the anti-interference equipment in the embedded system as claimed in claim 1 is characterized in that, described configuration control circuit also comprises:

Configuration keeps register, the configuration information when being used to preserve the watchdog circuit real work;

The original configuration register is used for preserving CPU to the original configuration information of watchdog circuit and according to the configuration information of the described configuration save register of described original configuration information updating; And

The configuration enabled device;

Wherein, have only when described configuration enabled device is in open mode, the configuration information in the described configuration save register just can upgrade.

4, the anti-interference equipment in the embedded system as claimed in claim 1 is characterized in that, described reset control circuit specifically comprises:

Reseting signal generating device, the significant level reset signal and the generation one low level reset signal of the high level spill over negate that is used for WatchDog Timer and electrify restoration circuit output.

5, the anti-interference equipment in the embedded system as claimed in claim 1 is characterized in that, described anti-interference equipment also comprises clock generating unit, is used to described anti-interference equipment that the clock signal that is independent of CPU is provided.

6, the anti-interference equipment in the embedded system as claimed in claim 5 is characterized in that, described clock generating unit is the RC oscillator.